CN219085970U

CN219085970U - Chip packaging structure

Info

Publication number: CN219085970U
Application number: CN202320106485.7U
Authority: CN
Inventors: 魏耀铖; 王兆攀
Original assignee: Hunan Yuemo Advanced Semiconductor Co ltd
Current assignee: Hunan Yuemo Advanced Semiconductor Co ltd
Priority date: 2023-02-03
Filing date: 2023-02-03
Publication date: 2023-05-26
Anticipated expiration: 2033-02-03

Abstract

The utility model belongs to the technical field of semiconductor packaging, and discloses a chip packaging structure. The chip packaging structure comprises a chip and a substrate, wherein the chip comprises a first chip and a second chip; the substrate comprises a first substrate and a second substrate; the first chip, the first substrate, the second chip and the second substrate are arranged in a stacked mode in the vertical direction, the first chip is electrically connected to the first substrate, the second chip is electrically connected to the second substrate, and the length and/or width of the first substrate is smaller than that of the second substrate, so that the end portion of the second substrate can protrude out of the end portion of the first substrate in the horizontal direction, and the upper surface of the first substrate and the upper surface of the second substrate can be electrically connected through the lead. The chip packaging structure provided by the utility model can simplify the packaging process, improve the efficiency and reduce the packaging cost while ensuring that the leads are reliably connected with the substrate.

Description

Chip packaging structure

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a chip packaging structure.

Background

A chip is a general term for semiconductor device products, and is a way to miniaturize a circuit. The chip package can connect the chip with other devices and has the functions of fixing and protecting the chip.

Under the trend of electronic components toward integration and miniaturization, the size and capacity of chips are increased, and the occupation of the whole space needs to be reduced. Therefore, the connection mode of the chip and the substrate is continuously improved, such as: the chip package is realized in a package stacking mode, so that the substrate can be fully and reasonably utilized, and the capacity of the chip can meet the requirement.

In the prior art, as shown in fig. 1, the package stack typically welds an SSD (i.e., solid state disk) chip 11 ' on a first substrate 21 ' by solder 6 '; the front surface of the NAND (i.e. the computer flash memory device) memory chip 12 ' is welded on the second substrate 22 ', and the back surface of the NAND memory chip 12 ' is connected with the first substrate 21 ' through the colloid 5 '; then, the whole plastic package body 4 'is subjected to metal spraying treatment to form a metal spraying layer 41', and then the surface of the plastic package body 4 'provided with the circuit external contact is subjected to laser grooving so as to electrically connect the ends of the first substrate 21' and the second substrate 22 'through the lead 3'.

Because the first substrate 21 'and the second substrate 22' in the prior art have the same size, the ends of the first substrate 21 'and the second substrate 22' are flush, and the lead 3 'is required to be grooved after metal spraying in order to protect the lead 3', so that the lead 3 'is not excessively protruded out of the outer surface of the plastic package body 4' while being reliably connected, but the whole packaging process is complicated, the efficiency is not improved, and the packaging processing cost is increased.

Disclosure of Invention

The utility model aims to provide a chip packaging structure which can simplify the packaging process, improve the efficiency and reduce the packaging cost while ensuring the reliable connection of leads.

To achieve the purpose, the utility model adopts the following technical scheme:

a chip package structure, comprising:

the chip comprises a first chip and a second chip;

a substrate including a first substrate and a second substrate;

the first chip, the first substrate, the second chip and the second substrate are stacked in the vertical direction, the first chip is electrically connected to the first substrate, the second chip is electrically connected to the second substrate, and the length and/or width of the first substrate is smaller than the length and/or width of the second substrate, so that the end part of the second substrate can protrude out of the end part of the first substrate in the horizontal direction, and the upper surface of the first substrate and the upper surface of the second substrate are electrically connected through a lead.

Optionally, a first electrical contact is disposed on the upper surface of the first substrate, a second electrical contact is disposed on the upper surface of the second substrate, and two ends of the lead wire are respectively connected with the first electrical contact and the second electrical contact, so that the first substrate and the second substrate are electrically connected.

Optionally, the first electrical contact is disposed on the upper surface of the first substrate and is spaced from the first chip in a horizontal direction; the second electric contact is arranged on the upper surface of the second substrate and is arranged at intervals with the second chip in the horizontal direction.

Optionally, the first chip is connected with the first substrate in a welding way; the second chip is connected with the second substrate in a welding way.

Optionally, the first chip is an SSD chip.

Optionally, the second chip is connected with the first substrate through colloid.

Optionally, two second chips are provided, and the two second chips are horizontally arranged on the second substrate at intervals.

Optionally, the second chip is a NAND memory chip.

Optionally, the packaging structure further comprises a plastic package body, wherein the plastic package body is packaged outside the chip and the substrate.

Optionally, the plastic package body is an epoxy plastic package material.

The beneficial effects are that:

according to the chip packaging structure, the first chip, the first substrate, the second chip and the second substrate are arranged in a stacked manner in the vertical direction to realize packaging stacking, so that the requirements on the capacity of the chip and the overall miniaturization are met; the first chip is electrically connected to the first substrate, the second chip is electrically connected to the second substrate, and the length and/or width of the first substrate is smaller than the length and/or width of the second substrate, so that the end part of the second substrate can protrude out of the end part of the first substrate in the horizontal direction after the chip packaging structure is assembled, and leads can be respectively connected to the upper surfaces of the first substrate and the second substrate, and reliable electrical connection of the first substrate and the second substrate is realized; because the end parts of the first substrate and the second substrate are arranged in a staggered manner, a space can be reserved for the lead, the lead can be packaged in the package without being exposed, and the protection effect on the lead is realized without metal spraying and slotting during packaging, so that the packaging process can be simplified, the process difficulty is reduced, the packaging efficiency is improved, and the packaging cost is reduced.

Drawings

FIG. 1 is a schematic diagram of a prior art chip package structure;

FIG. 2 is a schematic diagram of a connection between a chip and a substrate according to an embodiment of the present utility model;

FIG. 3 is a schematic diagram of a chip, a substrate and a lead connection according to an embodiment of the present utility model;

fig. 4 is a schematic diagram of a chip package structure after plastic packaging according to an embodiment of the present utility model.

In the figure:

11', SSD chip; 12', a NAND memory chip; 21', a first substrate; 22', a second substrate; 3', a lead wire; 4', plastic package; 41', a metal spraying layer; 5', colloid; 6', solder;

1. a chip; 11. a first chip; 12. a second chip;

2. a substrate; 21. a first substrate; 22. a second substrate;

3. a lead wire; 4. a plastic package body; 5. a colloid; 6. solder.

Detailed Description

The utility model is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present utility model are shown in the drawings.

In the description of the present utility model, unless explicitly stated and limited otherwise, the terms "connected," "connected," and "fixed" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

In the present utility model, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.

In the description of the present embodiment, the terms "upper", "lower", "right", etc. orientation or positional relationship are based on the orientation or positional relationship shown in the drawings, and are merely for convenience of description and simplicity of operation, and do not indicate or imply that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the utility model. Furthermore, the terms "first," "second," and the like, are used merely for distinguishing between descriptions and not for distinguishing between them.

As shown in fig. 2 to 4, the chip package structure (hereinafter simply referred to as "package structure") provided in the present embodiment includes a chip 1 and a substrate 2, the chip 1 including a first chip 11 and a second chip 12; the substrate 2 includes a first substrate 21 and a second substrate 22; the first chip 11, the first substrate 21, the second chip 12 and the second substrate 22 are stacked in the vertical direction, the first chip 11 is electrically connected to the first substrate 21, the second chip 12 is electrically connected to the second substrate 22, and the length and/or width of the first substrate 21 is smaller than the length and/or width of the second substrate 22, so that the end portion of the second substrate 22 can protrude out of the end portion of the first substrate 21 in the horizontal direction, and the upper surface of the first substrate 21 and the upper surface of the second substrate 22 are electrically connected through the lead 3.

The packaging structure realizes packaging lamination through the lamination arrangement of the first chip 11, the first substrate 21, the second chip 12 and the second substrate 22 in the vertical direction so as to meet the requirement of the storage capacity of the chip 1 and the requirement of the whole volume miniaturization. Specifically, in this embodiment, the package structure sequentially includes the first chip 11, the first substrate 21, the second chip 12, and the second substrate 22 from top to bottom in the vertical direction, and in other embodiments, the stacking order may be replaced according to the actual situation, so that the package structure may be used as desired.

The first chip 11 is electrically connected to the first substrate 21, and the second chip 12 is electrically connected to the second substrate 22, so as to electrically connect the chip 1 and the substrate 2. In addition, the length and/or width of the first substrate 21 of the packaging structure is smaller than the length and/or width of the second substrate 22, so that after the packaging structure is assembled, the end part of the second substrate 22 can protrude out of the end part of the first substrate 21 in the horizontal direction, leads 3 can be respectively connected to the upper surfaces of the first substrate 21 and the second substrate 22, reliable electric connection of the first substrate 21 and the second substrate 22 is realized, and further electric connection between the chip 1 and the substrate 2 and between the first substrate 21 and the second substrate 22 is realized, so that the use requirement of the packaging structure is met. Compared with the mode of connecting the lead 3 ' on the side surfaces of the first substrate 21 ' and the second substrate 22 ' in fig. 1, the packaging structure can reserve space for the lead 3 due to the staggered arrangement of the end parts of the first substrate 21 and the second substrate 22, so that the lead 3 can be packaged inside without being exposed after the substrate 2 is electrically connected during packaging, the risk of damaging the lead 3 during packaging is reduced, the reliable protection of the lead 3 is realized, the protection of the exposed lead 3 is realized without the measures such as metal spraying, slotting and the like during packaging, the packaging step is simplified, the process difficulty during packaging is reduced, the packaging efficiency is improved, and the packaging cost is also reduced due to the reduction of the metal spraying step. It is understood that the dimensional parameters of the first substrate 21 and the second substrate 22 may be set according to practical situations.

Optionally, the package structure further includes a plastic package body 4, where the plastic package body 4 is wrapped outside the chip 1 and the substrate 2.

Alternatively, the molding body 4 is made of an epoxy molding material.

After the chip 1 is electrically connected with the substrate 2, the packaging structure is placed in a mold, and the plastic package body 4 is made by injecting epoxy plastic package material to realize the packaging of the packaging structure. Because the lengths and/or widths of the first substrate 21 and the second substrate 22 are different, the ends of the first substrate 21 and the second substrate 22 are arranged in a staggered manner, so that the lead 3 can be arranged at the position of the difference between the lengths of the two substrates 2, when the package is carried out by the plastic package body 4, the package structure can be directly packaged in the plastic package body 4, the possibility that the lead 3 is worn or blocked by a die and the like is reduced, the reliability of connection is ensured, and the step of spraying metal and grooving on the surface of the plastic package body 4 for arranging the lead 3 is omitted, so that the process flow is simplified.

Alternatively, in the present embodiment, the first chip 11 is solder-connected with the first substrate 21; the second chip 12 is solder-connected to the second substrate 22.

Solder 6 may be provided on the substrate 2 to be electrically connected with the lower surface of the chip 1. The chip 1 is connected with the substrate 2 through welding, so that the chip 1 and the substrate 2 can be reliably fixed, and meanwhile, the electric connection between the chip 1 and the substrate 2 is ensured, and the packaging structure can meet the requirement of signal transmission.

Optionally, the upper surface of the second chip 12 is connected to the first substrate 21 through the glue 5, so that a fixed connection between the first substrate 21 and the second substrate 22 can be achieved through the second chip 12. Since no signal transmission is required between the second chip 12 and the first substrate 21, the relative fixing effect is achieved through the colloid 5.

Optionally, two second chips 12 are provided, and the two second chips 12 are horizontally spaced apart on the second substrate 22.

In this embodiment, two second chips 12 are provided to increase the storage capacity, and the two second chips 12 are disposed at intervals in the horizontal direction to reduce the risk of performance degradation caused by mutual influence of heat dissipation and the like. It will be appreciated that the number and location of the chips 1 may be set as desired.

Preferably, the first chip 11 is an SSD chip and the second chip 12 is a NAND memory chip.

Optionally, the upper surface of the first substrate 21 is provided with a first electrical contact, the upper surface of the second substrate 22 is provided with a second electrical contact, and two ends of the lead 3 are respectively connected with the first electrical contact and the second electrical contact, so that the first substrate 21 and the second substrate 22 are electrically connected.

The first and second electrical contacts electrically connect the first substrate 21 and the second substrate 22 by the wire 3 through a wire bonding process. Preferably, the first electrical contact and the second electrical contact are pads, i.e. circuit external contacts. Compared with the connection of the leads 3 on the side of the substrate 2, the embodiment has the leads 3 on the upper surface of the substrate 2, and the area of the substrate 2 at the connection of the leads 3 is larger, thereby being more convenient for improving the connection reliability and reducing the operation difficulty.

Alternatively, the first electrical contact is disposed on the upper surface of the first substrate 21 and is spaced apart from the first chip 11 in the horizontal direction; the second electrical contacts are disposed on the upper surface of the second substrate 22 and spaced apart from the second chip 12 in the horizontal direction.

The first electric contact and the second electric contact are arranged at intervals with the chip 1, so that the damage risk to the chip 1 when the lead 3 is connected can be reduced, the connection difficulty can be reduced, and the influence of the chip 1 on the end connection of the lead 3 during connection is avoided.

In this embodiment, the centers of the first substrate 21 and the second substrate 22 are centrally disposed, and the leads 3 may be disposed on both sides of the chip 1. Specifically, the positions and the number of the leads 3, the first electrical contacts, and the second electrical contacts may be set according to the specific situation, and the electrical connection of the substrate 2 can be achieved without affecting the arrangement of the chip 1.

It is to be understood that the above examples of the present utility model are provided for clarity of illustration only and are not limiting of the embodiments of the present utility model. Various obvious changes, rearrangements and substitutions can be made by those skilled in the art without departing from the scope of the utility model. It is not necessary here nor is it exhaustive of all embodiments. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the utility model are desired to be protected by the following claims.

Claims

1. Chip packaging structure, its characterized in that includes:

a chip (1), the chip (1) comprising a first chip (11) and a second chip (12);

a substrate (2), the substrate (2) comprising a first substrate (21) and a second substrate (22);

the first chip (11), the first substrate (21), the second chip (12) and the second substrate (22) are arranged in a stacked mode in the vertical direction, the first chip (11) is electrically connected to the first substrate (21), the second chip (12) is electrically connected to the second substrate (22), and the length and/or width of the first substrate (21) is smaller than that of the second substrate (22), so that the end portion of the second substrate (22) can protrude out of the end portion of the first substrate (21) in the horizontal direction, and the upper surface of the first substrate (21) and the upper surface of the second substrate (22) are electrically connected through the lead (3).

2. The chip package structure according to claim 1, wherein a first electrical contact is provided on an upper surface of the first substrate (21), a second electrical contact is provided on an upper surface of the second substrate (22), and both ends of the lead (3) are connected to the first electrical contact and the second electrical contact, respectively, so that the first substrate (21) and the second substrate (22) are electrically connected.

3. The chip package structure according to claim 2, wherein the first electrical contact is provided on an upper surface of the first substrate (21) and is spaced apart from the first chip (11) in a horizontal direction; the second electric contact is arranged on the upper surface of the second substrate (22) and is arranged at intervals from the second chip (12) in the horizontal direction.

4. A chip package structure according to any one of claims 1-3, wherein the first chip (11) is solder-connected to the first substrate (21); the second chip (12) is connected with the second substrate (22) in a welding way.

5. A chip package structure according to any of claims 1-3, wherein the first chip (11) is an SSD chip.

6. A chip package according to any of claims 1-3, characterized in that the second chip (12) is connected to the first substrate (21) by means of a glue (5).

7. A chip package according to any one of claims 1-3, wherein two second chips (12) are provided, and two second chips (12) are horizontally arranged on the second substrate (22) at intervals.

8. A chip package structure according to any of claims 1-3, characterized in that the second chip (12) is a NAND memory chip.

9. The chip packaging structure according to claim 1, further comprising a plastic package body (4), wherein the plastic package body (4) is wrapped outside the chip (1) and the substrate (2).

10. The chip packaging structure according to claim 9, wherein the plastic package body (4) is an epoxy plastic package material.