CN106158779A - Low-power consumption semiconductor rectifying device - Google Patents

Low-power consumption semiconductor rectifying device Download PDF

Info

Publication number
CN106158779A
CN106158779A CN201610625996.4A CN201610625996A CN106158779A CN 106158779 A CN106158779 A CN 106158779A CN 201610625996 A CN201610625996 A CN 201610625996A CN 106158779 A CN106158779 A CN 106158779A
Authority
CN
China
Prior art keywords
heavily doped
lead
district
wire bar
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201610625996.4A
Other languages
Chinese (zh)
Inventor
陈伟元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Vocational University
Original Assignee
Suzhou Vocational University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Vocational University filed Critical Suzhou Vocational University
Priority to CN201610625996.4A priority Critical patent/CN106158779A/en
Publication of CN106158779A publication Critical patent/CN106158779A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165Reinforcing structures
    • H01L2224/02166Collar structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/291Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/3701Shape
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Abstract

The invention discloses a kind of low-power consumption semiconductor rectifying device, its diode chip for backlight unit includes that surface is provided with the heavily doped P-type monocrystalline silicon piece in heavily doped N-type district, heavily doped N-type district contacts with heavily doped P-type monocrystalline silicon piece, heavily doped N-type district is formed around groove, and groove is positioned at heavily doped P-type monocrystalline silicon piece and heavily doped N-type district surrounding and extends to the middle part of heavily doped P-type monocrystalline silicon piece;The surface of groove is coated with insulation passivation protection layer; this insulation passivation protection floor is extended to the marginal area on surface, heavily doped N-type district by channel bottom; surface, heavily doped P-type district covers the second metal level as another electrode, and the first arc-shaped recess district and the second arc-shaped recess district are oppositely arranged with the pin area of the first lead-in wire bar and the pin area of the second lead-in wire bar respectively.By the way, unnecessary scolding tin is averagely allocated by the present invention, it is ensured that uniform welding, adds the intensity of welding, make unnecessary scolding tin carried out again with, bonding area at least adds 15%.

Description

Low-power consumption semiconductor rectifying device
Technical field
The present invention relates to rectifying device field, particularly relate to a kind of low-power consumption semiconductor rectifying device.
Background technology
Low-power consumption semiconductor rectifying device is a kind of electronic device with unidirectional conduction electric current, existing low-power consumption semiconductor Rectifying device mainly deposits techniques below problem: on the one hand, and the internal material connected mode of device is mainly by weld tabs at high temperature Together with chip is securely attached to by lower thawing with lead-in wire, but copper lead-in wire and scolding tin are difficult to accomplish the fusion of 100%, usual core Sheet is 85% with being connected sheet efficient weld area, and this one end that goes between only has about 60%, causes when big electric current passes through, and electric current divides Cloth is uneven, reduces product and bears the ability of surge.
" weld " be rectifying device produce critical process, particularly diode-like rectifying device, be designed into chip and lead Electrical lead position whether carefully and neatly done, whether weld tabs repeats puts, furnace temperature temperature design is the most reasonable etc., the defective products that welding produces Accounting for defective products total amount and reach more than 80%, whether welding link processes the proper final quality directly affecting product, and this project i.e. exists Rectifying device product design and production technology carry out a series of improvement.Produce a new generation's diode rectifier.
On the other hand, in addition to high power device, common rectifying device chip is square, and weld tabs is circular.By height In temperature welding continuous tunnel furnace, weld tabs i.e. melts as liquid, respectively connection chip and conductive lead wire.Owing to weld tabs presents not after high temperature Regular shape, after thawing, four back gauges with chip are respectively less than 0.2mm, once chip and weld tabs position have slight inclination or Person's welding temperature and speed of welding have slight deviation, scolding tin fall to flow to the edge of chip, thus touch the another of chip Simultaneously, the scolding tin flow through will become a wire, and rectifying device directly becomes wire, forms short circuit and cannot use;Another Even if kind of a situation is that scolding tin is not exposed to chip edge, client in use produces high temperature makes weld tabs thawing also have State situation, cause client to lose increasing.
Summary of the invention
The technical problem that present invention mainly solves is to provide a kind of low-power consumption semiconductor rectifying device, and solder side obtains The expansion of more than 13%, makes chip area drop to 60-65mil from existing 80mil, do not affect overvoltage protection ability In the case of, chip cost have dropped 11%, and high power device welding machine yield reaches more than 97%.
For solving above-mentioned technical problem, the technical scheme that the present invention uses is: provide a kind of low-power consumption semiconductor whole Stream device, including being positioned at the first lead-in wire bar of epoxy packages body, the second lead-in wire bar, connecting sheet and diode chip for backlight unit, first draws Lines one end is provided with the Support being connected with diode chip for backlight unit, and described diode chip for backlight unit one end is by solder(ing) paste and this Support electricity Connecting, the first lead-in wire bar other end is the first pin area, and the first pin area is as the electric current transmission ends of commutator;Described connection sheet Two ends are respectively the first welding ends and the second welding ends;Described second lead-in wire bar one end is the weldering being connected with described first welding ends Meeting district, the second lead-in wire bar other end is the second pin area, and the second pin area is as the electric current transmission ends of commutator;Described connection sheet Second welding ends is electrically connected by solder(ing) paste with the diode chip for backlight unit other end;Described diode chip for backlight unit includes that surface is provided with heavy doping The heavily doped P-type monocrystalline silicon piece of N-type region, this heavily doped N-type district contacts with heavily doped P-type monocrystalline silicon piece, heavily doped N-type district surrounding Being provided with groove, groove is positioned at heavily doped P-type monocrystalline silicon piece and heavily doped N-type district surrounding and extends to heavily doped P-type monocrystalline silicon piece Middle part;The surface of described groove is coated with insulation passivation protection layer, and insulation passivation protection layer is extended to heavily doped by channel bottom The marginal area on miscellaneous N-type region surface, surface, heavily doped P-type district is coated with the second metal level as electrode;
Heavily doped N-type region inside described insulation passivation protection layer has a U-shaped groove, under this heavily doped N-type district Surface and be positioned at U-shaped groove and be arranged right below a downward lobe, the described heavily doped N-type district exposed and U-shaped groove Surface is coated with the first metal layer as electrode;A strip bulge insulation division, this bar shaped it is provided with bottom described epoxy packages body Protruding insulation division is between the first pin area and the second pin area, and the both side surface being positioned at strip bulge insulation division is respectively equipped with First arc-shaped recess district and the second arc-shaped recess district, the first arc-shaped recess district and the second arc-shaped recess district respectively with the first pin area It is oppositely arranged with the second pin area.
Preferably, between Support and first pin area of described first lead-in wire bar, region is provided with one first bending part, the The Support of one lead-in wire bar is less than the first pin area;Between weld zone and second pin area of described second lead-in wire bar, region is provided with One second bending part, the weld zone of the second lead-in wire bar is less than the second pin area;First welding ends of described connection sheet and the second weldering Connecing and be provided with the 3rd bending part between end, the first welding ends is less than the second welding ends.
Preferably, the both sides, weld zone of described second lead-in wire bar are provided with block.
Preferably, the area of the weld zone of described second lead-in wire bar is more than the area of described first welding ends.
The invention has the beneficial effects as follows: low-power consumption semiconductor rectifying device the most of the present invention, it is protected near described insulation passivation Heavily doped N-type region inside sheath has a U-shaped groove, this heavily doped N-type district lower surface and being positioned at immediately below U-shaped groove Being provided with a downward lobe, the described heavily doped N-type district exposed and the surface of U-shaped groove cover the first gold medal as electrode Belong to layer;Circular weld tabs starts to melt and in irregular in the welding tunnel more than 260 DEG C, starts the compressing at conductive lead wire The lower edge flowing to chip, in the case of can not definitely controlling weld interval and temperature, scolding tin flows through the external protection of chip Being formed " Xi Qiao ", the chip being provided with guiding gutter now starts to absorb the weld tabs melted, owing to guiding gutter is annular design, Ren Hefang To unnecessary scolding tin all will enter the guiding gutter of welding, and there is in guiding gutter good mobility, unnecessary scolding tin can be put down All it is allocated, it is ensured that uniform welding, adds the intensity of welding, make unnecessary scolding tin carry out again with, solder side Amassing and at least add 15%, welding yield also will promote 6 percentage points;Secondly, high-power rectifying device is devised and weld tabs The hexagonal chips that area is the most close, it is ensured that maximum efficient weld area, makes the overvoltage protection ability of chip be able to fully Playing, the width of U-shaped guiding gutter and the degree of depth are individually designed according to the size of chip area, by experiment certification, due to solder side Obtain the expansion of more than 13%, made chip area drop to 60-65mil from existing 80mil, do not affect overvoltage protection energy In the case of power, chip cost have dropped 11%, and high power device welding machine yield reaches more than 97%.
Low-power consumption semiconductor rectifying device the most of the present invention, is provided with a strip bulge insulation bottom its described epoxy packages body Portion, this strip bulge insulation division is positioned at pin area and the pin area of the second lead-in wire bar of the first lead-in wire bar, is positioned at strip bulge exhausted The both side surface of edge is respectively equipped with the first arc-shaped recess district and the second arc-shaped recess district, this first arc-shaped recess district and the second arc Shape depressed area is oppositely arranged with the pin area of the first lead-in wire bar and the pin area of the second lead-in wire bar respectively, it is achieved at compact products In, it is effectively increased pin creep age distance, adds product ontology area of dissipation, improve reliability and the safety of device Property.
Accompanying drawing explanation
Fig. 1 is the structural representation of low-power consumption semiconductor rectifying device one of the present invention preferred embodiment;
Fig. 2 is the structural representation of diode chip for backlight unit in shown low-power consumption semiconductor rectifying device.
In accompanying drawing, the labelling of each parts is as follows: 1, the first lead-in wire bar;2, the second lead-in wire bar;3, sheet is connected;31, the first welding End;32, the second welding ends;4, diode chip for backlight unit;41, heavily doped P-type monocrystalline silicon piece;42, heavily doped N-type district;43, lobe; 44, groove;45, insulation passivation protection layer;46, the first metal layer;47, the second metal level;48, U-shaped groove;5, Support;61、 First pin area;62, the second pin area;7, weld zone;9, the first bending part;10, the second bending part;11, the 3rd bending part; 12, epoxy packages body;13, strip bulge insulation division;14, the first arc-shaped recess district;15, the second arc-shaped recess district.
Detailed description of the invention
Below in conjunction with the accompanying drawings presently preferred embodiments of the present invention is described in detail, so that advantages and features of the invention energy It is easier to be readily appreciated by one skilled in the art, thus protection scope of the present invention is made apparent clear and definite defining.
Referring to Fig. 1 and Fig. 2, the embodiment of the present invention includes:
Embodiment 1: a kind of low-power consumption semiconductor rectifying device, including the first lead-in wire bar 1, second being positioned at epoxy packages body 12 Lead-in wire bar 2, connection sheet 3 and diode chip for backlight unit 4, this first lead-in wire bar 1 one end is the Support 5 being connected with diode chip for backlight unit 4, institute Stating diode chip for backlight unit 4 one end to be electrically connected with this Support 5 by solder(ing) paste, first lead-in wire bar 1 other end is the first pin area 61, First pin area 61 of this first lead-in wire bar 1 is as the electric current transmission ends of described commutator;Described second lead-in wire bar 2 one end be with The weld zone 7 that first welding ends 31 of described connection sheet 3 connects, this second lead-in wire bar 2 other end is the second pin area 62, and this is the years old Second pin area 62 of two lead-in wire bars 2 is as the electric current transmission ends of described commutator;Described connection sheet 3 second welding ends 32 and two Pole die 4 other end is electrically connected by solder(ing) paste;
Described diode chip for backlight unit 4 includes that surface is provided with the heavily doped P-type monocrystalline silicon piece 41 in heavily doped N-type district 42, this heavily doped N-type District 42 contacts with heavily doped P-type monocrystalline silicon piece 41, and heavily doped N-type district 42 is formed around groove 44, and this groove 44 is positioned at heavy doping P Type monocrystalline silicon piece 41 and heavily doped N-type district 42 surrounding also extend to the middle part of heavily doped P-type monocrystalline silicon piece 41;Described groove 44 Surface is coated with insulation passivation protection layer 45, and this insulation passivation protection floor 45 is by extending to heavily doped N-type district 42 bottom groove 44 The marginal area on surface, surface, heavily doped P-type district 41 covers the second metal level 47 as another electrode;
Region, heavily doped N-type district 42 inside described insulation passivation protection floor 45 has a U-shaped groove 48, this heavy doping N Type district 42 lower surface and be positioned at U-shaped groove 48 and be arranged right below a downward lobe 43, the described heavily doped N-type district exposed 42 and the surface of U-shaped groove 48 cover as the first metal layer 46 of electrode;
Being provided with a strip bulge insulation division 13 bottom described epoxy packages body 12, this strip bulge insulation division 13 is positioned at the first lead-in wire First pin area 61 and the second pin area 62 of the second lead-in wire bar 2 of bar 1, the both side surface being positioned at strip bulge insulation division 13 is divided It is not provided with the first arc-shaped recess district 14 and the second arc-shaped recess district 15, this first arc-shaped recess district 14 and second arc-shaped recess district 15 It is oppositely arranged with the first pin area 61 of the first lead-in wire bar 1 and the second pin area 62 of the second lead-in wire bar 2 respectively.
Between Support 5 and first pin area 61 of above-mentioned first lead-in wire bar 1, region is provided with one first bending part 9, thus Make the Support 5 of the first lead-in wire bar 1 less than the first pin area 61;The area of the weld zone 7 of above-mentioned second lead-in wire bar 2 is more than institute State the area of the first welding ends 31.
Embodiment 2: a kind of low-power consumption semiconductor rectifying device, including epoxy packages body 12 be located in epoxy packages body 12 The first lead-in wire bar 1, second go between bar 2, connect sheet 3 and diode chip for backlight unit 4, this first lead-in wire bar 1 one end is and diode core The Support 5 that sheet 4 connects, described diode chip for backlight unit 4 one end is electrically connected with this Support 5 by solder(ing) paste, and the first lead-in wire bar 1 is another One end is the first pin area 61, and the first pin area 61 of this first lead-in wire bar 1 is as the electric current transmission ends of described commutator;Described Second lead-in wire bar 2 one end is the weld zone 7 connected with described the first welding ends 31 being connected sheet 3, this second lead-in wire bar 2 other end Being the second pin area 62, the second pin area 62 of this second lead-in wire bar 2 is as the electric current transmission ends of described commutator;Described connection Sheet 3 second welding ends 32 is electrically connected by solder(ing) paste with diode chip for backlight unit 4 other end;
Described diode chip for backlight unit 4 includes that surface is provided with the heavily doped P-type monocrystalline silicon piece 41 in heavily doped N-type district 42, this heavily doped N-type District 42 contacts with heavily doped P-type monocrystalline silicon piece 41, and heavily doped N-type district 42 is formed around groove 44, and this groove 44 is positioned at heavy doping P Type monocrystalline silicon piece 41 and heavily doped N-type district 42 surrounding also extend to the middle part of heavily doped P-type monocrystalline silicon piece 41;Described groove 44 Surface is coated with insulation passivation protection layer 45, and this insulation passivation protection floor 45 is by extending to heavily doped N-type district 42 bottom groove 44 The marginal area on surface, surface, heavily doped P-type district 41 covers the second metal level 47 as another electrode;
Region, heavily doped N-type district 42 inside described insulation passivation protection floor 45 has a U-shaped groove 48, this heavy doping N Type district 42 lower surface and be positioned at U-shaped groove 48 and be arranged right below a downward lobe 43, the described heavily doped N-type district exposed 42 and the surface of U-shaped groove 48 cover as the first metal layer 46 of electrode;
Being provided with a strip bulge insulation division 13 bottom described epoxy packages body 12, this strip bulge insulation division 13 is positioned at the first lead-in wire First pin area 61 and the second pin area 62 of the second lead-in wire bar 2 of bar 1, the both side surface being positioned at strip bulge insulation division 13 is divided It is not provided with the first arc-shaped recess district 14 and the second arc-shaped recess district 15, this first arc-shaped recess district 14 and second arc-shaped recess district 15 It is oppositely arranged with the first pin area 61 of the first lead-in wire bar 1 and the second pin area 62 of the second lead-in wire bar 2 respectively.
Between Support 5 and first pin area 61 of above-mentioned first lead-in wire bar 1, region is provided with one first bending part 9, thus Make the Support 5 of the first lead-in wire bar 1 less than the first pin area 61;The weld zone 7 of described second lead-in wire bar 2 and the second pin area Between 62, region is provided with one second bending part 10, so that the weld zone 7 of the second lead-in wire bar 2 is less than the second pin area 62;Institute State and be provided with the 3rd bending part 11 between the first welding ends 31 and second welding ends 32 of connection sheet 3, so that the first welding ends Less than the second welding ends.The both sides, weld zone 7 of above-mentioned second lead-in wire bar 2 are provided with block 8.
When using above-mentioned low-power consumption semiconductor rectifying device, its circular weld tabs starts in the welding tunnel more than 260 DEG C Melt and in irregular, start to flow to the edge of chip under the compressing of conductive lead wire, can not be exhausted in weld interval and temperature In the case of controlling, scolding tin flows through the external protection of chip and forms " Xi Qiao ", and the chip being provided with guiding gutter now starts to absorb The weld tabs melted, owing to guiding gutter is annular design, the unnecessary scolding tin in any direction all will enter the guiding gutter of welding, and water conservancy diversion There is in groove good mobility, unnecessary scolding tin averagely can be allocated, it is ensured that uniform welding, add the strong of welding Degree, makes unnecessary scolding tin carry out again with, bonding area and at least adds 15%, and welding yield also will promote 6 percentages Point.The hexagonal chips the most close with weld tabs area is devised for high-power rectifying device, it is ensured that maximum effectively welding Area, makes the overvoltage protection ability of chip be given full play to, and the width of U-shaped guiding gutter and the degree of depth are according to the size of chip area Individually designed, by experiment certification, owing to solder side has obtained the expansion of more than 13%, make chip area from existing 80mil Dropping to 60-65mil, in the case of not affecting overvoltage protection ability, chip cost have dropped 11%, high power device welding machine Yield reaches more than 97%.
The foregoing is only embodiments of the invention, not thereby limit the scope of the claims of the present invention, every utilize this The equivalent structure that bright description and accompanying drawing content are made, or directly or indirectly it is used in other relevant technical fields, the most in like manner It is included in the scope of patent protection of the present invention.

Claims (4)

1. a low-power consumption semiconductor rectifying device, including being positioned at the first lead-in wire bar (1) of epoxy packages body (12), second drawing Lines (2), connecting sheet (3) and diode chip for backlight unit (4), first lead-in wire bar (1) one end is provided with propping up of being connected with diode chip for backlight unit (4) Support district (5), described diode chip for backlight unit (4) one end is electrically connected with this Support (5) by solder(ing) paste, first go between bar (1) another End is the first pin area (61), and the first pin area (61) are as the electric current transmission ends of commutator;Described connection sheet (3) two ends are respectively It is the first welding ends (31) and the second welding ends (32);Described second lead-in wire bar (2) one end is and described first welding ends (31) The weld zone (7) connected, second lead-in wire bar (2) other end is the second pin area (62), and the second pin area (62) are as commutator Electric current transmission ends;Described connection sheet (3) second welding ends (32) is electrically connected by solder(ing) paste with diode chip for backlight unit (4) other end Connect;Described diode chip for backlight unit (4) includes that surface is provided with the heavily doped P-type monocrystalline silicon piece (41) in heavily doped N-type district (42), and this is heavily doped Miscellaneous N-type region (42) contacts with heavily doped P-type monocrystalline silicon piece (41), and heavily doped N-type district (42) are formed around groove (44), groove (44) it is positioned at heavily doped P-type monocrystalline silicon piece (41) and heavily doped N-type district (42) surrounding and extends to heavily doped P-type monocrystalline silicon piece (41) middle part;The surface of described groove (44) is coated with insulation passivation protection layer (45), and insulation passivation protection layer (45) is by ditch Groove (44) bottom extends to the marginal area on heavily doped N-type district (42) surface, and heavily doped P-type district (41) surface is coated with as electricity Second metal level (47) of pole;It is characterized in that: near the heavily doped N-type district (42) of described insulation passivation protection floor (45) inner side Region has a U-shaped groove (48), this heavily doped N-type district (42) lower surface and be positioned at U-shaped groove (48) be arranged right below one to Under lobe (43), the described heavily doped N-type district (42) exposed and the surface of U-shaped groove (48) are coated with as electrode The first metal layer (46);Described epoxy packages body (12) bottom is provided with a strip bulge insulation division (13), and this strip bulge insulate Portion (13) is positioned between the first pin area (61) and the second pin area (62), is positioned at the both side surface of strip bulge insulation division (13) Being respectively equipped with the first arc-shaped recess district (14) and the second arc-shaped recess district (15), the first arc-shaped recess district (14) and the second arc are recessed Fall into district (15) to be oppositely arranged with the first pin area (61) and the second pin area (62) respectively.
Low-power consumption semiconductor rectifying device the most according to claim 1, it is characterised in that: described first lead-in wire bar (1) Between Support (5) and the first pin area (61), region is provided with one first bending part (9), the Support (5) of the first lead-in wire bar (1) Less than the first pin area (61);Between weld zone (7) and the second pin area (62) of described second lead-in wire bar (2), region is provided with one Second bending part (10), the weld zone (7) of the second lead-in wire bar (2) is less than the second pin area (62);The first of described connection sheet (3) Being provided with the 3rd bending part (11) between welding ends (31) and the second welding ends (32), the first welding ends is less than the second welding ends.
Low-power consumption semiconductor rectifying device the most according to claim 1, it is characterised in that: described second lead-in wire bar (2) Weld zone (7) both sides are provided with block.
Low-power consumption semiconductor rectifying device the most according to claim 1, it is characterised in that: described second lead-in wire bar (2) The area of weld zone (7) is more than the area of described first welding ends (31).
CN201610625996.4A 2016-08-03 2016-08-03 Low-power consumption semiconductor rectifying device Pending CN106158779A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201610625996.4A CN106158779A (en) 2016-08-03 2016-08-03 Low-power consumption semiconductor rectifying device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201610625996.4A CN106158779A (en) 2016-08-03 2016-08-03 Low-power consumption semiconductor rectifying device

Publications (1)

Publication Number Publication Date
CN106158779A true CN106158779A (en) 2016-11-23

Family

ID=57328473

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201610625996.4A Pending CN106158779A (en) 2016-08-03 2016-08-03 Low-power consumption semiconductor rectifying device

Country Status (1)

Country Link
CN (1) CN106158779A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003197923A (en) * 2001-12-27 2003-07-11 Sanken Electric Co Ltd Semiconductor device
CN103117355A (en) * 2013-02-01 2013-05-22 苏州固锝电子股份有限公司 Patch type diode device structure
US20140042471A1 (en) * 2012-01-31 2014-02-13 Rohm Co., Ltd. Light-emitting apparatus and manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003197923A (en) * 2001-12-27 2003-07-11 Sanken Electric Co Ltd Semiconductor device
US20140042471A1 (en) * 2012-01-31 2014-02-13 Rohm Co., Ltd. Light-emitting apparatus and manufacturing method thereof
CN103117355A (en) * 2013-02-01 2013-05-22 苏州固锝电子股份有限公司 Patch type diode device structure

Similar Documents

Publication Publication Date Title
US20140318613A1 (en) Solar cell
US10879411B2 (en) Solar cell module
CN104282788A (en) Main-grid-free high-efficiency back contact solar cell module, main-grid-free high-efficiency back contact solar cell assembly and manufacturing technology of main-grid-free high-efficiency back contact solar cell assembly
KR20130112873A (en) Back contacted photovoltaic cell with an improved shunt resistance
CN107293597A (en) Surface mount rectifier part
CN203521454U (en) Ohmic contact electrode structure of flip-chip LED chip and flip-chip LED chip
US20150107645A1 (en) Solar cell
CN106158766A (en) Miniature attachment rectified semiconductor device
CN103532006A (en) Semiconductor laser
CN102842549B (en) The power MOSFET package body of square flat non-pin
CN208422903U (en) A kind of trench-type insulated gate bipolar transistor encapsulating structure
CN106158779A (en) Low-power consumption semiconductor rectifying device
CN106158767A (en) Miniature surface-adhered type diode component
CN204204882U (en) Without main grid high efficiency back contact solar cell assembly
CN205609509U (en) High yield pastes dress rectifying device
CN106158802A (en) Ultrathin surface-mount commutator
CN205428989U (en) Flip LED chip
CN210956687U (en) Long-life paster diode structure
CN205430164U (en) Photovoltaic terminal box and diode
CN106158980A (en) Miniature surface-adhered semiconductor rectifier device
CN209658165U (en) Patch type TVS semiconductor devices
CN107293596A (en) Anti- short-circuit rectifying device
CN203367266U (en) Encapsulation structure for buffering chip surface solder dosage
CN203367267U (en) Solder dosage-self adaptive rectifier structure
CN107516702A (en) Hinder flip LED chips in a kind of anti-top

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20161123