CN203367266U - Encapsulation structure for buffering chip surface solder dosage - Google Patents
Encapsulation structure for buffering chip surface solder dosage Download PDFInfo
- Publication number
- CN203367266U CN203367266U CN2013204159588U CN201320415958U CN203367266U CN 203367266 U CN203367266 U CN 203367266U CN 2013204159588 U CN2013204159588 U CN 2013204159588U CN 201320415958 U CN201320415958 U CN 201320415958U CN 203367266 U CN203367266 U CN 203367266U
- Authority
- CN
- China
- Prior art keywords
- solder side
- solder
- mesozone
- lead
- brace
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
- H01L2224/37001—Core members of the connector
- H01L2224/3701—Shape
- H01L2224/37011—Shape comprising apertures or cavities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/404—Connecting portions
- H01L2224/40475—Connecting portions connected to auxiliary connecting means on the bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
- H01L2224/848—Bonding techniques
- H01L2224/84801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The utility model relates to an encapsulation structure for buffering chip surface solder dosage. According to the encapsulation structure of the utility model, a supporting region of one end of a first lead line is connected with the lower surface of a rectifying chip; the lower surface of the rectifying chip is electrically connected with the supporting region of the first lead line through solder paste; a welding region of one end of a second lead line is connected with a first welding surface of a connecting sheet; a middle region is arranged between the first welding surface and a second welding surface of the connecting sheet; a first bent position is arranged between the middle region and the first welding surface; a second bent position is arranged between the middle region and the second welding surface; two opposite side ends of the second welding surface of the connecting sheet are provided with a strip-shaped gap respectively; one second through hole is formed on the second bent position, the second welding surface and the middle region; and the second through hole stretches across the second bent position and extends to the second welding surface and the edge of the middle region. The encapsulation structure of the utility model can adaptively absorb excess solder, and therefore, it can be ensured that enough solder can be laid in a welding region, and product failure caused by overflow of excess solder from the welding area can be avoided, and the electrical performance, reliability and yield of the product can be improved.
Description
Technical field
The utility model relates to a kind of semiconductor packing device, relates in particular to a kind of encapsulating structure for buffer chip surface scolder consumption.
Background technology
Rectifier is to utilize the unilateal conduction characteristic of diode to carry out rectification to alternating current, therefore be widely used in alternating current, converts in galvanic circuit.
When designing and developing brace structural semiconductor product, for the electric conductivity that promotes the high power device chip surface and the crucial electrical characteristics of boost device, need to the area design of brace and chips welding part enough greatly.Brace and chip upper surface weld together by scolder.Be limited to the coupling of brace-chips welding zone and chip upper surface area, the control of scolder consumption becomes key process parameter.Scolder meeting on the low side causes the device electrical characteristics bad, and scolder too much can cause device short circuit or Early reliability to lose efficacy.Often there is the prolongation along with the time in prior art, there will be various electrical properties to descend.Especially
Therefore, how to research and develop a kind of rectification chip encapsulating structure, can address the above problem, just become the direction that those skilled in the art make great efforts.
Summary of the invention
The utility model purpose is to provide a kind of encapsulating structure for buffer chip surface scolder consumption, should can self adaptation absorb unnecessary scolder for the encapsulating structure of buffer chip surface scolder consumption, both guaranteed that welding region sprawled the scolder of enough areas, but avoided again overflowing weld zone because amount of solder more and caused product failure, improved product electrically, reliability and yield.
For achieving the above object, the technical solution adopted in the utility model is: a kind of encapsulating structure for buffer chip surface scolder consumption, comprise the first lead-in wire bar, the second lead-in wire bar, brace and the rectification chip that are positioned at the epoxy packages body, the Support of this first lead-in wire bar one end is connected to described rectification chip lower surface, this rectification chip lower surface is electrically connected to the Support of this first lead-in wire bar by solder(ing) paste, and the first lead-in wire bar other end is as the pin area of device current transmission;
The weld zone that is positioned at described the second lead-in wire bar one end is connected with the first solder side of brace, and this second lead-in wire bar other end is as the pin area of device current transmission; Described brace the second solder side is electrically connected to by solder(ing) paste with the rectification chip upper surface;
There is a mesozone between the first solder side of described brace and the second solder side, be respectively equipped with first fold crook and the second bending part between this mesozone and the first solder side and the second solder side, thereby make the mesozone height higher than the first solder side and the second solder side, the both sides end face that the second solder side of described brace is relative all has the strip breach; Described the second solder side is evenly distributed with several the first through holes, and one second through hole is positioned on the second bending part, the second solder side, mesozone, and this second through hole is across the second bending part and extend to the second solder side, mesozone fringe region.
In technique scheme, further improved plan is as follows:
1. in such scheme, the first solder side height of described brace is lower than described the second solder side height.
2. in such scheme, described first fold crook, the second bending part and mesozone angle are 125 ° ~ 145 °.
Because technique scheme is used, the utility model compared with prior art has following advantages and effect:
1. the utility model is for the encapsulating structure of buffer chip surface scolder consumption, there is a mesozone between the first solder side of its brace and the second solder side, be respectively equipped with first fold crook and the second bending part between this mesozone and the first solder side and the second solder side, thereby make the mesozone height higher than the first solder side and the second solder side, the both sides end face that the second solder side of described brace is relative all has the strip breach, in the situation that guarantee not reduce contact area and increase resistance, can self adaptation absorb unnecessary scolder, thereby prevent that scolder from entering non-weld zone, both guaranteed that welding region sprawled the scolder of enough areas, but avoided again overflowing weld zone because amount of solder more and caused product failure, short circuit, improved product electrically and reliability improved yield.
2. the utility model is for the encapsulating structure of buffer chip surface scolder consumption, there is a mesozone between the first solder side of its brace and the second solder side, be respectively equipped with first fold crook and the second bending part between this mesozone and the first solder side and the second solder side, thereby make the mesozone height higher than the first solder side and the second solder side, the both sides end face that the second solder side of described brace is relative all has the strip breach; Described the second solder side is evenly distributed with several the first through holes; Both can prevent that scolder from entering non-weld zone, but avoided overflowing weld zone because amount of solder more and caused product failure, short circuit, improved product electrically and reliability improved yield, the second solder side is evenly distributed with several first through holes because the first through hole covers the scolder overflowed, prevent that scolder from overflowing at the solder side edge, utilized the lateral area of the first through hole in the brace, contact resistance and response time have been reduced, reduce power consumption, also strengthened the bonding strength of brace and rectification chip.
3. the utility model is for the encapsulating structure of buffer chip surface scolder consumption, and the both sides end face that the second solder side of its brace is relative all has the strip breach; Described the second solder side is evenly distributed with several the first through holes, and one second through hole is positioned on the second bending part, the second solder side, mesozone, and this second through hole is across the second bending part and extend to the second solder side, mesozone fringe region; Further prevent that scolder from entering non-weld zone, but avoided overflowing weld zone because amount of solder more and caused product failure, short circuit, improved product electrically and reliability improved yield, the second solder side is evenly distributed with several first through holes because through hole covers the scolder overflowed, prevent that scolder from overflowing at the solder side edge, reduce contact resistance and response time, reduced power consumption.
The accompanying drawing explanation
Accompanying drawing 3 is the encapsulating structure schematic diagram of the utility model for buffer chip surface scolder consumption;
Accompanying drawing 4 is A-A cross-sectional view in accompanying drawing 3.
In above accompanying drawing: 1, the first lead-in wire bar; 11, Support; 2, the second lead-in wire bar; 21, weld zone; 3, brace; 31, the first solder side; 32, the second solder side; 33, mesozone; 34, first fold crook; 35, the second bending part; 4, rectification chip; 5, pin area; 6, strip breach; 7, the first through hole; 8, scolder; 9, the second through hole.
Embodiment
Below in conjunction with drawings and Examples, the utility model is further described:
Embodiment: a kind of encapsulating structure for buffer chip surface scolder consumption, comprise the first lead-in wire bar 1, the second lead-in wire bar 2, brace 3 and the rectification chip 4 that are positioned at the epoxy packages body, the Support 11 of these the first lead-in wire bar 1 one ends is connected to described rectification chip 4 lower surfaces, these rectification chip 4 lower surfaces are electrically connected to the Support 11 of this first lead-in wire bar 1 by solder(ing) paste, and first lead-in wire bar 1 other end is as the pin area 5 of device current transmission;
The weld zone 21 that is positioned at described the second lead-in wire bar 2 one ends is connected with the first solder side 31 of brace 3, and these the second lead-in wire bar 2 other ends are as the pin area 5 of device current transmission; Described brace 3 second solders side 32 are electrically connected to by solder(ing) paste with rectification chip 4 upper surfaces;
There is a mesozone 33 between the first solder side 31 of described brace 3 and the second solder side 32, be respectively equipped with first fold crook 34 and the second bending part 35 between this mesozone 33 and the first solder side 31 and the second solder side 32, thereby make mesozone 33 height higher than the first solder side 31 and the second solder side 32, the both sides end face that the second solder side of described brace 3 is relative all has strip breach 6; Described the second solder side 32 is evenly distributed with several the first through holes 7, one second through hole 9 is positioned on the second bending part 35, the second solder side 32, mesozone 33, and this second through hole 9 is across the second bending part 35 and extend to the second solder side 32, mesozone 33 fringe regions.
The first solder side 31 height of above-mentioned brace 3 are lower than described the second solder side 32 height.
Above-mentioned first fold crook 34, the second bending part 35 are 125 ° ~ 145 ° with mesozone 33 angles.
While adopting the above-mentioned encapsulating structure for buffer chip surface scolder consumption, there is a mesozone between the first solder side of its brace and the second solder side, be respectively equipped with first fold crook and the second bending part between this mesozone and the first solder side and the second solder side, thereby make the mesozone height higher than the first solder side and the second solder side, the both sides end face that the second solder side of described brace is relative all has the strip breach, in the situation that guarantee not reduce contact area and increase resistance, can self adaptation absorb unnecessary scolder, thereby prevent that scolder 8 from entering non-weld zone, both guaranteed that welding region sprawled the scolder 8 of enough areas, but avoided again overflowing weld zone because scolder 8 amounts more and caused product failure, short circuit, improved product electrically and reliability improved yield, secondly, there is a mesozone between the first solder side of its brace and the second solder side, be respectively equipped with first fold crook and the second bending part between this mesozone and the first solder side and the second solder side, thereby make the mesozone height higher than the first solder side and the second solder side, the both sides end face that the second solder side of described brace is relative all has the strip breach, described the second solder side is evenly distributed with several the first through holes, prevent that scolder 8 from overflowing at the solder side edge, utilized the lateral area of the first through hole in the brace, reduced contact resistance and response time, reduce power consumption, also strengthened the bonding strength of brace and rectification chip.
Above-described embodiment is only explanation technical conceive of the present utility model and characteristics, and its purpose is to allow the person skilled in the art can understand content of the present utility model and implement according to this, can not limit protection range of the present utility model with this.All equivalences of doing according to the utility model Spirit Essence change or modify, within all should being encompassed in protection range of the present utility model.
Claims (3)
1. the encapsulating structure for buffer chip surface scolder consumption, comprise the first lead-in wire bar (1), the second lead-in wire bar (2), brace (3) and the rectification chip (4) that are positioned at the epoxy packages body, the Support (11) of this first lead-in wire bar (1) one end is connected to described rectification chip (4) lower surface, this rectification chip (4) lower surface is electrically connected to the Support (11) of this first lead-in wire bar (1) by solder(ing) paste, and first lead-in wire bar (1) other end is as the pin area (5) of device current transmission;
The weld zone (21) that is positioned at described the second lead-in wire bar (2) one ends is connected with first solder side (31) of brace (3), and this second lead-in wire bar (2) other end is as the pin area (5) of device current transmission; Described brace (3) second solders side (32) are electrically connected to by solder(ing) paste with rectification chip (4) upper surface;
It is characterized in that: between first solder side (31) of described brace (3) and the second solder side (32), there is a mesozone (33), be respectively equipped with first fold crook (34) and the second bending part (35) between this mesozone (33) and the first solder side (31) and the second solder side (32), thereby make mesozone (33) height higher than the first solder side (31) and the second solder side (32), the both sides end face that the second solder side of described brace (3) is relative all has strip breach (6); Described the second solder side (32) is evenly distributed with several the first through holes (7), one second through hole (9) is positioned at the second bending part (35), the second solder side (32), mesozone (33) above, and this second through hole (9) is across the second bending part (35) and extend to the second solder side (32), mesozone (33) fringe region.
2. encapsulating structure according to claim 1 is characterized in that: the first solder side (31) height of described brace (3) lower than described the second solder side (32) highly.
3. encapsulating structure according to claim 1 is characterized in that: described first fold crook (34), the second bending part (35) are 125 ° ~ 145 ° with mesozone (33) angle.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2013204159588U CN203367266U (en) | 2013-07-12 | 2013-07-12 | Encapsulation structure for buffering chip surface solder dosage |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN2013204159588U CN203367266U (en) | 2013-07-12 | 2013-07-12 | Encapsulation structure for buffering chip surface solder dosage |
Publications (1)
Publication Number | Publication Date |
---|---|
CN203367266U true CN203367266U (en) | 2013-12-25 |
Family
ID=49814987
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN2013204159588U Expired - Lifetime CN203367266U (en) | 2013-07-12 | 2013-07-12 | Encapsulation structure for buffering chip surface solder dosage |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN203367266U (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103383929A (en) * | 2013-07-12 | 2013-11-06 | 苏州固锝电子股份有限公司 | High-reliability rectifying device |
CN110202289A (en) * | 2018-06-13 | 2019-09-06 | 华帝股份有限公司 | Welding material spreading part, welding part and manufacturing method of welding part |
-
2013
- 2013-07-12 CN CN2013204159588U patent/CN203367266U/en not_active Expired - Lifetime
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103383929A (en) * | 2013-07-12 | 2013-11-06 | 苏州固锝电子股份有限公司 | High-reliability rectifying device |
CN110202289A (en) * | 2018-06-13 | 2019-09-06 | 华帝股份有限公司 | Welding material spreading part, welding part and manufacturing method of welding part |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN203721707U (en) | Chip packaging structure | |
CN203367266U (en) | Encapsulation structure for buffering chip surface solder dosage | |
CN203367267U (en) | Solder dosage-self adaptive rectifier structure | |
CN103383932A (en) | Packaging structure for improving electrical performance of chip | |
CN102842549B (en) | The power MOSFET package body of square flat non-pin | |
CN205336219U (en) | Photovoltaic terminal box and diode | |
CN103383929B (en) | High reliability rectifying device | |
CN203617270U (en) | Jumper wire for Schottky diode | |
CN204014275U (en) | For the pad syndeton of link block plate and motherboard | |
CN208538848U (en) | The encapsulating structure of rectification chip | |
CN109065523B (en) | Packaging structure of rectifying chip | |
CN203118997U (en) | Anti-offset diode device | |
CN101937898A (en) | Rectifier structure for moisture protection | |
CN105679733A (en) | High-yield rectification chip package structure | |
CN204441274U (en) | There is the diode component of Novel connection contact pin | |
CN203733808U (en) | Rectifier diode device | |
CN203118939U (en) | Square flat type power device capsule | |
CN201681826U (en) | Surface mounted rectifier applied in circuit board | |
CN204088297U (en) | Heavy-duty diode device | |
CN203733807U (en) | High-reliability surface mounted diode | |
CN203118935U (en) | DFN (dual flat-pack no-lead) package structure for rectifier chip | |
CN205028893U (en) | Transient voltage inhibitor with radiating seat | |
CN203733806U (en) | Axial surface mounted diode device | |
CN204516745U (en) | A kind of square flat pinless encapsulation structure | |
CN204441494U (en) | A kind of battery pack composite joint sheet |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CX01 | Expiry of patent term | ||
CX01 | Expiry of patent term |
Granted publication date: 20131225 |