CN106409789B - 半导体器件及其形成方法 - Google Patents

半导体器件及其形成方法 Download PDF

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CN106409789B
CN106409789B CN201510456885.0A CN201510456885A CN106409789B CN 106409789 B CN106409789 B CN 106409789B CN 201510456885 A CN201510456885 A CN 201510456885A CN 106409789 B CN106409789 B CN 106409789B
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semiconductor substrate
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semiconductor devices
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CN106409789A (zh
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谢欣云
周鸣
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Priority to US15/212,984 priority patent/US9923065B2/en
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Priority to US15/893,319 priority patent/US10312333B2/en
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Abstract

一种半导体器件及其形成方法，其中，所述半导体器件包括：提供半导体衬底，所述半导体衬底表面具有凸起的鳍部；位于所述鳍部侧壁的绝缘层，所述绝缘层位于所述半导体衬底表面，且其表面低于鳍部的顶部表面，所述绝缘层的导热系数大于氧化硅的导热系数。半导体器件中鳍部侧壁的绝缘层选用导热系数大于氧化硅的导热系数的绝缘材料，在保证绝缘的同时，提高了传热速率。因此，半导体器件工作的过程中，鳍部附近或半导体衬底内产生的热量通过上述导热系数大的绝缘层传导出去，可快速降低半导体器件的温度，提高了半导体器件的散热性，从而提高其性能。

Description

半导体器件及其形成方法
技术领域
本发明涉及半导体制造技术领域，尤其涉及一种半导体器件及其形成方法。
背景技术
随着半导体工艺技术的不断发展，工艺节点逐渐减小，后栅(gate-last)工艺得到了广泛应用，以获得理想的阈值电压，改善器件性能。但是当器件的特征尺寸(CD，CriticalDimension)进一步下降时，即使采用后栅工艺，常规的MOS场效应管的结构也已经无法满足对器件性能的需求，多栅器件作为常规器件的替代得到了广泛的关注。
鳍式场效应管(Fin FET)是一种常见的多栅器件，图1示出了现有技术的一种鳍式场效应管的立体结构示意图。如图1所示，包括：半导体衬底10，所述半导体衬底10上形成有凸出的鳍部14，鳍部14一般是通过对半导体衬底10刻蚀后得到的；介质层11，覆盖所述半导体衬底10的表面以及鳍部14的侧壁的一部分；栅极结构12，横跨在所述鳍部14上，覆盖所述鳍部14的顶部和侧壁，栅极结构12包括栅介质层(图中未示出)和位于栅介质层上的栅电极层(图中未示出)。对于Fin FET，鳍部14的顶部以及两侧的侧壁与栅极结构12相接触的部分都成为沟道区，即具有多个栅，有利于增大驱动电流，改善器件性能。
然而，随着工艺节点的进一步减小，现有技术中具有上述鳍式场效应晶体管的半导体器件的性能仍然存在问题。
发明内容
本发明解决的问题是提供一种半导体器件及其形成方法，可以有效解决半导体器件内的绝缘与导热的问题，提高半导体器件的散热性，从而提高其性能。
为解决上述问题，本发明提供一种半导体器件，包括：提供半导体衬底，所述半导体衬底表面具有凸起的鳍部；位于所述鳍部侧壁的绝缘层，所述绝缘层位于所述半导体衬底表面，且其表面低于鳍部的顶部表面，所述绝缘层的导热系数大于氧化硅的导热系数。
可选的，所述绝缘层的材料为氮化铝或氧化铝。
可选的，所述鳍部底部由两侧侧壁向中心凹陷，且所述鳍部底部的宽度大于等于鳍部顶部宽度的1/3。
可选的，所述鳍部侧壁还形成有氧化层，所述绝缘层覆盖所述氧化层表面。
可选的，当所述半导体衬底包括第一区域和第二区域，所述第一区域和第二区域的半导体衬底表面均具有多个鳍部时，所述绝缘层位于第一区域和第二区域之间的鳍部侧壁。
相应的，本发明的实施例还提供了一种半导体器件的形成方法，包括：提供半导体衬底，所述半导体衬底表面具有凸起的鳍部；形成覆盖所述鳍部顶部和侧壁的绝缘薄膜，所述绝缘薄膜位于所述半导体衬底表面，且其导热系数大于氧化硅的导热系数；刻蚀去除部分厚度的绝缘薄膜，暴露出所述鳍部顶部和部分侧壁，形成表面低于鳍部的顶部表面的绝缘层。
可选的，所述绝缘薄膜的形成工艺为原子层沉积工艺。
可选的，在形成绝缘薄膜前，还包括：形成覆盖所述鳍部顶部表面的硬掩膜层；形成覆盖所述鳍部侧壁表面的侧墙；刻蚀所述鳍部底部，使所述鳍部底部由两侧侧壁向中心凹陷，且所述鳍部底部的宽度大于等于鳍部顶部宽度的1/3。
可选的，刻蚀所述鳍部底部采用的工艺为湿法刻蚀工艺、或为干法和湿法相结合的刻蚀工艺。
可选的，所述湿法刻蚀工艺采用的化学试剂为四甲基氢氧化铵。
可选的，当采用干法和湿法相结合的刻蚀工艺时，所述干法刻蚀工艺采用气体流量为50sccm～1000sccm的CF4、100sccm～3000sccm的He、50sccm～1000sccm的O2，刻蚀功率为100W～3000W，刻蚀腔室压强0.1Mt～20Mt。
可选的，还包括：在形成绝缘薄膜前，氧化所述鳍部表面和半导体衬底表面，形成覆盖所述鳍部顶部和侧壁、并覆盖所述半导体衬底表面的氧化层。
与现有技术相比，本发明的技术方案具有以下优点：
由于鳍部凸起于半导体衬底表面，具有一定的高度，因而对散热较为敏感，在本发明的实施例中，半导体器件中鳍部侧壁的绝缘层选用导热系数大于氧化硅的导热系数的绝缘材料，在保证绝缘的同时，提高了传热速率。因此，半导体器件工作的过程中，鳍部附近或半导体衬底内产生的热量通过上述导热系数大的绝缘层传导出去，可快速降低半导体器件的温度，提高了半导体器件的散热性，从而提高其性能。
进一步的，所述绝缘层的材料为氮化铝，相比于传统的氧化硅材料(导热系数7.6瓦/米·度)，其导热系数高达150瓦/米·度-180瓦/米·度，并且氮化铝具有耐高压、耐高温、耐腐蚀等特性，在提高半导体器件的散热性的同时，可有效提高半导体器件在复杂环境中的绝缘性能。
进一步的，所述鳍部底部由两侧侧壁向中心凹陷，且所述鳍部底部的宽度大于等于鳍部顶部宽度的1/3，所述绝缘层将鳍部底部包裹，在保证半导体器件的驱动电流的同时，可有效降低半导体器件的漏电流。
更进一步的，在形成半导体器件的过程中，所述用于形成绝缘层的绝缘薄膜采用原子层沉积工艺形成，形成的绝缘薄膜的质量较好，即使是具有多个鳍部的情况，所述绝缘薄膜也可以较好的填充在相邻鳍部的缝隙之间，有助于后续形成绝缘性能较好的绝缘层。
附图说明
图1是现有技术的鳍式场效应晶体管的立体结构示意图；
图2-图10是本发明实施例的半导体器件的形成过程的剖面结构示意图。
具体实施方式
正如背景技术所述，现有技术的具有上述鳍式场效应晶体管的半导体器件的性能仍然存在问题。
经过研究发现，具有上述鳍式场效应晶体管的半导体器件的性能之所以存在问题，是由于现有技术中相邻鳍部之间均采用氧化硅作为隔离结构，而氧化硅的导热性能较差，其导热系数仅为7.6瓦/米·度，因而半导体器件在工作时，所述鳍部和半导体衬底周围产生的热量难以及时传导出去，即散热性差，使得半导体器件的温度迅速升高，影响了其性能。
经过进一步研究发现，氮化铝的导热系数远高于传统的氧化硅材料，达150瓦/米·度-180瓦/米·度，并且氮化铝具有耐高压、耐高温、耐腐蚀等特性，将其作为隔离鳍部的绝缘层时，在提高半导体器件的散热性的同时，可有效提高半导体器件在复杂环境中的绝缘性能。
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
请参考图2，提供半导体衬底100。
所述半导体衬底100为后续形成鳍式场效应晶体管提供工艺平台。所述半导体衬底100可以是单晶硅，多晶硅或非晶硅；半导体衬底100也可以是硅、锗、锗化硅、砷化镓等半导体材料；所述半导体衬底100可以是体材料，也可以是复合结构，如绝缘体上硅；所述半导体衬底100还可以是其它半导体材料，这里不再一一举例。本实施例中，所述半导体衬底100的材料为硅，且所述半导体衬底100包括第一区域I和第二区域II，后续所述第一区域I和第二区域II均用于形成一个或多个鳍部。
请参考图3，形成覆盖所述半导体衬底100表面的硬掩膜薄膜101，形成位于所述硬掩膜薄膜101表面的光刻胶层102，所述光刻胶层102具有定义出鳍部的开口。
所述硬掩膜薄膜101用于在后续刻蚀半导体衬底100形成鳍部的过程中保证鳍部顶部的质量。所述硬掩膜薄膜101的形成工艺为沉积工艺，例如化学气相沉积工艺。所述硬掩膜薄膜101的材料为氮化硅、氮化钛等，其厚度与实际情况相关，以能在刻蚀过程中保护到鳍部顶部为宜。本发明的实施例中，所述硬掩膜薄膜101的材料为氮化硅。
所述光刻胶层102用于定义出鳍部的形状、位置等。所述光刻胶层102可以为正胶或负胶，所述开口与鳍部的位置相对应。本发明的实施例中，所述光刻胶层102具备多个开口，用于后续在第一区域I和第二区域II形成多个鳍部。
请参考图4，以所述光刻胶层102(如图3所示)为掩膜，依次刻蚀所述硬掩膜薄膜101(如图3所示)和部分厚度的半导体衬底100，形成硬掩膜层101a和鳍部103。
所述硬掩膜层101a用于在后续工艺中进一步保护鳍部103不受损坏。所述硬掩膜层101a由硬掩膜薄膜101刻蚀后得到，因此，所述硬掩膜层101a的材料与硬掩膜薄膜101相同，为氮化硅、氮化钛等。本发明的实施例中，所述硬掩膜层101a的材料为氮化硅。
所述鳍部103用于后续作为形成鳍式场效应晶体管的基础。本发明的实施例中，所述鳍部103由刻蚀半导体衬底100后形成，因此，所述鳍部103的材料与半导体衬底100相同。
需要说明的是，在本发明的其他实施例中，所述鳍部103还可以由刻蚀位于半导体衬底100表面的半导体层后得到，而所述半导体层的材料可以为其他不同于半导体衬底100的半导体材料。即所述鳍部103的材料还可以为其他不同于半导体衬底100的半导体材料，在此不再赘述。
所述鳍部103具有单个或多个。本发明的实施例中，所述第一区域I和第二区域II均具有多个鳍部103，后续工艺中需要隔离相邻的鳍部103。
需要说明的是，形成硬掩膜层101a后，所述光刻胶层102中的开口已转移至硬掩膜层101a中，此时光刻胶层102即可去除。也就是说，所述光刻胶层102可在形成硬掩膜层101a后立即去除，也可以在形成鳍部103后再去除，在此不再赘述。
请参考图5，形成覆盖所述鳍部103侧壁的侧墙104。
所述侧墙104用于在后续工艺中和硬掩膜层101a共同保护鳍部103，使所述鳍部103不受损坏。本发明的实施例中，所述侧墙104的形成步骤为：形成覆盖所述鳍部103的顶部和侧壁、以及半导体衬底100表面的侧墙薄膜(未图示)；回刻蚀所述侧墙薄膜，暴露出鳍部103顶部的硬掩膜层101a和半导体衬底100表面，形成侧墙104，所述侧墙104覆盖硬掩膜层101a和鳍部103的侧壁。
所述侧墙104选择与鳍部103和半导体衬底100之间刻蚀选择比相差较大的材料，例如氮化硅、氮化钛等，以降低后续去除侧墙104时对鳍部103的损伤。本发明的实施例中，所述侧墙104的材料选择为氮化硅，与硬掩膜层101a的材料相同。
请参考图6，刻蚀所述鳍部103的底部103a，使所述鳍部103的底部103a由两侧侧壁向中心凹陷，且所述鳍部103的底部103a的宽度Wa大于等于鳍部103的顶部103b宽度Wb的1/3。
经研究发现，由于鳍部103凸出于半导体衬底100表面，后续以鳍部103为基础形成的栅电极距离鳍部103的底部103a较远，因而鳍式场效应晶体管在工作时，栅电极对鳍部103的底部103a区域的控制较弱，导致该区域容易产生漏电流，影响半导体器件的性能。进一步的，为解决鳍部103的底部103a处容易产生漏电流的现象，本发明的实施例中对鳍部103的底部103a进行了刻蚀，使得所述鳍部103的底部103a由两侧侧壁向中心凹陷，后续形成氧化层或绝缘层将鳍部103的底部103a紧密包裹，可以更好的防止漏电流的产生。
刻蚀所述鳍部103的底部103a时，采用的刻蚀工艺为湿法刻蚀工艺、或者为干法和湿法相结合的刻蚀工艺。由于刻蚀所述鳍部103的底部103a时，鳍部103的侧壁和顶部103b分别被侧墙104和硬掩膜层101a覆盖，因而刻蚀的过程中，鳍部103的侧壁和顶部103b并不会被刻蚀。本发明的实施例中，由于鳍部103的底部103a的材料为硅，在进行湿法刻蚀工艺时，所采用的化学试剂为碱性试剂，例如四甲基氢氧化铵。
在本发明的其他实施例中，当采用干法和湿法相结合的刻蚀工艺时，所述干法刻蚀工艺采用气体流量为50sccm～1000sccm的CF4、100sccm～3000sccm的He、50sccm～1000sccm的O2，刻蚀功率为100W～3000W，刻蚀腔室压强0.1Mt～20Mt；所述湿法刻蚀工艺采用的化学试剂仍然为碱性试剂，如四甲基氢氧化铵。
需要说明的是，无论采取何种刻蚀方式，只需保证刻蚀完成后，鳍部103的底部103a的宽度Wa大于等于鳍部103的顶部103b宽度Wb的1/3，以免刻蚀后的鳍部103发生断裂。
请参考图7，去除所述侧墙104；氧化所述鳍部103表面和半导体衬底100表面，形成覆盖所述鳍部103顶部103b和侧壁、并覆盖所述半导体衬底100表面的氧化薄膜105。
去除所述侧墙104，以利于后续工艺的顺利进行。去除所述侧墙104采用的工艺为刻蚀工艺，例如干法刻蚀工艺。
所述氧化薄膜105用于修复刻蚀后的鳍部103表面和半导体衬底100表面。所述氧化薄膜105的形成工艺为氧化工艺，其材料为氧化硅。本发明的实施例中，氧化鳍部103表面和半导体衬底100表面后，还进行退火工艺，经刻蚀后鳍部103和半导体衬底100表面的硅原子发生转移，使刻蚀后原本在微观下凹凸不平的鳍部103和半导体衬底100表面更平滑、质量更高，以利于后续提高半导体器件的性能。
本发明的实施例中，由于第一区域I内的多个鳍部间距离较近，第二区域II内的多个鳍部间距离也较近，所述氧化薄膜105将第一区域I内和第二区域II内的多个鳍部间的间隙填满，而第一区域I最右侧的鳍部103和第二区域II最左侧的鳍部103之间相距则较远，形成氧化薄膜105后，上述两个鳍部103之间仍然具有较大间隙。
需要说明的是，在本发明的其他实施例中，可以是第一区域I内的多个鳍部103相距较近，而第二区域II内的多个鳍部103相距较远，形成的氧化薄膜105填充满第一区域I内的鳍部103之间的间隙，而未填充满第二区域II内的多个鳍部103间的间隙；也可以是第一区域I内的多个鳍部103和第二区域II内的多个鳍部103均相距较远，形成氧化薄膜105后，所述第一区域I和第二区域II的相邻鳍部103之间仍具有较大缝隙。
请参考图8，形成覆盖所述鳍部103顶部103b和侧壁的绝缘薄膜106，所述绝缘薄膜106位于所述半导体衬底100表面，且其导热系数大于等于30瓦/米·度。
如前文所述，氧化薄膜105的导热性能较差，例如，当氧化薄膜105为氧化硅时，其导热系数仅为7.6瓦/米·度，因而若仅以氧化薄膜105作为隔离鳍部的材料，后续半导体器件工作时，所述鳍部和半导体衬底周围产生的热量是难以及时传导出去的，半导体器件的温度容易迅速升高，影响其性能。
经过进一步研究发现，氮化铝的导热系数远高于传统的氧化硅材料，达150瓦/米·度-180瓦/米·度，并且氮化铝具有耐高压、耐高温、耐腐蚀等特性，将其作为隔离鳍部的材料时，在提高半导体器件的散热性的同时，可有效提高半导体器件在复杂环境中的绝缘性能。因此，本发明的实施例中，在形成上述氧化薄膜105后，还形成所述绝缘薄膜106，用于后续在起到绝缘效果的同时，提高半导体器件的散热性。
经研究发现，当所述绝缘薄膜106的导热系数大于等于30瓦/米·度时，即可较好的满足半导体器件的散热需要，半导体器件不易迅速升温，器件性能优越。本发明的实施例中，基于现有工艺方法和水平，选择导热系数为150瓦/米·度-180瓦/米·度的氮化铝作为绝缘薄膜106的材料，可采用原子层沉积工艺形成质量较好的绝缘薄膜106。形成的绝缘薄膜的质量较好，即使是具有多个鳍部的情况，所述绝缘薄膜也可以较好的填充在相邻鳍部的缝隙之间，有助于后续形成绝缘性能较好的绝缘层。
需要说明的是，在本发明的其他实施例中，所述绝缘薄膜106的材料还可以为导热系数为45瓦/米·度的氧化铝或其他导热系数大于氧化硅的导热系数的材料。
需要说明的是，在本发明的其他实施例中，可以不形成氧化薄膜105，而直接形成绝缘薄膜106，在此不再赘述。
需要说明的是，在本发明的其他实施例中，只要相邻鳍部103间存在间隙，均可用绝缘薄膜106填充满。
请参考图9，平坦化所述绝缘薄膜106和氧化薄膜105，直至暴露出硬掩膜层101a。
为便于后续工艺的进行，在形成绝缘薄膜106后，需进一步平坦化，以暴露出硬掩膜层101a，所述暴露出硬掩膜层101a在后续工艺中被去除。本发明的实施例中，所述平坦化工艺为化学机械研磨工艺。
需要说明的是，在本发明的其他实施例中，所述平坦化工艺还可以为其他工艺，例如可直接进行刻蚀工艺，在此不再赘述。
请参考图10，刻蚀去除部分厚度的绝缘薄膜106(如图9所示)，暴露出所述鳍部103顶部103b和部分侧壁，形成表面低于鳍部103的顶部103b表面的绝缘层106a。
刻蚀去除部分厚度的绝缘薄膜106，暴露出所述鳍部103顶部103b和部分侧壁，以利于后续在暴露出来的部分鳍部103顶部和侧壁形成栅极结构，以及位于栅极结构两侧的鳍部103内的源极和漏极。本发明的实施例中，硬掩膜层101a在刻蚀去除部分厚度的绝缘薄膜106形成绝缘层106a的过程中可以保护鳍部103的顶部103b不受损坏。较为优选的情况为，选择合适厚度和材料的硬掩膜层101a，使得形成绝缘层106a后硬掩膜层101a刚好刻蚀完毕，暴露出鳍部103的顶部103b。在本发明的实施例中，在形成绝缘层106a后，还有部分厚度的硬掩膜层101a剩余，可进一步将剩余的硬掩膜层101a去除，在此不在赘述。
需要说明的是，在刻蚀去除部分厚度的绝缘薄膜106的同时，所述氧化薄膜105(如图9所示)也被刻蚀，形成了氧化层105a，所述氧化层105a包裹鳍部103的底部103a并覆盖半导体衬底100。
所述绝缘层106a用于隔离相邻鳍部103、以及后续形成的栅电极和半导体衬底100等。本发明的实施例中，所述绝缘层106a和氧化层105a共同隔离相邻鳍部103、以及后续形成的栅电极和半导体衬底100等，不仅可以有效降低鳍部103底部103a处的漏电流，还能很好的起到绝缘作用，且形成的半导体器件的热传导性好，散热较快，半导体器件的温度变化较小，半导体器件的性能受温度影响较小。
上述步骤完成后，还可以在暴露出的鳍部103顶部和侧壁形成栅极结构，以及位于栅极结构两侧的鳍部103内的源极和漏极等，在此不再赘述。
相应的，请继续参考图10，本发明的实施例还提供了一种采用上述方法形成的半导体器件，包括：提供半导体衬底100，所述半导体衬底100表面具有凸起的鳍部103；位于所述鳍部103侧壁的绝缘层106a，所述绝缘层106a位于所述半导体衬底100表面，且其表面低于鳍部103的顶部103b表面，所述绝缘层106a的导热系数大于等于30瓦/米·度。
本发明的实施例中，当所述半导体衬底100包括第一区域I和第二区域II，所述第一区域I和第二区域II的半导体衬底100表面均具有多个鳍部103时，所述绝缘层106a位于第一区域I和第二区域II之间的鳍部103侧壁；所述绝缘层106a的材料为氮化铝或氧化铝；所述鳍部103底部103a由两侧侧壁向中心凹陷，且所述鳍部103底部103a的宽度大于等于鳍部103顶部103b宽度的1/3；所述鳍部103侧壁还形成有氧化层105a，氧化层105a包裹鳍部103底部103a，所述绝缘层106a覆盖所述氧化层105a表面。
更多关于本发明实施例的半导体器件的结构的描述，请参考前述半导体器件的形成方法中的相关描述，在此不再赘述。
本发明的实施例中，由于鳍部凸起于半导体衬底表面，具有一定的高度，因而对散热较为敏感，在本发明的实施例中，半导体器件的鳍部侧壁的绝缘层选用导热系数大于等于30瓦/米·度的绝缘材料，在保证绝缘的同时，提高了传热速率。因此，半导体器件工作的过程中，鳍部附近或半导体衬底内产生的热量通过上述导热系数大的绝缘层传导出去，可快速降低半导体器件的温度，提高了半导体器件的散热性，从而提高其性能。
进一步的，所述绝缘层的材料为氮化铝，相比于传统的氧化硅材料(导热系数7.6瓦/米·度)，其导热系数高达150瓦/米·度-180瓦/米·度，并且氮化铝具有耐高压、耐高温、耐腐蚀等特性，在提高半导体器件的散热性的同时，可有效提高半导体器件在复杂环境中的绝缘性能。
进一步的，所述鳍部底部由两侧侧壁向中心凹陷，且所述鳍部底部的宽度大于等于鳍部顶部宽度的1/3，所述绝缘层将鳍部底部包裹，在保证半导体器件的驱动电流的同时，可有效降低半导体器件的漏电流。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (8)

1.一种半导体器件，其特征在于，包括：
提供半导体衬底，所述半导体衬底表面具有凸起的鳍部；所述半导体衬底包括第一区域和第二区域，所述第一区域和第二区域的半导体衬底表面均具有多个鳍部；
位于所述鳍部侧壁的绝缘层，所述绝缘层仅位于第一区域和第二区域之间的所述半导体衬底表面，且其表面低于鳍部的顶部表面，所述绝缘层的导热系数大于氧化硅的导热系数；
每个所述鳍部侧壁还形成有氧化层，所述绝缘层覆盖第一区域与第二区域相邻的鳍部侧壁上的氧化层的表面；所述氧化层是通过去除填充满相邻鳍部间隙的部分厚度的氧化薄膜形成的。
2.如权利要求1所述的半导体器件，其特征在于，所述绝缘层的材料为氮化铝或氧化铝。
3.如权利要求1所述的半导体器件，其特征在于，所述鳍部底部由两侧侧壁向中心凹陷，且所述鳍部底部的宽度大于或等于鳍部顶部宽度的1/3。
4.一种如权利要求1-3中任一项所述的半导体器件的形成方法，其特征在于，包括：
提供半导体衬底，所述半导体衬底表面具有凸起的鳍部；所述半导体衬底包括第一区域和第二区域，所述第一区域和第二区域的半导体衬底表面均具有多个鳍部；
形成覆盖所述鳍部顶部和侧壁的绝缘薄膜，所述绝缘薄膜位于所述半导体衬底表面，且其导热系数大于氧化硅的导热系数；
刻蚀去除部分厚度的绝缘薄膜，暴露出所述鳍部顶部和部分侧壁，形成表面低于鳍部的顶部表面的绝缘层；所述绝缘层仅位于第一区域和第二区域之间的所述半导体衬底表面；
在形成绝缘薄膜前，氧化所述鳍部表面和半导体衬底表面，形成覆盖所述鳍部顶部和侧壁、并覆盖所述半导体衬底表面的氧化薄膜，所述氧化薄膜填充满相邻鳍部间隙；在刻蚀去除部分厚度的绝缘薄膜的同时，刻蚀去除部分厚度的所述氧化薄膜，形成氧化层；所述绝缘层覆盖第一区域与第二区域相邻的鳍部侧壁上的氧化层的表面。
5.如权利要求4所述的半导体器件的形成方法，其特征在于，所述绝缘薄膜的形成工艺为原子层沉积工艺。
6.如权利要求4所述的半导体器件的形成方法，其特征在于，在形成绝缘薄膜前，还包括：形成覆盖所述鳍部顶部表面的硬掩膜层；形成覆盖所述鳍部侧壁表面的侧墙；刻蚀所述鳍部底部，使所述鳍部底部由两侧侧壁向中心凹陷，且所述鳍部底部的宽度大于等于鳍部顶部宽度的1/3。
7.如权利要求6所述的半导体器件的形成方法，其特征在于，刻蚀所述鳍部底部采用的工艺为湿法刻蚀工艺、或为干法和湿法相结合的刻蚀工艺。
8.如权利要求7所述的半导体器件的形成方法，其特征在于，所述湿法刻蚀工艺采用的化学试剂为四甲基氢氧化铵。
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