CN106356308B - 管芯结合到板的方法以及使用该方法制成的设备 - Google Patents

管芯结合到板的方法以及使用该方法制成的设备 Download PDF

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CN106356308B
CN106356308B CN201610557638.4A CN201610557638A CN106356308B CN 106356308 B CN106356308 B CN 106356308B CN 201610557638 A CN201610557638 A CN 201610557638A CN 106356308 B CN106356308 B CN 106356308B
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die
alloy
metal
reflow
board
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CN106356308A (zh
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M·J·瑟登
F·J·卡尼
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Semiconductor Components Industries LLC
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Semiconductor Components Industries LLC
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Abstract

本公开涉及管芯结合到板。一种将在管芯表面上具有第一和第二金属层的多个管芯结合到板的方法,包括向板上放置第一管芯以及将所述第一管芯和所述板放入回流炉中,所述板包括陶瓷或衬底板或金属引线框架之一,且具有可焊接表面。该方法包括在第一回流温度下进行回流第一时间段,直到第一金属板层和第一管芯的第一和第二金属管芯层中的至少一个形成合金,以将第一管芯粘附到板。该合金的熔化温度比第一回流温度高。因此,可以在稍晚时间增加额外的管芯并进行回流,以附着到板,而不会导致第一管芯到板的结合失效。

Description

管芯结合到板的方法以及使用该方法制成的设备
技术领域
本公开总体上涉及一种电路制造,更具体而言,涉及一种器件结合技术。
背景技术
多芯片模块正越来越多地用于控制机器和系统的操作。不过,出于各种制造考虑的原因,各种器件并非始终都是同时安装到多芯片模块中的。尽管并非始终适于特定应用,但丝焊应用常常被使用。例如,在覆盖区要求需要有效率的集成电路(IC)面积使用的情况下,丝焊方案可能不适合。
替代的方式是使用焊接合金和焊膏。在特定环境中,使用任一种形式的焊接对于将一个管芯结合到板(board),例如陶瓷或衬底板或金属引线框架是有益的。典型地,在将器件和板放在回流炉或窑炉中时,焊接合金或焊膏将会流动,然后将冷却,以将管芯结合到板,如果需要,在器件和板之间生成电连接。对于单个管芯的情况而言,这种方式是有益的,因为如果在回流炉或窑炉中后续回流发生故障,可以取出并更换管芯。
不过,使用焊接合金或焊膏的一个问题是焊料将会回流,原始管芯和板之间的结合将会在接下来将板和新管芯放在回流炉中以将新管芯结合到板时发生故障。在结合失效时,原始管芯可能甚至从板或金属引线框架滑落。解决这个问题的一种方法是为原始或第一管芯使用不同的金属合金,使得结合管芯的金属合金具有比使第二或新管芯的焊接合金回流所需的温度更高的熔化温度。用于这种方式的两种金属包括铅和金。不过,已知铅会导致健康问题,并非始终是合乎需要的。另一方面,金很昂贵,会使产品成本上升。因此,尽管具有其局限性,但常常使用焊料。
附图说明
参考根据各实施例的附图,本领域的技术人员可以更好地理解本公开,并且其众多特征和优点将变得清楚,在附图中:
图1是将第一管芯结合到电路板之前的电路板和第一管芯的侧视图。
图2是电路板与结合的第一管芯和未结合的第二管芯的侧视图。
图3是电路板与结合的第一管芯和第二管芯的侧视图。
图4是电路板与结合的第一管芯和第二管芯的侧视图。
图5是示出了第一管芯的回流热分布的温度-时间曲线图。
图6是示出了第一管芯的回流热分布和第二管芯的第二回流的温度-时间曲线图。
图7是流程图,示出了用于结合管芯的方法。
图8是流程图,示出了用于结合管芯的方法。
在不同附图中使用相同的参考符号表示相似或相同的项目。除非另外注明,“耦合”一词及其关联的动词形式包括通过现有技术中已知的手段的直接连接和间接电连接,并且除非另外注明,对直接连接的任何描述都还暗示了使用适当形式的间接电连接的替代实施例。
具体实施方式
图1是根据实施例将第一管芯结合到电板之前的电路板和第一管芯的侧视图。图1示出了一种系统,该系统包括具有金属层12和14的管芯10以及具有金属层18的板16。板16可以通过任何已知方式构造,并可以包括,例如陶瓷或有机衬底板。或者,可以使用金属引线框架替代板。在下文中,无论何时提到使用板、陶瓷板、衬底板或金属引线框架,都应当理解,可以替代地使用其他支撑结构元件的任一种(板、衬底板、陶瓷板或金属引线框架)。
板16的金属层18包括诸如锡、银或铜的可焊接金属层中的至少一种。金属层18还可以包括多个金属或金属合金层,例如,铜、镍、锡或银或由两种或更多种金属形成的合金。在一个实施例中,管芯上的金属层包括银、锡和镍的组合。该管芯可以包括三个或更多层。尽管图1示出了管芯10上的两个层12和14以及板16上的一个层18,但实施例不限于此,且管芯和板可以包括额外的层。此外,任一个层都可以是合金,不需要是单个元件或金属。例如,标记为m2的层14在一个实施例中也可以是合金。
如图1中所示,管芯10要被附着到板16(更具体而言,附着到板16的层18)。在现有技术中,常常使用焊料膏或管芯附件将管芯结合到板。不过,在这里,选择管芯上多个金属层的金属或金属合金以及板上的至少一个层,使得它们在回流期间熔化并形成合金,该合金后来的熔化温度高于初始金属层回流形成合金期间使用的温度。在描述的实施例中,选择金属,使得即使使用焊料或焊料膏,金融仍将熔化并与焊料混合,以生成熔化温度高于使焊料回流所需的合金。为了使板和一个或多个管芯“回流”,常常将板放在指定温度分布曲线的回流炉或烤炉中指定的时间。在替代过程中也可以使用用于使金属回流的其他技术。这里任何地方提到窑炉或烤炉都应当被理解为包括用于使管芯和板的金属层熔化或回流的替代技术。
图2是根据实施例,板与结合的第一管芯和未结合的第二管芯的侧视图。更具体而言,管芯10和板16被示为在回流之后,其中管芯10的层12和14中的至少一个熔化并与板16的层18混合,以生成合金层20以将管芯10结合到板16。由金属m2和m3(可能还有m1)的特定组合形成的合金层20,具有比层12、14和18的金属m1、m2和m3的任一种分别更高的熔化温度(回流温度)。在图2的范例中,所有的金属m2都已经与金属m3混合,以生成层20的合金m4。
在这里,在图2中,具有层24和26的管芯22被示为依靠着板16的层18设置,但尚未附着或结合到板16。因此,在回流炉或窑炉中对板和管芯10和管芯22进行回流,以令金属m3和m6(还可能有m5)熔化并回流,以生成管芯22和板16的层18之间的结合。如果使用与前面相同的回流温度,金属m6和m3(可能还有层24的m5)将熔化,以生成新合金而不会完全熔化层20的合金m4。根据操作,合金m4可以部分或稍微熔化,但将不会完全熔化从而影响管芯和板之间的结合,使得管芯被移动或可能甚至从板意外滑落。
图3是根据实施例的电路板与结合的第一管芯和第二管芯的侧视图。在图3的范例中,层14的一些金属m2留存,而一些已经与层18的金属m3混合,生成层20的合金m4。这与图2形成对比,在图2中,层14的所有金属m2都熔化,并与板层18的金属m3混合。如前所述,在第一回流期间生成合金m4。此外,层26的一些金属m6留存,而金属m6的一些与层18的金属m3混合,生成层28的合金m7。合金m7是在第二回流期间在第一回流温度下生成的,在第二回流期间,第一回流温度不会使层20的金属m4完全回流(熔化),从而将管芯22结合或附着到板16。如果要将板16第三次回流以增加另一个管芯,只要回流温度与之前相同或至少分别低于层20和28的金属m4和m7的熔化温度,合金m4或m7就不会完全熔化。
图4是根据实施例的电路板与结合的第一管芯和第二管芯的侧视图。参考图4,管芯30被示为在回流之后结合到板36。在回流之前,管芯30包括至少三个金属层,类似于包括层48、50和52的管芯46。在图4中例示的实施例中,管芯30包括初始层32和34,以及新的合金层42和44。板36包括层38和40,层38和40均可以是纯金属或合金。在回流期间,管芯30的初始层包括金属m3(可能是包括m2的层34的一部分),金属m3与板36的层38和40的金属m4和m5中的至少一种混合,生成包括至少一种合金的层42和44。
在本发明的一个实施例中,一种工艺包括对管芯进行回流,直到至少两种金属熔化并混合以生成合金。作为额外的工艺步骤,可以将回流时间延长到第二时间段,以令管芯层或板层的任一个的第三金属(如果不是第四金属的话)混合生成额外的合金。图4示出了这一额外工艺步骤的结果,其中被示为层42和44的两种金属合金是通过回流延长或额外时间来生成的,以部分或全部地组合金属m2、m3、m4和m5。此外,该过程可以任选地包括延长回流时间以从管芯和板的包括金属m1-m5的各个金属层生成额外的合金。如前所述,在将管芯46移到板36上并进行回流时,管芯层42和44的合金m6和m7将不会完全熔化和回流。因此,板36将保持与管芯30结合。
应当理解,这里示出了不同的层以代表具有不同金属组合的合金。不过,在实际作法中,金属的比例可以根据初始金属层厚度和生成合金的回流工艺总时间而逐渐变化。因此,应当理解,可以根据回流工艺的结果,更适当地使用术语“金属间合金”或“金属互化物”替代合金。回流持续时间和相对层厚和构造影响着各个金属层熔化多少以及它们混合得有多好,以在所得合金之内生成均匀分布的金属。例如,如果金属组分在不同区域中不同,术语“金属间合金”可能比术语“合金”更适当,因为“合金”倾向于是指金属含量的均质或均匀分布。这里提到合金意在包括金属间合金。
图5是示出了根据一个实施例的第一管芯的回流热分布的温度-时间曲线图。现在参考图5,示出了回流热分布曲线图,该回流热分布曲线图标识出五个时间段p1-p5,代表在根据一个实施例的工艺中使用的各个热时间段。可以看出,时间段p1代表将回流炉或窑炉预热到预热温度的加热斜变。时间段p2代表在典型回流过程中使用的预热时间段。时间段p2可以用于烧掉杂质或助熔剂和/或逐渐提高温度,以避免损坏板或管芯。时间段p3代表到达回流温度的加热斜变。时间段p4代表维持回流温度的持续时间。典型地,在现有技术应用中,在使用传统焊料元件来将引线和器件彼此结合或结合到印刷板的情况下,回流温度并不会维持任何可察觉的持续时间。不过,在这里,将回流温度至少维持到达到时间t1。
时间t0是达到回流温度的时间,而时间t1是形成合金并生成结合所需的时间量。时间t1可以与时间t0重合。时间t1是随着正在熔化什么金属以及金属层相对厚度而变化的。此外,如结合前面的附图所述,可以在管芯或板的至少一个上使用多个金属层。如果回流温度保持超过时间t1到时间t2,可能由管芯或板上设置的额外金属层形成额外的合金,因为保持回流温度会导致进一步熔化。因此,在时间t2之后不久,时间段5开始,代表冷却时间段。如前所述,在时间t1和t2由回流温度形成的合金的后续熔化温度高于时间段p4的回流温度。图5代表的过程是针对第一管芯的回流过程。
图6是示出了根据一个实施例,第一管芯的回流热分布和第二管芯的第二回流的温度-时间曲线图。实质上,图6中所示的回流热分布曲线与图5等同,只是分布曲线是重复的。图6的回流热分布曲线的左侧部分代表第一管芯的回流过程,而右侧部分代表第一管芯要经受的第二管芯的回流过程。结合图5对各个时间段的描述在此是相同的,并且不会重复。在已经将第一管芯结合到板的情况下对第二管芯执行回流工艺。不过,因为在第一回流期间形成的合金的特性和更高的熔化温度的原因,第一管芯及其金属层不会回流(完全或充分熔化到影响板和管芯之间结合的程度),而在图6中所示的第二回流时间段期间第二管芯的金属层在回流炉或窑炉中回流。
图7是流程图,示出了根据一个实施例用于结合管芯的方法。图7的方法开始于在具有金属层的可焊接板上放置第一管芯(102)。可焊接板可以包括任何类型的已知板,包括用于固定或连接电子器件的陶瓷板和衬底板或金属引线框架。在一个实施例中,金属层是可焊接金属层,例如铜。在公开的实施例中,管芯包括形成于一个表面上的两个金属层,而板包括至少一个可焊接金属表面。将管芯放置在板上,使得板和第一管芯的外金属层彼此接触。之后,将第一管芯和板放在回流炉或烤炉中(104)。将板和管芯保持在加热的回流炉中以使第一管芯和可焊接板的金属层根据第一回流温度分布曲线回流,形成第一合金(106)。
温度分布曲线可以包括紧接着立即冷却的到达指定温度的温度斜变或到达某一温度或温度范围的斜变,该温度或温度范围被维持指定期间或持续时间,足以允许金属层回流以生成至少一种合金。这里提到温度分布曲线包括用于熔化管芯和板金属层的温度和时间的任意组合,以生成期望的合金和/或金属间合金。该方法任选地包括根据第二温度分布曲线继续进行回流(例如,以第二回流温度分布曲线持续第二时间段),以继续使第一管芯和管芯与板的一个或多个金属层回流,从而形成第二合金或金属间合金(108)。
在第一回流过程结束且任何形成的合金已经冷却并硬化之后,该方法包括在可焊接板(110)上放置第二管芯,使第一和第二管芯处在回流炉或烤炉(112)中,以基本重复回流过程。之后,根据第三回流温度分布曲线对第二管芯和板金属层进行回流,而不会使第一回流过程期间生成的第一管芯和板的任何合金金属完全回流。第二管芯和板金属层被回流,以形成用于第二管芯和板的第三合金(114)。最后,该方法任选地包括继续使第二管芯和板的金属层根据第四温度分布曲线回流,以形成第二管芯的第四合金(116)。应当理解,第一、第二、第三和第四温度分布曲线可以相似或者可以在厚度或组分上有所变化。类似地,所生成的第一、第二、第三和第四合金和/或金属互化物基于该温度分布曲线和金属层组分,因此可以相似或不同。
图8是流程图,示出了根据一个实施例用于结合管芯的方法。一开始,将第一管芯靠着没有可焊接焊膏的板放置。如前所述,在一个实施例中,该管芯具有至少两个金属层,而板具有可焊接的至少一个金属层(120)。之后,将管芯和板加热到第一温度,以烧掉助熔剂和/或杂质(122)。在一些工艺中,向外部金属层添加助熔剂以避免可能干扰回流工艺的不希望的氧化。在一个实施例中,将管芯和板放入回流炉或窑炉中,最终使金属层回流,以生成合金或金属间层(在整个金属中金属组分不同的层)。之后,将板和管芯加热到第二温度,以使板金属层与管芯的至少一个金属层回流,形成第一合金(124)。在一个实施例中,一旦达到第二温度,就将环境温度从第二温度降低。对于某种金属组合而言,一旦环境温度达到指定回流温度,金属就充分熔化,可以立即开始冷却过程,除非还要熔化其他金属层以形成期望合金。
任选地,将板和管芯保持在第二温度达指定时间。该方法继续进行,继续维持加热,以继续使板金属与第一和第二管芯的金属层回流,形成第二合金(126)。这个步骤包括在指定时间内保持指定温度范围(例如,步骤124中的第二温度范围)。在所述实施例中,不使用焊料或焊料膏。或者,对于图8的方法而言,在将管芯靠着板放置时,除了板和管芯的金属层之外,可以使用焊料或焊料膏,只要金属熔化并与焊料或焊料膏混合以生成熔化温度高于焊料熔化温度的合金即可。
在第一和第二合金充分冷却以将管芯结合到板之后,该方法包括将第二管芯靠着板放置而不使用可焊接焊膏(128)。之后,该方法任选地包括将第二管芯和具有已附着第一管芯的板加热到第一温度,以烧掉助熔剂和/或杂质(130)。之后,提高回流炉或烤炉温度以根据第四温度加热板,对板金属层和第二管芯第一金属层回流,形成第三合金(132)。如结合步骤124所述,第四温度可以与第二温度相同,或者可以根据设计要求对其进行修改。最后,该方法结束,在第四温度或近似等于第四温度的温度范围处保持加热,以对板金属层与第二管芯的第一和第二管芯金属层进行回流,形成第四合金(134)。如前所述,这个步骤可以包括仅在指定期间内保持指定温度或温度范围。应当理解,第一和第二管芯可能具有基本类似的金属层,从而从回流过程获得基本类似的合金。换言之,如果金属和温度分布曲线或过程类似,第三和第四合金可以分别与第一和第二合金非常类似。
上文公开的主题被认为是例示性的而非限制性的,所附权利要求意在覆盖落在权利要求真实范围之内的所有此类修改、增强和其他实施例。
根据该方法的一个方面,可焊接表面包括铜,第一和第二金属管芯层分别包括银和锡。
根据另一方面,至少一个层包括镍,至少一个层包括银。
根据又一方面,第一合金的熔化温度在220摄氏度到260摄氏度的范围中。
根据又一方面,熔化温度大于260摄氏度。
在另一种形式中,一种将管芯结合到板的方法包括:靠着板或金属引线框架放置具有第一可焊接表面的第一管芯,而不使用焊料膏,所述板或金属引线框架具有第二可焊接表面,板还包括陶瓷板或衬底板之一,其中第一管芯的第一可焊接表面包括第一多个金属层,且其中第一可焊接表面的外层包括银和锡合金,其银组分低于7%重量百分比,且其中与外层相邻的内层为金属层或金属合金层,包括钛、镍或银之一;以及在第一回流温度下对第一管芯进行回流,以形成熔化温度高于第一回流温度的额外合金,其中该额外合金将第一管芯结合到板。
根据该方法的另一个方面,第二可焊接表面包括铜、银和锡层中的至少一种。
根据又一方面,该方法还包括接下来向第二可焊接表面上放置具有第二可焊接管芯表面的第二管芯,以及在第一回流温度下进行回流而不使第一管芯的额外合金回流,以生成熔化温度高于第一回流温度的第二额外合金。
根据又一方面,该方法包括如下至少一者:一开始对第一管芯回流第二时间段,以至少生成第三额外合金,接下来对第二管芯回流第二时间段,以生成第四额外合金。
根据该设备的一方面,陶瓷板或衬底板或金属引线框架的第一可焊接层包括铜、银和锡中的至少一种。
于是,在法律允许的最大程度上,本发明的范围由以下权利要求及其等同要件的可允许最宽解释确定,不应被以上具体实施方式所限制。

Claims (9)

1.一种将多个在管芯表面上具有多个金属层的管芯结合到板的方法,包括:
将第一管芯放置到所述板的可焊接表面上,所述第一管芯包括至少三个金属层,所述板包括陶瓷板或衬底板或金属引线框架之一,其中顶部金属管芯层靠着所述第一管芯的可焊接表面设置;
在220摄氏度到260摄氏度之间的第一回流温度下对所述第一管芯的第一金属管芯层和第二金属管芯层中的至少一个进行第一回流达第一时间段,以从所述第一管芯的第一金属管芯层和第二金属管芯层中的至少一个以及所述板上的多个金属层中的至少一个形成第一合金,从而在所述第一管芯和所述板之间生成结合;
在第一回流温度下保持热量达第二时间段以回流所述板以及所述第一金属管芯层和第二金属管芯层以从所述第一管芯的所述第一金属管芯层和所述第二金属管芯层中的至少一个以及所述板上的所述多个金属层中的至少一个形成第二合金;
将第二管芯放置在所述板的所述可焊接表面上,所述第二管芯包括至少三个金属层,其中顶部金属层管芯层靠着所述第二管芯的可焊接表面设置;
在220摄氏度到260摄氏度之间的第一回流温度下对所述第二管芯的第一金属管芯层和第二金属管芯层中的至少一个进行第二回流达第一时间段以从所述第二管芯的第一金属管芯层和第二金属管芯层中的至少一个以及所述板上的多个金属层中的至少一个形成第一合金从而在所述第二管芯和所述板之间形成结合;以及
在第一回流温度下保持热量达第二时间段以回流所述板以及所述第二管芯的所述第一金属管芯层和第二金属管芯层以从所述第二管芯的所述第一金属管芯层和所述第二金属管芯层中的至少一个以及所述板上的所述多个金属层中的至少一个形成第二合金;
其中所述第一合金的熔化温度高于260摄氏度。
2.根据权利要求1所述的方法,其中所述第一管芯至少包括第三金属管芯层,所述方法还包括:
在所述第一回流温度下进行回流达第三时间段,所述第三时间段足够长以使得所述板的所述可焊接表面与所述管芯上的第二金属层和第三金属层中的至少一个形成第三合金。
3.根据权利要求2所述的方法,其中所述第一回流和所述第二回流中的每个持续导致形成包括镍、银和锡的合金的时间段。
4.根据权利要求1所述的方法,其中所述板包括具有铜和银层的陶瓷板,且其中所述第一管芯和所述第二管芯中的每个包括镍、银和锡层。
5.根据权利要求1所述的方法,其中所述第一合金熔化温度至少比所述第一回流温度高10摄氏度。
6.根据权利要求1所述的方法,还包括:
将第二管芯放置到所述板的所述可焊接表面上,其中所述第二管芯的顶部金属管芯层靠着所述板的所述可焊接表面设置;
在所述第一合金熔化温度下进行第二回流达所述第一时间段,直到所述板的所述可焊接表面和所述第二管芯的至少一个金属管芯层形成第一合金或第二合金,从而将所述第二管芯粘附到所述板;并且
其中在所述第二回流期间,在所述第一管芯和所述板之间形成的所述第一合金不完全熔化,并且所述第一管芯保持粘附到所述板。
7.一种设备,包括:
板的表面上的第一可焊接层,所述板包括陶瓷板或衬底板或金属引线框架之一;
所述第一可焊接层上的第二可焊接层;
第一电路,所述第一电路包括:
包括第一多个金属层的第一管芯上的第一可焊接管芯表面,其中外层包括银和锡的第一合金,所述第一合金的银组分小于7%重量百分比,且其中与所述外层相邻的内层包括钛、镍或银之一;
第二合金,第二合金的后续熔化温度高于将所述第一管芯粘附到所述板的所需的第一回流温度,其中所述第二合金将所述第一合金结合到所述板的所述表面,从而将所述第一管芯保持到所述板;以及
第三合金,第三合金的后续熔化温度高于将所述第一管芯粘附到所述板的所需的第一回流温度,其中所述第三合金将所述第一合金和所述第二合金结合到所述板的所述表面,从而将所述第一管芯保持到所述板;
第二电路,所述第二电路包括:
包括第四合金的第二管芯上的第二可焊接管芯表面;并且其中所述第一电路和所述第二电路被配置成控制所述设备的操作。
8.根据权利要求7所述的设备,其中所述第二合金的熔化温度使其在后续回流工艺期间,在用于增加所述第二电路的所述第一回流温度下不会完全熔化。
9.根据权利要求7所述的设备,其中在前一次回流期间生成的合金的后续熔化温度比使第一多个金属层回流并生成合金的前一次回流期间的回流温度高至少15摄氏度。
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Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10622285B2 (en) * 2016-07-08 2020-04-14 Rohm Co., Ltd. Semiconductor device with solders of different melting points and method of manufacturing
DE102017108422A1 (de) 2017-04-20 2018-10-25 Osram Opto Semiconductors Gmbh Verfahren zum Befestigen eines Halbleiterchips auf einem Leiterrahmen und elektronisches Bauelement
US11430744B2 (en) * 2017-08-10 2022-08-30 Cree, Inc. Die-attach method to compensate for thermal expansion

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290357A (zh) * 2010-06-18 2011-12-21 Nxp股份有限公司 键合封装及其方法
CN103155127A (zh) * 2010-10-22 2013-06-12 松下电器产业株式会社 半导体接合结构体和半导体接合结构体的制造方法
CN103493190A (zh) * 2011-12-27 2014-01-01 松下电器产业株式会社 接合结构体

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5186383A (en) 1991-10-02 1993-02-16 Motorola, Inc. Method for forming solder bump interconnections to a solder-plated circuit trace
DE102005055280B3 (de) 2005-11-17 2007-04-12 Infineon Technologies Ag Verbindungselement zwischen Halbleiterchip und Schaltungsträger sowie Verfahren zur Herstellung und Verwendung des Verbindungselements
JP4742844B2 (ja) 2005-12-15 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US7508012B2 (en) 2006-01-18 2009-03-24 Infineon Technologies Ag Electronic component and method for its assembly
US20070205253A1 (en) 2006-03-06 2007-09-06 Infineon Technologies Ag Method for diffusion soldering
US20090160039A1 (en) 2007-12-20 2009-06-25 National Semiconductor Corporation Method and leadframe for packaging integrated circuits
US8610270B2 (en) * 2010-02-09 2013-12-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and semiconductor assembly with lead-free solder
US8348139B2 (en) * 2010-03-09 2013-01-08 Indium Corporation Composite solder alloy preform
US9312240B2 (en) 2011-01-30 2016-04-12 UTAC Headquarters Pte. Ltd. Semiconductor packages and methods of packaging semiconductor devices
US8431445B2 (en) 2011-06-01 2013-04-30 Toyota Motor Engineering & Manufacturing North America, Inc. Multi-component power structures and methods for forming the same
US9773744B2 (en) * 2011-07-12 2017-09-26 Globalfoundries Inc. Solder bump cleaning before reflow
TW201320207A (zh) 2011-11-15 2013-05-16 Ableprint Technology Co Ltd 抑制濺錫之迴焊方法
US9219030B2 (en) 2012-04-16 2015-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Package on package structures and methods for forming the same
CN104412724A (zh) 2012-07-04 2015-03-11 松下知识产权经营株式会社 电子部件安装构造体、ic卡、cof封装
EP2883242A1 (de) 2012-08-10 2015-06-17 Gottfried Wilhelm Leibniz Universität Hannover Verfahren zum herstellen eines hermetisch abgeschlossenen gehäuses
US9559071B2 (en) 2013-06-26 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Mechanisms for forming hybrid bonding structures with elongated bumps
US9111793B2 (en) 2013-08-29 2015-08-18 International Business Machines Corporation Joining a chip to a substrate with solder alloys having different reflow temperatures
US9355980B2 (en) 2013-09-03 2016-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
KR101430673B1 (ko) 2013-11-05 2014-08-19 주식회사 케이이씨 반도체 디바이스 및 이의 다이 본딩 구조
JP2015122445A (ja) 2013-12-24 2015-07-02 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US9520370B2 (en) * 2014-05-20 2016-12-13 Micron Technology, Inc. Methods of forming semiconductor device assemblies and interconnect structures, and related semiconductor device assemblies and interconnect structures
US9925612B2 (en) 2014-07-29 2018-03-27 Panasonic Intellectual Property Management Co., Ltd. Semiconductor component, semiconductor-mounted product including the component, and method of producing the product

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102290357A (zh) * 2010-06-18 2011-12-21 Nxp股份有限公司 键合封装及其方法
CN103155127A (zh) * 2010-10-22 2013-06-12 松下电器产业株式会社 半导体接合结构体和半导体接合结构体的制造方法
CN103493190A (zh) * 2011-12-27 2014-01-01 松下电器产业株式会社 接合结构体

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