CN106328631B - 半导体装置封装 - Google Patents
半导体装置封装 Download PDFInfo
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Abstract
本发明涉及一种半导体装置封装和一种制造所述半导体装置封装的方法。所述半导体装置封装包括衬底、接地元件、组件、封装体以及导电层。所述接地元件安置于所述衬底中并且包括在所述衬底的侧表面的第二部分处暴露的连接表面。所述组件安置于所述衬底的上表面上。所述封装体覆盖所述组件和所述衬底的所述上表面。所述封装体的侧表面与所述衬底的所述侧表面对准。所述导电层覆盖所述封装体的上表面和所述侧表面,并且进一步覆盖所述衬底的所述侧表面的所述第二部分。所述衬底的所述侧表面的第一部分自所述导电层暴露。
Description
技术领域
本发明大体上涉及半导体装置封装。更确切地说,本发明涉及具有电磁干扰屏蔽罩的半导体装置封装。
背景技术
在至少部分地由针对增强的处理速度和较小尺寸的需求的驱动下,半导体装置已变得越来越复杂。虽然增强的处理速度和较小尺寸的益处显而易见,但半导体装置的这些特征还可产生问题。具体来说,较高时脉速度可涉及信号电平之间的更频繁转变,其又可导致在较高频率或较短波长下的电磁发射的较高电平。电磁发射可自源半导体装置辐射,并且可入射到邻近半导体装置上。如果邻近半导体装置处的电磁发射的电平充分高,那么这些发射可不利地影响所述半导体装置的操作。此现象有时被称作电磁干扰(EMI)。较小尺寸化的半导体装置可通过在总电子系统内提供那些半导体装置的较高密度而加重EMI,并且因此加重邻近半导体装置处非所要电磁发射的较高电平。
在形成屏蔽罩以减轻EMI的工艺中,半导体装置的接合/球垫可受损;例如,一些用于形成EMI屏蔽罩的导电材料可无意地在接合/球垫上形成,其可使接合/球垫对EMI屏蔽罩短路,此可导致产品失效。
就是在此背景下,产生了开发本文中所描述的半导体装置封装和相关方法的需要。
发明内容
根据本发明的一个实施例,提供一种半导体装置封装。所述半导体装置封装包括基板、接地元件、组件、封装体以及电磁干扰(EMI)屏蔽罩。所述接地元件安置于所述基板中并且包括在所述基板的侧表面的第二部分处暴露的连接表面。所述组件安置于所述基板的上表面上。所述封装体覆盖所述组件和所述基板的所述上表面。所述封装体的侧表面与所述基板的所述侧表面对准。所述EMI屏蔽罩覆盖所述封装体的上表面和所述侧表面,并且进一步覆盖所述基板的所述侧表面的所述第二部分。所述基板的所述侧表面的第一部分自所述EMI屏蔽罩暴露。
根据本发明的另一个实施例,提供制造半导体装置封装的方法。所述方法包括:(a)提供具有上表面、与上表面相反的下表面以及自上表面延伸到下表面的侧表面的基板,其中侧表面包括与下表面相邻的第一部分和与第一部分对准并且与上表面相邻的第二部分。所述基板包括在所述基板的侧表面的第二部分处暴露的接地元件。所述方法进一步包括:(b)在所述基板的上表面上附接电子组件;(c)在所述基板上形成封装体以囊封电子组件和所述基板的上表面;(d)用第一粘合剂覆盖所述基板的侧表面的第一部分和下表面;(e)在所述封装体的上表面和侧表面、所述基板的侧表面的第二部分以及所述接地元件的暴露部分上形成导电层;以及(f)移出第一粘合剂。
根据本发明的另一个实施例,提供制造半导体装置封装的方法。所述方法包括:(a)将所述基板压制到在容器中的材料中以覆盖所述基板的侧表面的第一部分,其中所述基板包含囊封所述基板的一上表面的一封装体;(b)形成导电层以覆盖封装体的上表面和侧表面并且进一步覆盖不同于所述基板的侧表面的第一部分的第二部分;以及(c)移出容器和材料。
附图说明
图1说明根据本发明的一个实施例的半导体装置封装的截面视图;
图2说明根据本发明的一个实施例的半导体装置封装的截面视图;
图3A、图3B、图3C、图3D以及图3E说明根据本发明的一个实施例的制造过程;
图4A、图4B、图4C、图4D以及图4E说明根据本发明的一个实施例的制造工艺;以及
图5A、图5B、图5C、图5D以及图5E和图5F说明根据本发明的一个实施例的制造工艺。
贯穿图式和详细描述使用共同参考数字以指示相同或类似元件。从以下结合附图作出的详细描述,本发明将会更显而易见。
具体实施方式
图1说明根据本发明的一个实施例的半导体装置封装1的截面视图。半导体装置封装1包括基板10、多个组件11a、11b、封装体12以及EMI屏蔽罩13。
基板10包含上表面101和与上表面101相反的下表面102。基板10还包含在上表面101与下表面102之间延伸的侧表面103。在一或多个实施例中,侧表面103基本上为平面,并且侧表面103基本上正交于上表面101或下表面102。
基板10包括接地元件10g,其中一部分接地元件10g自基板10的侧表面103暴露。接地元件10g位于基板10的上表面101与下表面102之间。接地元件10g包括在基板的侧表面处暴露的连接表面。接地元件10g电连接到基板10中所包括的电互连件,并且提供电路径以减少EMI。在一或多个实施例中,接地元件10g是安置于基板10中的内部接地通孔或内部接地迹线的一部分。在一或多个实施例中,接地元件10g为沿着基板10的侧表面103安置的接地环。在一或多个实施例中,基板10包括多个接地元件10g。在一或多个实施例中,接地元件10g为安置于基板10内的导电层,并且导电层可包括一或多种导电材料,如金属或金属合金。
基板10包括在基板的下表面102上的导电垫10p。在一或多个实施例中,基板10包括连接到导电垫10p的焊球10b。焊球10b提供用于半导体装置封装1的输入和输出电连接。在一或多个实施例中,焊球10b中的一或多者借助于基板10中所包括的电互连件电连接到组件11a、11b。在一或多个实施例中,至少一个焊球10b是接地电接点并且经由基板10中所包括的电互连件电连接到接地元件10g。
基板10例如由印刷电路板(PCB)形成,如基于纸的铜箔层压物、复合铜箔层压物或聚合物浸渍的基于玻璃纤维的铜箔层压物。基板10可经其它适合的载体(如引线框)替换。
组件11a、11b安装在基板10的上表面101上。在一或多个实施例中,组件11a是半导体芯片或裸片,而组件11b是被动装置,如电阻器、电容器、电感器或其组合。组件11a是借助于导电凸块11ab接合到基板10的倒装芯片。在一或多个实施例中,组件11a可经由接线(未显示)线接合到基板10。导电凸块11ab可由例如锡、铜或任何其它适合的导电材料形成。组件11b表面安装到基板10。
尽管在图1中显示三个组件(例如一个组件11a和两个组件11b),在其它实施例中可包括更多组件或更少组件。
封装体12安置于基板10的上表面101上并且覆盖组件11a、11b以及基板10的上表面101,以提供机械稳定性以及抵抗氧化、湿度以及其它环境条件的保护。封装体12可包括例如具有填料的环氧树脂、模制化合物、环氧模制化合物、聚酰亚胺、酚类或具有分散在其中的硅酮的材料。
在一或多个实施例中,封装体12的侧表面122与基板10的侧表面103对准(例如共面或基本上共面)。
EMI屏蔽罩13覆盖封装体12的上表面121和侧表面122,并且进一步覆盖基板10的一部分侧表面103以提供抵抗EMI的保护。基板10的另一部分侧表面103(例如朝向基板10的下表面102)自EMI屏蔽罩103暴露以避免EMI屏蔽罩103与焊球10b之间的可引起短路的接触。在一些实施例中,侧表面103的覆盖部分的垂直程度可大于侧表面103的暴露部分的垂直程度,如其中侧表面103的覆盖部分的垂直程度大于基板10的厚度的约50%,例如至少约55%、至少约60%或至少约65%,尽管侧表面103的覆盖和暴露部分的相对程度可颠倒或对于其它实施例以其它方式改变。在图1中所说明的实施例中,EMI屏蔽罩13覆盖接地元件10g的暴露部分的连接表面。在其它实施例中,EMI屏蔽罩13部分覆盖接地元件10g的暴露部分的连接表面,而接地元件10g的暴露部分的连接表面的其余部分经EMI屏蔽罩13揭开。EMI屏蔽罩13电连接到接地元件10g的暴露部分的连接表面,并且经由接地元件10g接地,进而减少电磁发射。在一或多个实施例中,EMI屏蔽罩13是导电层,并且导电层可包括一或多种导电材料,如金属或金属合金。
图2说明根据本发明的一个实施例的半导体装置封装2的截面视图。半导体装置封装2包括组件21、钝化层22、重布层23以及EMI屏蔽罩24。在一或多个实施例中,半导体装置封装2是晶片级芯片规模封装。
组件21是有源组件,如裸片。组件21包括第一表面211、与第一表面211相反的第二表面212以及在第一表面211与第二表面212之间延伸的侧表面213。组件21包括在其第一表面211上的电节点21n。
钝化层22安置于组件21的第一表面211上。钝化层22可为不导电或绝缘聚合物,如聚酰亚胺(PI)、环氧树脂、聚苯并噁唑(PBO)或苯并环丁烯(BCB);或者,可使用无机钝化层,如二氧化硅(SiO2)。
重布层23安置于钝化层22上,并且包括电介层23d和金属层23m。重布层23包括第一表面231和基本上正交于第一表面231的侧表面233。导电垫25安置于重布层23的第一表面231上。在一或多个实施例中,焊球26连接到导电垫25。焊球26提供用于半导体装置封装2的输入和输出电连接。在一或多个实施例中,焊球26中的至少一些借助于钝化层22和重布层23中所包括的电互连件电连接到组件21。重布层23包括接地元件23g,其中接地元件23g的一部分具有自重布层23的侧表面233暴露的连接表面。在一或多个实施例中,接地元件23g是安置于重布层23中的内部接地通孔或内部接地迹线的一部分。在一或多个实施例中,接地元件23g是沿着重布层23的侧表面233安置的接地环。在一或多个实施例中,重布层23包括多个接地元件23g。
电介层23d可为不导电或绝缘聚合物,如聚酰亚胺(PI)、环氧树脂、聚苯并噁唑(PBO)或苯并环丁烯(BCB)。
EMI屏蔽罩24覆盖组件21的第二表面212和侧表面213、钝化层22的侧表面223以及重布层23的侧表面233的一部分,以提供抵抗EMI的保护。重布层23的侧表面233的另一部分自EMI屏蔽罩24暴露以避免EMI屏蔽罩24与焊球26之间的可引起短路的接触。在图2中所说明的实施例中,EMI屏蔽罩24覆盖接地元件23g的暴露部分的连接表面。在其它实施例中,EMI屏蔽罩24部分覆盖接地元件23g的暴露部分的连接表面,而接地元件23g的暴露部分的连接表面的其余部分未由EMI屏蔽罩24覆盖。EMI屏蔽罩24电连接到接地元件23g的暴露部分的连接表面,并且经由接地元件23g接地,进而减少电磁发射。在一或多个实施例中,EMI屏蔽罩24是导电层。
图3A到3E说明根据本发明的一个实施例的半导体工艺。
参看图3A,提供第一载体30和第二载体31。第二载体31附接到第一载体30。空腔31h自第二载体31的上表面311朝向第一载体30形成,但不充分地延伸通过第二载体31。第一载体30和第二载体31与空腔31h一起形成容器。
在一或多个实施例中,第一载体30是玻璃或聚甲基丙烯酸甲酯(PMMA),并且第二载体31是聚对苯二甲酸伸乙酯(PET)。其它材料可另外或替代地用于第一载体30和第二载体31。
参看图3B,将粘合剂32注入到容器中(例如第二载体31的空腔31h中),并且移出过量(多余)粘合剂32以使得粘合剂32的上表面321和第二载体31的上表面311基本上共面。在一或多个实施例中,粘合剂32是光学可固化的并且更确切地说,是紫外(UV)光可固化的。在一或多个实施例中,粘合剂32是热可固化的。在一或多个实施例中,粘合剂32是可剥离粘合剂。
参看图3C,将半导体装置封装1'放置到容器中粘合剂32中。半导体装置封装1'类似于图1中显示的半导体装置封装1,不同之处在于省略EMI屏蔽罩13。
按压半导体装置封装1'以使得半导体装置封装1'的焊球10b与空腔31h的下表面31h1接触。第二载体31的上表面311低于基板10的接地元件10g,并且因此粘合剂32不覆盖接地元件10g的暴露部分。在将半导体装置封装1'按压到粘合剂32中之后,使粘合剂32固化或凝固。在一或多个实施例中,粘合剂32可使用UV来固化。在一或多个实施例中,粘合剂32可通过加热来固化。
在一或多个实施例中,半导体装置封装1'可通过以下来形成:(i)提供基板10;(ii)将电子组件11a、11b附接到基板10上;(iii)在基板10的下表面102上形成导电垫10p;(iv)在基板10上形成封装体12以囊封电子组件11a、11b以及基板10的上表面101;以及(v)在导电垫10p上形成焊球10b。
基板10可为例如PCB,如基于纸的铜箔层压物、复合铜箔层压物或聚合物浸渍的基于玻璃纤维的铜箔层压物。基板10可经任何其它适合的载体(如引线框)替换。
在图3C中所说明的实施例中,组件11a是借助于导电凸块11ab接合到基板10的倒装芯片。在其它实施例中,组件11a可线接合到基板10。导电凸块11ab可为例如锡、铜或任何其它适合的导电材料。在图3C中所说明的实施例中,组件11b表面安装到基板10。在其它实施例中可使用其它安装技术。
封装体12可例如通过将囊装剂涂覆到基板10的上表面101来形成以基本上覆盖或囊封组件11a、11b以及基板10的上表面101。在一或多个实施例中,囊装剂可包括例如基于酚醛清漆的树脂、基于环氧树脂的树脂、基于硅酮的树脂或任何其它适合的囊封材料。在一或多个实施例中,囊封可通过使用多种模制技术(如压缩模制、射出模制以及传递模制)中的一或多者来涂覆。
参看图3D,EMI屏蔽罩13在暴露表面上形成,包括在封装体12的上表面121和侧表面122上,和在基板10的未经粘合剂32覆盖的一部分侧表面103上。EMI屏蔽罩13可使用多种涂布技术中的一或多者形成,如化学气相沉积(CVD)、物理气相沉积(PVD)、无电极电镀、电镀、印刷、喷涂、溅射以及真空沉积。在形成EMI屏蔽罩13之后,沿着EMI屏蔽罩13的侧表面,如沿着图3D中的虚线进行切割工艺,以切开粘合剂32。可例如通过刀片锯切或激光切割进行切割工艺。
参看图3E,将粘合剂32、第一载体30以及第二载体31与半导体装置封装1'分离以形成如图1中所示的半导体装置封装1。
根据图3A到3E中所说明的工艺,因为粘合剂32在形成EMI屏蔽罩13之前固化,由固化粘合剂32保护导电垫10p和焊球10b以使得形成EMI屏蔽罩13的金属或导电材料不接触导电垫10p或焊球10b。
此外,对于图3A到3E中所说明的实施例,因为粘合剂32不覆盖接地元件10g的暴露部分(参见图3C),当进行图3D中的涂布工艺时EMI屏蔽罩13覆盖接地元件10g的暴露部分。因此,半导体装置封装1具有改善的电磁屏蔽能力。类似工艺可用于形成图2的封装2。
图4A到4E说明根据本发明的另一个实施例的半导体工艺。图4A到4E中显示的半导体工艺类似于图3A到3E中显示的工艺,不同之处在于形成图4A中显示的空腔42h与形成如图3A中所示的空腔31h不同。
参看图4A,提供第一载体40和第二载体41。第二载体41附接到第一载体40。第一粘合剂42涂覆到或形成于第二载体41的上表面411上第二载体41的边缘周围。在固化第一粘合剂42之后,空腔42h由固体第一粘合剂42包围。第一载体40和第二载体41与固化第一粘合剂42一起形成容器。
参看图4B,将第二粘合剂43注入到容器中(例如空腔42h中),并且移出过量(多余)第二粘合剂43以使得第二粘合剂43的上表面431和第一粘合剂42的上表面421基本上共面。在一或多个实施例中,第一粘合剂42和第二粘合剂43中的一者或两者是光学可固化的,并且更确切地说,是UV可固化的。在一或多个实施例中,第一粘合剂42和第二粘合剂43中的一者或两者是热可固化的。在一或多个实施例中,第一粘合剂42和第二粘合剂43中的一者或两者是可剥离粘合剂。在一或多个实施例中,第一粘合剂42与第二粘合剂43相同。在一或多个实施例中,第一粘合剂42与第二粘合剂43不同。
参看图4C,将半导体装置封装1'放置到容器中第二粘合剂43中。半导体装置封装1'与图3C中显示的半导体装置封装相同。
按压半导体装置封装1'以使得半导体装置封装1'的焊球10b与第二载体41的上表面411接触。第一粘合剂42的上表面421低于基板10的接地元件10g,并且因此第二粘合剂43不覆盖接地元件10g的暴露部分。在将半导体装置封装1'按压到第二粘合剂43中之后,第二粘合剂43经固化以变为固体。在一或多个实施例中,第二粘合剂43可使用UV来固化。在一或多个实施例中,第二粘合剂43可通过加热来固化。
参看图4D,EMI屏蔽罩13形成于暴露表面上,包括在封装体12的上表面121和侧表面122上,和在基板10的未经第二粘合剂43覆盖或囊封的侧表面103的一部分上。EMI屏蔽罩13可使用多种涂布技术中的一或多者形成,如CVD、PVD、无电极电镀、电镀、印刷、喷涂、溅射以及真空沉积。在形成EMI屏蔽罩13之后,沿着EMI屏蔽罩13的侧表面,如沿着图4D中的虚线进行切割工艺以切开第二粘合剂43。可例如通过刀片锯切或激光切割进行切割工艺。
参看图4E,将第一粘合剂42、第二粘合剂43、第一载体40以及第二载体41与半导体装置封装1'分离,以形成如图1中所示的半导体装置封装1。类似工艺可用于形成图2的封装2。
图5A到5F说明根据本发明的另一个实施例的半导体工艺。图5A到5F中显示的半导体工艺类似于图3A到3E中显示的工艺,不同之处在于形成图5A中显示的空腔51h与形成图3A中显示的空腔31h不同。
参看图5A,提供第一载体50和第二载体51。第二载体51附接到第一载体50。具有阶梯形状的空腔51h自第二载体51的上表面512朝向第一载体50形成,但不充分地延伸通过第二载体51。第一载体50和第二载体51与空腔51h一起形成容器。
参看图5B,将第一粘合剂52注入到容器中(例如空腔51h中)并且移出过量(多余)第一粘合剂52以使得第一粘合剂52的上表面521和第二载体51的上表面511基本上共面。第一粘合剂52经固化以变为固体。在一或多个实施例中,第一粘合剂52经光学固化,并且更确切地说经UV固化。在一或多个实施例中,第一粘合剂52经热固化。第一粘合剂52可类似于如上文所描述的粘合剂32。
参看图5C,将第二粘合剂53注入到容器中(例如空腔51h中),并且移出过量(多余)第二粘合剂53以使得第二粘合剂53的上表面531和第二载体51的上表面512基本上共面。在一或多个实施例中,第二粘合剂53是光学可固化的,并且更确切地说是UV可固化的。在一或多个实施例中,第二粘合剂53是热可固化的。第二粘合剂53可类似于如上文所描述的粘合剂32。在一或多个实施例中,第一粘合剂52与第二粘合剂53相同。在一或多个实施例中,第一粘合剂52与第二粘合剂53不同。
参看图5D,将半导体装置封装1'放置到容器中第二粘合剂53中。半导体装置封装1'与图3C中显示的半导体装置封装相同。按压半导体装置封装1'以使得半导体装置封装1'的焊球10b与第一粘合剂52的上表面521接触。第二粘合剂53的上表面531低于基板10的接地元件10g,并且因此第二粘合剂53不覆盖接地元件10g的暴露部分。在将半导体装置封装1'按压到第二粘合剂53中之后,第二粘合剂53经固化以变为固体。在一或多个实施例中,第二粘合剂53可使用UV来固化。在一或多个实施例中,第二粘合剂53可通过加热来固化。
参看图5E,EMI屏蔽罩13形成于暴露表面上,包括在封装体12的上表面121和侧表面122上,和在基板10的未经第二粘合剂53覆盖或囊封的一部分侧表面103上。EMI屏蔽罩13可使用多种涂布技术中的一或多者形成,如CVD、PVD、无电极电镀、电镀、印刷、喷涂、溅射以及真空沉积。在形成EMI屏蔽罩13之后,沿着EMI屏蔽罩13的侧表面,如沿着图5E中的虚线进行切割工艺以切开第二粘合剂53。可例如通过刀片锯切或激光切割进行切割工艺。
参看图5F,将第一粘合剂52、第二粘合剂53、第一载体50以及第二载体51与半导体装置封装1'分离以形成图1中显示的半导体装置封装1。类似工艺可用于形成图2的封装2。
返回参看图3E,在分离工艺期间由于粘合剂32的粘合强度,一部分粘合剂32可保留在导电垫10p或焊球10b上,并且可通过清洁或移出操作来移出。类似现象可出现在如图4E中所示的工艺中。在图5A到5F中显示的制造工艺中,在注入随后经固化的第二粘合剂53之前固化第一粘合剂52。以此方式,第一粘合剂52倾向于固定第二粘合剂53并且防止其在与半导体装置封装1'分离时(图5F)跟随半导体装置封装1,以使得可减少粘合剂52或53保留在导电垫10p或焊球10b上的现象。
如本文所用,术语“基本上”和“约”用于描述和解释较小变化。当与事件或情形结合使用时,所述术语可指事件或情形明确发生的情况以及事件或情形极近似于发生的情况。举例来说,当与数值结合使用时,术语可指小于或等于±10%,如小于或等于±5%,小于或等于±4%,小于或等于±3%,小于或等于±2%,小于或等于±1%,小于或等于±0.5%,小于或等于±0.1%,或小于或等于±0.05%。
举例来说,术语“基本上正交”可指90°±10°,如90°±5°、90°±4°、90°±3°、90°±2°、90°±1°、90°±0.5°、90°±0.1°或90°±0.05°。
术语“基本上平面”可指表面的最高点与最低点之间的约不大于1μm、不大于8μm或不大于10μm的差。如果侧表面之间的任何位移不大于10μm,如不大于8μm、不大于5μm或不大于1μm,那么可认为侧表面是“基本上共面的”。
另外,有时在本文中按范围格式呈现量、比率以及其它数值。应理解,此类范围格式是用于便利和简洁,并且应灵活地理解,不仅包括明确地指定为范围限制的数值,而且包括涵盖于所述范围内的所有个别数值或子范围,如同明确地指定每一数值和子范围一般。
虽然已参考本发明的特定实施例描述和说明本发明,但这些描述和说明并不限制本发明。所属领域的技术人员应理解,在不脱离如由所附权利要求书界定的本发明的真实精神和范围的情况下,可作出各种改变并且可取代等效物。所述说明可能未必按比例绘制。归因于制造工艺和公差,本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书和图式视为说明性的而非限制性的。可做出修改,以使特定情况、材料、物质组成、方法或工艺适应于本发明的目标、精神以及范围。所有所述修改都打算属于在此所附权利要求书的范围内。虽然本文中所公开的方法已参考按特定次序执行的特定操作加以描述,但应理解,可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此,除非本文中特别指示,否则操作的次序和分组并非本发明的限制。
Claims (18)
1.一种制造半导体装置封装的方法,其包含:
(a)提供具有上表面、与所述上表面相反的下表面以及自所述上表面延伸到所述下表面的侧表面的基板,其中所述侧表面包括与所述下表面相邻的第一部分和与所述第一部分对准并且与所述上表面相邻的第二部分,所述基板包括在所述基板的所述侧表面的所述第二部分处暴露的接地元件;
(b)将至少一个电子组件附接在所述基板的所述上表面上;
(c)在所述基板上形成封装体以囊封所述电子组件和所述基板的所述上表面;
(d)用第一粘合剂覆盖所述基板的所述侧表面的所述第一部分和所述下表面;
(e)在所述封装体的上表面和侧表面、所述基板的所述侧表面的所述第二部分以及所述接地元件的暴露部分上形成导电层;以及
(f)移除所述第一粘合剂。
2.根据权利要求1所述的方法,其进一步包含在(d)之后固化所述第一粘合剂。
3.根据权利要求1所述的方法,其进一步包含在(d)中将所述基板放置到在容器中的所述第一粘合剂中。
4.根据权利要求3所述的方法,其中所述容器通过以下来提供:
提供自载体的上表面界定凹槽的所述载体,
其中所述载体的所述上表面低于所述基板的所述侧表面的所述第二部分。
5.根据权利要求3所述的方法,其中所述容器通过以下来提供:
提供载体;和
在所述载体上涂覆第二粘合剂,
其中所述第二粘合剂的上表面低于所述基板的所述侧表面的所述第二部分。
6.根据权利要求3所述的方法,其进一步包含在将所述基板放置到所述容器中的所述第一粘合剂中之前移除过量第一粘合剂以使得所述第一粘合剂的上表面与所述容器的上表面对准。
7.根据权利要求3所述的方法,其中所述容器通过以下来提供:
提供自载体的上表面界定第一凹槽的所述载体;和
界定在所述第一凹槽下方的第二凹槽,
其中所述载体的所述上表面低于所述基板的所述侧表面的所述第二部分。
8.根据权利要求7所述的方法,其进一步包含在所述第二凹槽内涂覆第二粘合剂,其中所述第一粘合剂的上表面低于所述基板的所述侧表面的所述第二部分。
9.根据权利要求1所述的方法,其进一步包含在(e)中:
沿着所述导电层的侧表面切割所述第一粘合剂;和
将所述基板与所述第一粘合剂分离。
10.一种制造半导体装置封装的方法,所述方法包含:
(a)将基板压制到在容器中的材料中以覆盖所述基板的侧表面的第一部分,其中所述基板包含囊封所述基板的一上表面的一封装体;
(b)形成导电层以覆盖所述封装体的上表面和侧表面并且以进一步覆盖不同于所述基板的所述侧表面的所述第一部分的第二部分;以及
(c)通过沿所述导电层的侧表面切割所述材料移除所述容器和所述材料,且将所述基板与所述材料分离。
11.根据权利要求10所述的方法,其进一步包含在(a)之后固化所述材料。
12.根据权利要求10所述的方法,其进一步包含在(a)之前移除所述容器中的过量材料,以使得所述材料的上表面与所述容器的上表面对准。
13.根据权利要求10所述的方法,其进一步包含固化所述材料。
14.一种制造半导体装置封装的方法,其包含:
(a)将半导体装置封装压制到容器中的材料中以覆盖所述半导体装置封装的一部分;
(b)形成电磁干扰屏蔽罩以覆盖所述半导体装置封装自所述材料暴露的其余部分;以及
(c)通过沿所述半导体装置封装的侧表面切割所述材料将所述半导体装置封装与所述材料分离。
15.根据权利要求14所述的方法,其中所述材料包括粘合剂,且所述方法进一步包含在(a)之后固化所述粘合剂。
16.根据权利要求14所述的方法,其中所述半导体装置封装包含接地元件,且(a)包含将所述半导体装置封装压制到所述材料中,从而使得所述接地元件的连接表面自所述材料暴露。
17.根据权利要求16所述的方法,其中所述材料的上表面低于所述接地元件的所述连接表面。
18.根据权利要求14所述的方法,其中(b)包含将金属涂覆在所述半导体装置封装自所述材料暴露的其余部分上。
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