CN106298676A - 半导体元件的制作方法 - Google Patents
半导体元件的制作方法 Download PDFInfo
- Publication number
- CN106298676A CN106298676A CN201510291873.7A CN201510291873A CN106298676A CN 106298676 A CN106298676 A CN 106298676A CN 201510291873 A CN201510291873 A CN 201510291873A CN 106298676 A CN106298676 A CN 106298676A
- Authority
- CN
- China
- Prior art keywords
- lining
- semiconductor element
- manufacture method
- stack structure
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 36
- 239000002184 metal Substances 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000000463 material Substances 0.000 claims description 34
- 238000005516 engineering process Methods 0.000 claims description 29
- 238000007254 oxidation reaction Methods 0.000 claims description 21
- 230000003647 oxidation Effects 0.000 claims description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 15
- 229910052721 tungsten Inorganic materials 0.000 claims description 15
- 239000010937 tungsten Substances 0.000 claims description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 10
- 238000005121 nitriding Methods 0.000 claims description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 2
- 229910017052 cobalt Inorganic materials 0.000 claims description 2
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 238000005496 tempering Methods 0.000 claims description 2
- 238000001039 wet etching Methods 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 230000005641 tunneling Effects 0.000 description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 16
- 230000015654 memory Effects 0.000 description 15
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 14
- 239000000203 mixture Substances 0.000 description 9
- 230000008569 process Effects 0.000 description 9
- 239000000377 silicon dioxide Substances 0.000 description 9
- 238000003860 storage Methods 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 7
- 229910052757 nitrogen Inorganic materials 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 238000004380 ashing Methods 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000011435 rock Substances 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000001912 gas jet deposition Methods 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- 239000003973 paint Substances 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000005728 strengthening Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 238000010345 tape casting Methods 0.000 description 2
- ZNOKGRXACCSDPY-UHFFFAOYSA-N tungsten trioxide Chemical compound O=[W](=O)=O ZNOKGRXACCSDPY-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- JIMUOUDLWPNFAY-UHFFFAOYSA-N [Si]=O.[Hf].[N] Chemical compound [Si]=O.[Hf].[N] JIMUOUDLWPNFAY-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000003064 anti-oxidating effect Effects 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000004615 ingredient Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012774 insulation material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- QGLKJKCYBOYXKC-UHFFFAOYSA-N nonaoxidotritungsten Chemical compound O=[W]1(=O)O[W](=O)(=O)O[W](=O)(=O)O1 QGLKJKCYBOYXKC-UHFFFAOYSA-N 0.000 description 1
- 125000002524 organometallic group Chemical group 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000013618 particulate matter Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004062 sedimentation Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910001930 tungsten oxide Inorganic materials 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/02252—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by plasma treatment, e.g. plasma oxidation of the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
本发明公开一种半导体元件的制作方法,其步骤包含:在基底上形成一栅极堆叠结构,其包含一浮动栅、一栅极间介电层、一控制栅、以及一金属层,在栅极堆叠结构上形成一共形衬层,在衬层上覆盖一掩模层,其中掩模层低于金属层使得部分衬层裸露而出,以及进行一氮化步骤将裸露的衬层转化成氮化衬层,使得栅极堆叠结构中至少包含金属层的部分会为氮化衬层所覆盖。
Description
技术领域
本发明涉及一种半导体元件的制作方法,特别是涉及一种闪存存储器的制作方法。
背景技术
闪存存储器(Flash)是一种常见的非挥发性存储器,其存储单元可能包含了由通道区所分隔的源极区与漏极区,以及设置在通道区上方的电荷存储结构,其由浮动栅与电荷捕获层等部位所构成,并以一介电质,如氧化物,来与其他元件电性隔绝。举例而言,电荷存储结构与通道区之间一般都会设置穿隧介电质(即栅极氧化层)来彼此隔绝。存储单元的控制栅位于电荷存储结构的上方,其通过一电荷阻挡层(如现有技术中惯称的多晶硅间介电质或栅极间介电质,inter-poly dielectric,IPD)与电荷存储结构电性隔绝。如此,电荷存储结构可以设计成浮动栅的形式,使其电性浮动并与上下方的控制栅以及通道区绝缘。
为了进一步改善栅极及其互连结构的电性,集成电路制造商开发出使用纯金属层来作为字符线中导电层的技术,如钨金属(tungsten)由于具有便宜、高熔点(约3400℃)等特性,其非常适合用在现今的半导体制作工艺中。然而,使用未反应的钨作为字符线中的导电层会在集成电路制作工艺中产生问题。举例来说,在一般半导体制作工艺中,字符线堆叠结构的图形化后就会进行源极/漏极的再氧化步骤(re-oxidation),以修复源极/漏极角落区域受损的栅极氧化层并减轻热电子效应。在再氧化步骤期间,从堆叠结构侧壁裸露出来的钨在高温的有氧环境下会被快速地转变成三氧化钨(WO3)。这样钨的氧化现象会造成电性的劣化,如钨氧化物侧向隆起导致字符线与字符线之间彼此桥接,或者是钨导电层变质导致薄膜电阻过高等问题。
为了改善上述钨的氧化问题,目前业界一般的作法是在进行再氧化步骤之前先在字符线堆叠结构上覆盖一保护性的衬层,如一层氮化硅,来隔绝钨导电层接触到外界的氧化环境,这样的作法可以避免钨导电层氧化造成电性劣化等问题。然而,尽管上述形成衬层的作法解决了前述现有问题,其又会衍生出其他的问题。举例言之,一般氮化硅衬层需要达到一定的厚度以上(如大于3nm)才能有效地保护钨导电层不受氧化,然而过厚的衬层(如大于2nm)会容易残留在字符线堆叠结构的角落处而与该处裸露出的栅极氧化层接触,如此在后续的低掺杂漏极(lightly-doped drain,LDD)灰化步骤中,氮化硅衬层中的氮杂质会渗入并污染栅极氧化层,使得栅极/字符线的电性受到严重的劣化。再者,有些现有的衬层形成方法并不能很融洽地整合到元件制造的标准流程中,例如,衬层的存在有可能导致后续再氧化步骤的不足或变质。
是以,现今业界希望能够开发出能融洽地整合到现有存储元件制作工艺中的方法,其期能够顺利地解决前述字符线堆叠结构上钨导电层的氧化问题,并不会影响存储元件原有的电性。
发明内容
有鉴于前述现有技术所会遭遇到的问题,本发明特以提出了一种新颖的半导体元件制作方法,其特点在于可在现有的制作工艺中针对存储元件栅极堆叠结构中易受氧化的金属层部位强化保护,而不影响到堆叠结构其他部位的性质以及存储元件整体的电性表现。
本发明一实施例提供一种半导体元件的制作方法,其步骤包含提供一基底、在基底上形成一栅极堆叠结构,其中栅极堆叠结构从基底一侧开始依序包含一浮动栅、一栅极间介电层、一控制栅、以及一金属层、在基底与栅极堆叠结构上共形地形成一衬层、在衬层上形成一掩模层,其中掩模层的顶面低于金属层,使得部分衬层裸露而出、以及进行一氮化步骤将裸露出的衬层转化成一氮化衬层,使得栅极堆叠结构中至少包含金属层的部分会为氮化衬层所覆盖。
无疑地,本发明的这类目的与其他目的在阅者读过下文以多种图示与绘图来描述的优选实施例细节说明后将变得更为显见。
附图说明
图1-图7为本发明实施例一半导体元件制作流程的截面示意图。
符号说明
100 基底
101 穿隧介电层
102 衬层
102a 薄化衬层
103 掩模层
104 氮化衬层
105 氧化衬层
106 氧化层
107 氧化衬层
110 栅极堆叠结构
112 浮动栅
113 栅极间介电层
114 控制栅
115 金属层
116 硬掩模层
具体实施方式
本发明揭露了一种形成半导体元件、存储单元以及/或存储器阵列等结构的方法,其特点在于在裸露的导电质表面形成一衬层,并对一预定水平高度以上的该衬层进行一氮化处理使其改质。氮化处理后的衬层可在后续制作工艺期间提供导电质良好的保护效果,例如避免裸露的导电质氧化,而预定水平高度以下的衬层则可以加以薄化或移除,以避免其妨碍到常规制作工艺的进行或是影响到元件的电性。
文中使用的“氧化”一词可以代表半导体结构在氧自由基存在的环境下受热的行为,例如一临场蒸气生成制作工艺(in-situ steam generation,ISSG),但不限于此。
文中使用的“氮化衬层”一词指的是从衬层衍生出的材质,相较于原始的衬层,其材质具有大量的氮成分,或者是其氮成分相对较多。
文中使用的“基底”一词,其代表且包含了那些让半导体元件或存储单元等组成物形成在其上的基材或构体。此基底可为一种半导体基底、一种形成在支撑结构上的半导体基材、或是一种金属电极、或是一种其上形成有一或多个材料、结构、区域的半导体基底。此基底可为传统的硅基底或是含有半导体材料的块材。此处所称的“基底”一词不只代表了传统的硅晶片,其也包含了绝缘层覆硅基底(silicon-on-insulator,SOI),如硅蓝宝石基底(silicon-on-sapphire,SOS)、硅玻璃基底(silicon-on-glass,SOG)、硅底材上的硅外延层,或是其他的半导体或光电材质,如硅锗(SiGe)、锗(Ge)、砷化镓(GaAs)、氮化镓(GaN)、磷化铟(InP)等材料。再者,当下文描述中使用“基底”一词时,其可代表所有先前制作工艺阶段已经形成在该半导体基材之上或之中的材料、区域、或接点等。
文中关于空间或方位上的用词,如“下方”、“之下”、“较低/低于”、“底”、“上方”、“之上”、“较高/高于”、“顶”、“前”、“后”、“左”、“右”等词,其用来便于描述附图中所绘示的组成元件或特征之间的相对关系。除非有特别加以指明,不然这些空间上的用词都意欲含括图中所绘示以外的其他方位或位向。举例言之,假使图中的物件被反过来,原本被描述成位于某其他元件“下方”或“之下”的元件会变成位于该其他元件“上方”或“之上”。故此,视该用词的前后文义而定,对本领域的一般技术人士而言,“下方”一词可能会同时含括了“上方”与“下方”的方位。文中的物件也可能以其他方式来定位(如转九十度或反向等),而文中使用的这类空间相关的描述词也以此来释义。
当文中指出某元件位于另一元件“上”或“上方”时,其代表且包含了该元件直接位于该另一元件正上方、相邻、之下、或是与该另一元件直接接触等含意,其也包含了该元件并非直接位于该另一元件正上方、相邻、之下、或是与该另一元件直接接触等含意。相反地,当某元件被描述成直接位于该另一元件上时,不会有任何其他元件介于其间。
除非文中有特别加以指出,不然文中所描述的材料都可以任何合适的技术来形成,如旋涂法、刮涂法、浸涂法、毯覆式刮涂法、化学气相沉积(CVD)、原子层沉积法(ALD)、以及物理气相沉积法(PVD)等,但不限于此。或者,材料可以在当前制作工艺中(in-situ)直接生长。视所欲形成的特定材料而定,本领域的一般技术人士可以选择要用来沉积或成长这些材料的技术。
除非文中有特别加以指出,不然文中所述关于材料的移除动作都可以任何合适的技术来达成,如蚀刻或磨平等作法,但不限于此。
文中所揭露的方法可用来形成至少一种具有导电区域的半导体元件结构。举例言之,所揭露的方法可用来形成导电接触、导电互连结构、晶体管、以及存储元件等,如动态随机存取存储(DRAM)单元、闪存存储器(flash,包含具有NAND,NOR,AND等逻辑单元的存储器阵列)、或是其他的存储器架构。
在下文的细节描述中,元件符号会标示在随附的图示中成为其中的一部份,并且以可实行该实施例的特例描述方式来表示。这类实施例会说明足够的细节使该领域的一般技术人士得以具以实施。阅者需了解到本发明中也可利用其他的实施例或是在不悖离所述实施例的前提下作出结构性、逻辑性、及电性上的改变。因此,下文的细节描述将不欲被视为是一种限定,反之,其中所包含的实施例将由随附的权利要求来加以界定。
请参照图1-图7,其绘示出根据本发明优选实施例中一半导体元件制作流程的截面示意图。需注意,为了图示简明以及说明清晰之故,附图中都仅将绘释出单一半导体元件,如一存储单元结构,且其中可能省略了某些现有且非本发明特点的组成部件,如源极、漏极、或是接触窗等。
首先,如图1所示,提供一基底100作为半导体元件。基底100可为一硅基材,如掺有掺质(如n型或p型掺质)的单晶硅基材,或是具有预先形成的半导性区域的半导体晶片。基底100可能为一同质性基材,或者其上可能已经形成或整合有多种不同的集成电路结构。一穿隧介电层101可形成在基底100上,其材质可包含二氧化硅(SiO2)、氮化硅(Si3N4)、或其他合适的材料。穿隧介电层101也可能是由多个电性绝缘材质或区域所构成。
复参照图1,在形成穿隧介电层101后,接着在穿隧介电层101上形成一栅极堆叠结构110。栅极堆叠结构110从靠近基底100一侧开始依序包含浮动栅(floating gate,FG)112、栅极间介电层(inter-gate/poly dielectric,IPD)113、控制栅(control gate,CG)114、金属层115、以及硬掩模层116等部位。栅极堆叠结构110作为一电荷存储节点,其通过穿隧介电层101与基底100的主动区域(active area,AA)电容耦接。栅极堆叠结构110可以一般的光刻蚀刻制作工艺来形成,举例言之,首先在穿隧介电层101上依序形成浮动栅112、栅极间介电层113、控制栅114、金属层115、以及硬掩模层116等部位的材料层。接着进行第一次光刻蚀刻制作工艺将硬掩模层116图形化成半导体元件的形状,再以硬掩模层116为蚀刻掩模进行第二次蚀刻制作工艺来将下方的材料层部位一起图形化,形成栅极堆叠结构110。需注意在此实施例中,栅极堆叠结构110的图形化步骤并未将穿隧介电层101也图形化,其仅受到蚀刻步骤而使厚度有所删减。当然,在其他实施例中,栅极堆叠结构110部位以外的穿隧介电层101也有可能被完全移除。
在栅极堆叠结构110中,浮动栅112是一电荷负载结构,设定来捕捉电荷。浮动栅112材质可包含一或多种元素金属,如钨、钛、钴等,或是含有金属成分的化合物,如金属硅化物、金属氮化物等,或是掺有导电掺质的半导体材料,如掺杂过的多晶硅,但不以此为限,其可使用诸如化学气相沉积(CVD)、有机金属气相沉积(MOCVD)、物理气相沉积(PVD)、原子层沉积法(ALD)、或其他合适的方法来形成。
在栅极堆叠结构110中,栅极间介电层113形成在浮动栅112与控制栅114之间,其用来阻隔两栅极之间的电荷流通。以如此方式,电荷存储结构可以设计成浮动栅的形式,使其电性浮动并与上下方的控制栅以及通道区绝缘。栅极间介电层113的材质可包含二氧化硅(SiO2)或氮化硅(Si3N4),或是由两者所组成的ONO介电复层结构(SiO2-Si3N4-SiO2)。栅极间介电层113也可使用高介电(high-k)材料来形成,如氧化铝(Al2O3)或氮氧化铪硅(HfSiON),但不以此为限。同样地,栅极间介电层113可使用ALD、CVD、PVD或是喷气沉积法(jet vapor deposition,JVD)等方式来形成。以ONO介电复层结构为例,第一层SiO2与中间层的Si3N4以ALD法沉积,而最外层的SiO2以CVD法沉积。在某些实施例中,栅极间介电层113也可能会包覆住整个浮动栅112结构。
在栅极堆叠结构110中,控制栅114形成在栅极间介电层113之上并通过栅极间介电层113与浮动栅112电容耦接,其可为存储单元结构中字符线的一部分。控制栅114的材质可为掺有导电掺质的半导体材料,如掺杂过的多晶硅,或是金属硅化物或金属氮化物等,但不以此为限。在本发明实施例中,控制栅也可能是由一个掺杂导电区域(如前述掺杂过的多晶硅)以及一个金属材质区域所构成的复层结构,如图1所示实施例中,控制栅114上还形成有一金属层115,该金属层也可以视为是控制栅的一部分,其材质可为钨(W)或镍(Ni)。在字符线中设置纯金属层有助于改善栅极及其互连结构的电性,但未反应的纯金属层(如钨)在后续的加热制作工艺(如源极/漏极的再氧化步骤)容易氧化变质,造成电性的劣化,此即本发明所欲解决的问题。
除此之外,栅极堆叠结构110的最上方还有一上盖层116,其使用绝缘材质形成,如SiO2、Si3N4、或是SiON等。或者,在某些实施例中,可直接使用前述的硬掩模层作为上盖层。
接下来请参照图2。在形成栅极堆叠结构110后,接着在基底100以及栅极堆叠结构110上共形地覆盖一保护性的衬层102,用来保护栅极堆叠结构110的侧壁不受后续制作工艺环境影响,如氧化环境或是蚀刻环境,或是保护基底上的主动区域不受到控制栅114或金属层115的金属粒子所污染。衬层102会从栅极堆叠结构110处延伸共形地覆盖并接触整个穿隧介电层101上。在此实施例中,衬层102的材质与上盖层116相似,其优选可使用ALD法以SiO2、Si3N4、或是SiON等材质来形成。
在本发明实施例中,尽管衬层102存在可以有效地避免金属层115氧化或是杂质粒子污染问题,但是由于衬层102有与穿隧介电层101直接接触的关系,当后续有进行高温制作工艺时,衬层102中的杂质粒子(如氮杂质)很容易扩散到穿隧介电层101中。特别是为了有效保护金属层115,衬层102都会有设定成具有一定厚度(如>2nm),然而过厚的衬层102容易残留,促使杂质粒子更容易扩散进入穿隧介电层101中,特别是从局部应力较大的角落处,从而显著地影响半导体元件的电性。
为了解决上述问题,本发明的作法是对衬层102作局部性的强化,以使衬层102在发挥保护性功效的同时又不会影响到敏感的元件电性。现在请参照图3,首先在衬层102上形成一掩模层103以覆盖衬层102以及基底100,接着对掩模层103进行一选择性的回蚀制作工艺(etch back),使得掩模层103的顶面低于栅极堆叠结构100中的金属层115,以让部分的衬层102裸露而出。掩模层103的材质可为一般的光致抗蚀剂或其他蚀刻率与衬层102有明显差别的材料,不以此为限。此步骤的目的在于至少让覆盖住金属层的衬层102部位裸露而出,以进行后续的强化动作。
接下来请参照图4。在裸露出覆盖金属层的衬层102部位后,接着对裸露的衬层102进行一氮化步骤。此氮化步骤可包含等离子体氮化制作工艺(plasma nitridation)以及/或后氮化回火制作工艺(post nitridation annealing,PNA),其目的在于将覆盖金属层的衬层102部位改质成更具保护性,如更耐蚀刻以及抗氧化。从图4可以看出,经过此氮化步骤,上半部的衬层已经转变为材质不同的氮化衬层104。
现在请参照图5,在形成氮化衬层104之后,接着进行一灰化步骤(ashing)将掩模层103完全移除,裸露出下方原有衬层102。接着进行一选择性的湿蚀刻制作工艺移除部分的原有衬层102,使其厚度减少至一预定值(如≤2nm)而形成一薄化衬层102a。或者,在某些情况下也可将原有衬层102完全移除。在此步骤中,由于氮化衬层104的材质已与原有衬层102不同,故湿蚀刻制作工艺仅会移除原有衬层102,不会对氮化衬层104造成任何影响。此步骤的目的在于削减甚至移除衬层102下方与穿隧介电层101接触的部位,使得穿隧介电层101不易受到杂质粒子扩散的影响。
在衬层102薄化至一定厚度以下之后,接着即可进行后续常规的半导体元件制作步骤,如进行一低掺杂漏极(lightly-doped drain,LDD)的灰化步骤。如图6所示,LDD灰化步骤是用来移除形成LDD区域时所使用的光致抗蚀剂,一般的灰化制作工艺是在含氧的等离子体环境下进行,其会将残留在基底100上的光致抗蚀剂完全去除,并使得薄化衬层102a转变为一氧化层106。同时,灰化制作工艺也会氧化氮化衬层104,使其表面转化成氮氧化硅层105。
最后,请参照图7,在LDD灰化步骤后,视产品与制作工艺而定,可再选择性地进行一氧化制作工艺来平缓整个栅极堆叠结构110的表面,例如使用Tokyo Electron的槽型平面天线(slot plane antenna,SPA)等离子体氧化制作工艺来对栅极堆叠结构110的表面进行氧化处理。从图7可以看到,栅极堆叠结构110结构上的氮化衬层104、氮氧化硅层105以及氧化层106在此氧化制作工艺的作用下与下方的穿隧介电层101整合成一单一较为平整的氧化衬层107保护结构。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (10)
1.一种半导体元件的制作方法,包含:
提供一基底;
在该基底上形成一栅极堆叠结构,该栅极堆叠结构从靠近该基底的一侧开始依序包含浮动栅、栅极间介电层、控制栅、以及金属层;
在该基底与该栅极堆叠结构上共形地形成一衬层;
在该衬层上形成一掩模层,其中该掩模层的顶面低于该栅极堆叠结构的该金属层,使得部分的该衬层裸露而出;以及
进行一氮化步骤,将裸露出的该衬层转化成一氮化衬层,使得该栅极堆叠结构中至少包含该金属层的部分会为该氮化衬层所覆盖。
2.如权利要求1所述的半导体元件的制作方法,其中形成该掩模层的步骤还包含对该掩模层进行一回蚀制作工艺,使得该掩模层的顶面低于该栅极堆叠结构的该金属层并让部分的该衬层裸露而出。
3.如权利要求1所述的半导体元件的制作方法,还包含:
在该氮化步骤后将该掩模层完全移除,以裸露出剩余的该衬层;以及
薄化裸露出的剩余的该衬层。
4.如权利要求3所述的半导体元件的制作方法,其中裸露出的剩余的该衬层通过进行一湿蚀刻制作工艺来薄化。
5.如权利要求3所述的半导体元件的制作方法,还包含在该薄化步骤后进行一槽型平面天线等离子体氧化制作工艺,以氧化该氮化衬层以及薄化后的该衬层。
6.如权利要求3所述的半导体元件的制作方法,其中薄化后的该衬层厚度小于2纳米(nm)。
7.如权利要求1所述的半导体元件的制作方法,还包含在该氮化步骤后,在该栅极堆叠结构中至少包含该金属层的部分被该氮化衬层所覆盖的情况下进行一低掺杂漏极(LDD)的灰化步骤。
8.如权利要求1所述的半导体元件的制作方法,其中该氮化步骤包含等离子体氮化制作工艺以及后氮化回火制作工艺。
9.如权利要求1所述的半导体元件的制作方法,其中该金属层的材料为钨、镍或钴。
10.如权利要求1所述的半导体元件的制作方法,其中该衬层的材料为氧化硅、氮化硅或氮氧化硅。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW104115365 | 2015-05-14 | ||
TW104115365A TWI555066B (zh) | 2015-05-14 | 2015-05-14 | 半導體元件的製作方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN106298676A true CN106298676A (zh) | 2017-01-04 |
CN106298676B CN106298676B (zh) | 2019-04-16 |
Family
ID=57210929
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510291873.7A Active CN106298676B (zh) | 2015-05-14 | 2015-06-01 | 半导体元件的制作方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9490349B1 (zh) |
CN (1) | CN106298676B (zh) |
TW (1) | TWI555066B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110419104A (zh) * | 2017-08-31 | 2019-11-05 | 长江存储科技有限责任公司 | 三维存储装置的阵列共源极结构以及其形成方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108630700A (zh) * | 2017-03-22 | 2018-10-09 | 中芯国际集成电路制造(上海)有限公司 | 闪存器件及其制造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1376309A (zh) * | 1999-09-02 | 2002-10-23 | 先进微装置公司 | 封装钨栅极mos晶体管与存储单元及其制造方法 |
US20030119334A1 (en) * | 2001-12-22 | 2003-06-26 | Kwak Noh Yeal | Method of manufacturing a flash memory cell |
US20050277252A1 (en) * | 2004-06-15 | 2005-12-15 | Young-Sub You | Methods of forming a gate structure of a non-volatile memory device and apparatus for performing the same |
TW200837896A (en) * | 2007-03-09 | 2008-09-16 | Nanya Technology Corp | Method for fabricating flash memory device |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4845917B2 (ja) * | 2008-03-28 | 2011-12-28 | 株式会社東芝 | 半導体装置の製造方法 |
DE102012205977B4 (de) * | 2012-04-12 | 2017-08-17 | Globalfoundries Inc. | Halbleiterbauelement mit ferroelektrischen Elementen und schnellen Transistoren mit Metallgates mit großem ε sowie Herstellungsverfahren |
-
2015
- 2015-05-14 TW TW104115365A patent/TWI555066B/zh active
- 2015-06-01 CN CN201510291873.7A patent/CN106298676B/zh active Active
- 2015-07-28 US US14/811,823 patent/US9490349B1/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1376309A (zh) * | 1999-09-02 | 2002-10-23 | 先进微装置公司 | 封装钨栅极mos晶体管与存储单元及其制造方法 |
US20030119334A1 (en) * | 2001-12-22 | 2003-06-26 | Kwak Noh Yeal | Method of manufacturing a flash memory cell |
US20050277252A1 (en) * | 2004-06-15 | 2005-12-15 | Young-Sub You | Methods of forming a gate structure of a non-volatile memory device and apparatus for performing the same |
TW200837896A (en) * | 2007-03-09 | 2008-09-16 | Nanya Technology Corp | Method for fabricating flash memory device |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN110419104A (zh) * | 2017-08-31 | 2019-11-05 | 长江存储科技有限责任公司 | 三维存储装置的阵列共源极结构以及其形成方法 |
US10658379B2 (en) | 2017-08-31 | 2020-05-19 | Yangtze Memory Technologies Co., Ltd. | Array common source structures of three-dimensional memory devices and fabricating methods thereof |
CN110419104B (zh) * | 2017-08-31 | 2020-05-22 | 长江存储科技有限责任公司 | 三维存储装置的阵列共源极结构以及其形成方法 |
CN111430358A (zh) * | 2017-08-31 | 2020-07-17 | 长江存储科技有限责任公司 | 三维存储装置的阵列共源极结构以及其形成方法 |
CN111430358B (zh) * | 2017-08-31 | 2021-03-12 | 长江存储科技有限责任公司 | 三维存储装置的阵列共源极结构以及其形成方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI555066B (zh) | 2016-10-21 |
US9490349B1 (en) | 2016-11-08 |
CN106298676B (zh) | 2019-04-16 |
TW201640567A (zh) | 2016-11-16 |
US20160336431A1 (en) | 2016-11-17 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN112002696B (zh) | 3dnand存储器件的结构及其形成方法 | |
US7511331B2 (en) | Semiconductor device having side wall spacers | |
KR100469129B1 (ko) | 불휘발성 메모리 장치 및 그 제조방법 | |
US10573513B2 (en) | Semiconductor structures including liners comprising alucone and related methods | |
CN102315224B (zh) | 使用FinFET的非易失性存储器件及其制造方法 | |
KR20060028765A (ko) | 비휘발성 메모리 디바이스 | |
US7847333B2 (en) | Structured, electrically-formed floating gate for flash memories | |
CN108010915B (zh) | 浮栅型闪存sab制作方法以及浮栅型闪存结构 | |
US9418864B2 (en) | Method of forming a non volatile memory device using wet etching | |
US20140374811A1 (en) | Methods of forming semiconductor device structures and related semiconductor devices and structures | |
US6495420B2 (en) | Method of making a single transistor non-volatile memory device | |
CN106298676A (zh) | 半导体元件的制作方法 | |
US6255167B1 (en) | Method of forming high density buried bit line flash EEPROM memory cell with a shallow trench floating gate | |
US6242773B1 (en) | Self-aligning poly 1 ono dielectric for non-volatile memory | |
US8030165B2 (en) | Poly gate etch method and device for sonos-based flash memory | |
KR20080081581A (ko) | 비휘발성 메모리 소자의 제조 방법 | |
US11223014B2 (en) | Semiconductor structures including liners comprising alucone and related methods | |
US20030040152A1 (en) | Method of fabricating a NROM cell to prevent charging | |
KR20050064233A (ko) | Sonos형 비휘발성 메모리 소자 및 그 제조 방법 | |
US20110287625A1 (en) | Methods of forming a pattern, methods of forming a gate structure and methods of manufacturing a semiconductor device using the same | |
US20120244695A1 (en) | Method for fabricating flash memory device and floating gate therein | |
CN111341778B (zh) | 一种nand闪存器件及形成方法 | |
US9431406B1 (en) | Semiconductor device and method of forming the same | |
KR100554985B1 (ko) | Sonos형 비휘발성 메모리 소자 및 그 제조 방법 | |
CN118055617A (zh) | 降低控制栅电阻的结构及其制造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
TR01 | Transfer of patent right |
Effective date of registration: 20190703 Address after: Hsinchu Science Park, Taiwan, China Patentee after: Lijing Jicheng Electronic Manufacturing Co., Ltd. Address before: Hsinchu Science Park, Taiwan, China Patentee before: Powerflash Technology Corporation |
|
TR01 | Transfer of patent right |