CN106298657B - Pmos器件及其集成工艺方法 - Google Patents
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Abstract
一种PMOS器件及其集成工艺方法。PMOS器件集成工艺方法包括:在P型衬底中形成由浅沟槽隔离的高压与低压N阱区;在高压与低压N阱区上分别形成栅极结构;涂覆第一光刻胶层,定义第一光刻胶图案,去除高压N阱区上方光刻胶,对高压N阱区执行离子注入以形成高压PMOS器件的轻掺杂扩散区;去除光刻胶,形成高压N阱区与低压N阱区上的栅极结构的侧墙,涂覆第二光刻胶层,利用模板定义第二光刻胶图案,同时去除高压N阱区和低压N阱区上方光刻胶,对高压N阱区与低压N阱区执行以相对于衬底表面成倾斜角度的离子注入,以形成低压PMOS器件的轻掺杂扩散区,在高压PMOS器件的轻掺杂扩散区周围形成二次扩散注入区;形成高压PMOS重掺杂的源漏区和低压PMOS重掺杂的源漏区。
Description
技术领域
本发明涉及半导体制造领域,更具体地说,本发明涉及一种PMOS器件及其集成工艺方法。
背景技术
通常HVPMOS(高压PMOS)与LVPMOS(低压PMOS)器件在集成过程中,由于器件性能差异,必须要分别形成其N阱注入和PLDD(P型轻掺杂扩散注入区)注入,但是HVPMOS与LVPMOS器件共用重掺杂源漏注入。
图1至图6示意性地示出了根据现有技术的PMOS器件集成工艺方法。
如图1至图6所示,根据现有技术的PMOS器件集成工艺方法包括:在P型衬底100中形成由浅沟槽隔离的高压N阱区10与低压N阱区20,在高压N阱区10与低压N阱区20上分别形成由栅极氧化层200和栅极多晶硅300组成的栅极结构;涂覆第一光刻胶层,利用模板定义第一光刻胶图案30,去除高压N阱区10上方光刻胶,对高压N阱区10执行离子注入以形成高压PMOS器件的轻掺杂扩散区40,随后去除第一光刻胶图案30;涂覆第二光刻胶层,利用模板定义第二光刻胶图案50,去除低压N阱区20上方光刻胶,对低压N阱区20执行离子注入以形成低压PMOS器件的轻掺杂扩散区60,随后去除第二光刻胶图案50;形成栅极结构的侧墙70;随后,涂覆第三光刻胶层,利用模板定义第三光刻胶图案,同时去除高压N阱区10和低压N阱区20上方光刻胶,离子注入分别形成高压PMOS的重掺杂源漏区80和低压PMOS的重掺杂源漏区90。
如上所述,在根据现有技术的PMOS器件集成工艺方法中,分别形成其N阱注入和P型轻掺杂源漏注入区,因此工艺相对复杂。
希望提供一种能够在不影响器件性能的情况下简化工艺节约成本的PMOS器件集成工艺方法。
发明内容
本发明所要解决的技术问题是针对现有技术中存在上述缺陷,提供一种能够在不影响器件性能的情况下简化工艺节约成本的PMOS器件集成工艺方法以及由此获得的PMOS器件。
为了实现上述技术目的,根据本发明,提供了一种PMOS器件集成工艺方法,包括:
第一步骤:在P型衬底中形成由浅沟槽隔离的高压N阱区与低压N阱区;
第二步骤:在高压N阱区与低压N阱区上分别形成由栅极氧化层和栅极多晶硅组成的栅极结构;
第三步骤:涂覆第一光刻胶层,利用模板定义第一光刻胶图案,去除高压N阱区上方光刻胶,对高压N阱区执行离子注入以形成高压PMOS器件的轻掺杂扩散区,随后去除光刻胶;
第四步骤:形成栅极结构的侧墙;涂覆第二光刻胶层,利用模板定义第二光刻胶图案,同时去除高压N阱区和低压N阱区上方光刻胶,对高压N阱区与低压N阱区执行以相对于衬底表面成倾斜角度的离子注入,以形成低压PMOS器件的轻掺杂扩散区,并且在高压PMOS器件的轻掺杂源漏注入区周围形成二次扩展注入区;
第五步骤:
离子注入分别形成高压PMOS重掺杂的源漏区和低压PMOS重掺杂的源漏区。
优选地,在第三步骤,利用第一光刻胶图案对高压N阱区执行的离子注入是成倾斜角度的离子注入,其中离子注入方向与衬底表面法线之间的角度为10°~45°。
优选地,第四步骤的相对于衬底表面成倾斜角度的离子注入的方向与衬底表面法线之间的角度为5°~45°。
优选地,第四步骤的相对于衬底表面成倾斜角度的离子注入的P型离子注入能量为5~150keV。
优选地,高压PMOS器件的轻掺杂扩散注入区的掺杂体浓度为1e17~1e19cm-3。
优选地,所述P型衬底的体掺杂浓度为1e14~1e16cm-3。
优选地,所述高压N阱区与低压N阱区的掺杂浓度为1e16~1e18cm-3。
优选地,低压PMOS器件的轻掺杂扩散注入区的掺杂体浓度为1e17~1e19cm-3。
优选地,侧墙的成分为氧化硅或者氮化硅,侧墙的厚度为10A~1000A。
优选地,所述高压PMOS重掺杂的源漏区和低压PMOS重掺杂的源漏区体浓度为1e18~1e22cm-3。
为了实现上述技术目的,根据本发明,还提供了一种采用根据上述PMOS器件集成工艺方法制成的PMOS器件。
附图说明
结合附图,并通过参考下面的详细描述,将会更容易地对本发明有更完整的理解并且更容易地理解其伴随的优点和特征,其中:
图1至图6示意性地示出了根据现有技术的PMOS器件集成工艺方法。
图7示意性地示出了根据本发明优选实施例的PMOS器件集成工艺方法的第一步骤。
图8示意性地示出了根据本发明优选实施例的PMOS器件集成工艺方法的第二步骤。
图9示意性地示出了根据本发明优选实施例的PMOS器件集成工艺方法的第三步骤。
图10示意性地示出了根据本发明优选实施例的PMOS器件集成工艺方法的第四步骤。
图11示意性地示出了根据本发明优选实施例的PMOS器件集成工艺方法的第五步骤。
需要说明的是,附图用于说明本发明,而非限制本发明。注意,表示结构的附图可能并非按比例绘制。并且,附图中,相同或者类似的元件标有相同或者类似的标号。
具体实施方式
为了使本发明的内容更加清楚和易懂,下面结合具体实施例和附图对本发明的内容进行详细描述。
图7至图11示意性地示出了根据本发明优选实施例的PMOS器件集成工艺方法的各个步骤。
如图7至图11所示,根据本发明优选实施例的PMOS器件集成工艺方法包括:
第一步骤:在P型衬底100中形成由浅沟槽隔离的高压N阱区10与低压N阱区20;
优选地,所述P型衬底100的体掺杂浓度为1e14~1e16cm-3,所述高压N阱区10与低压N阱区20的掺杂浓度为1e16~1e18cm-3。
第二步骤:在高压N阱区10与低压N阱区20上分别形成由栅极氧化层200和栅极多晶硅300组成的栅极结构;
第三步骤:涂覆第一光刻胶层,利用模板定义第一光刻胶图案30,去除高压N阱区10上方光刻胶,对高压N阱区10执行离子注入以形成高压PMOS器件的轻掺杂扩散区40,随后去除光刻胶;
优选地,在第三步骤,利用第一光刻胶图案30对高压N阱区10执行的离子注入是成倾斜角度的离子注入,其中离子注入方向与衬底表面法线之间的角度为10°~45°。
优选地,高压PMOS器件的轻掺杂扩散区40的掺杂浓度为1e17~1e19cm-3。高压PMOS的P型轻掺杂扩散区与N阱形成缓变PN结。
第四步骤:形成高压N阱区10与低压N阱区20上的栅极结构的侧墙70,涂覆第二光刻胶层,利用模板定义第二光刻胶图案,同时去除高压N阱区和低压N阱区上方光刻胶,对高压N阱区10与低压N阱区20执行以相对于衬底表面成倾斜角度的离子注入(即,离子注入方向与衬底表面不垂直),以形成低压PMOS器件的轻掺杂扩散区61,并且在高压PMOS器件的轻掺杂源漏注入区40周围形成二次扩展注入区41;
优选地,第四步骤的相对于衬底表面成倾斜角度的离子注入的方向与衬底表面法线之间的角度为5°~45°。
优选地,第四步骤的相对于衬底表面成倾斜角度的离子注入的P型离子注入能量为5~150keV。
优选地,低压PMOS器件的轻掺杂扩散区61的掺杂体浓度为1e17~1e19cm-3。
优选地,侧墙70的成分为氧化硅或者氮化硅。优选地,侧墙70的厚度为10A~1000A。
第五步骤:形成高压PMOS的重掺杂源漏区80和低压PMOS的重掺杂源漏区90。
优选地,高压PMOS的重掺杂源漏区80和低压PMOS的重掺杂源漏区90的体掺杂浓度为1e18~1e22cm-3。
在本发明的另一优选实施例中,本发明还提供了一种采用上述PMOS器件集成工艺方法制成的PMOS器件,如图11所示。
本发明与传统工艺不同,省去LVPMOS的P型轻掺杂扩散注入的掩模板,同时将这步注入挪到源漏注入之前,采用源漏注入的掩膜版进行LVPMOS的P型轻掺杂扩散注入区的注入。这样HVPMOS也会打入这步注入,为了不影响HVPMOS的器件性能,可以对HVPMOS的P型轻掺杂源漏的注入进行微调。同时由于HV器件一般对器件的击穿电压要求较高,其HVPMOS的P型轻掺杂扩散注入一般在多晶硅栅刻蚀完成之后,斜角注入,形成缓变的HVPMOS的P型轻掺杂扩散注入区与N阱结,因此不能省去HVPMOS的P型轻掺杂扩散注入这步掩膜版而与源漏注入共用掩膜版。LVPMOS器件不要求较高的击穿电压,将LVPMOS的P型轻掺杂源漏注入挪到源漏这步,相比于传统结构,不会造成器件的性能漂移。
此外,需要说明的是,除非特别说明或者指出,否则说明书中的术语“第一”、“第二”、“第三”等描述仅仅用于区分说明书中的各个组件、元素、步骤等,而不是用于表示各个组件、元素、步骤之间的逻辑关系或者顺序关系等。
可以理解的是,虽然本发明已以较佳实施例披露如上,然而上述实施例并非用以限定本发明。对于任何熟悉本领域的技术人员而言,在不脱离本发明技术方案范围情况下,都可利用上述揭示的技术内容对本发明技术方案作出许多可能的变动和修饰,或修改为等同变化的等效实施例。因此,凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所做的任何简单修改、等同变化及修饰,均仍属于本发明技术方案保护的范围内。
而且还应该理解的是,本发明并不限于此处描述的特定的方法、化合物、材料、制造技术、用法和应用,它们可以变化。还应该理解的是,此处描述的术语仅仅用来描述特定实施例,而不是用来限制本发明的范围。必须注意的是,此处的以及所附权利要求中使用的单数形式“一个”、“一种”以及“该”包括复数基准,除非上下文明确表示相反意思。因此,例如,对“一个元素”的引述意味着对一个或多个元素的引述,并且包括本领域技术人员已知的它的等价物。类似地,作为另一示例,对“一个步骤”或“一个装置”的引述意味着对一个或多个步骤或装置的引述,并且可能包括次级步骤以及次级装置。应该以最广义的含义来理解使用的所有连词。因此,词语“或”应该被理解为具有逻辑“或”的定义,而不是逻辑“异或”的定义,除非上下文明确表示相反意思。此处描述的结构将被理解为还引述该结构的功能等效物。可被解释为近似的语言应该被那样理解,除非上下文明确表示相反意思。
而且,本发明实施例的方法和/或系统的实现可包括手动、自动或组合地执行所选任务。而且,根据本发明的方法和/或系统的实施例的实际器械和设备,可利用操作系统通过硬件、软件或其组合实现几个所选任务。
Claims (10)
1.一种PMOS器件集成工艺方法,其特征在于包括:
第一步骤:在P型衬底中形成由浅沟槽隔离的高压N阱区与低压N阱区;
第二步骤:在高压N阱区与低压N阱区上分别形成高压栅极氧化层和低压栅氧化层,以及由栅极多晶硅组成的栅极结构;
第三步骤:涂覆第一光刻胶层,利用模板定义第一光刻胶图案,去除高压N阱区上方光刻胶,对高压N阱区执行离子注入以形成高压PMOS器件的轻掺杂扩散区;
第四步骤:去除光刻胶,形成高压N阱区与低压N阱区上的栅极结构的侧墙,涂覆第二光刻胶层,利用模板定义第二光刻胶图案,同时去除高压N阱区和低压N阱区上方光刻胶,对高压N阱区与低压N阱区执行以相对于衬底表面成倾斜角度的离子注入,以形成低压PMOS器件的轻掺杂扩散区,并且在高压PMOS器件的轻掺杂扩散区周围形成二次扩散注入区;
第五步骤:形成高压PMOS重掺杂的源漏区和低压PMOS重掺杂的源漏区,源漏区的注入与低压PMOS器件的轻掺杂扩散区的注入共用掩膜板。
2.根据权利要求1所述的PMOS器件集成工艺方法,其特征在于,在第三步骤,利用第一光刻胶图案对高压N阱区执行的离子注入是成倾斜角度的离子注入,其中离子注入方向与衬底表面法线之间的角度为10°~45°。
3.根据权利要求1或2所述的PMOS器件集成工艺方法,其特征在于,第四步骤的相对于衬底表面成倾斜角度的离子注入的方向与衬底表面法线之间的角度为5°~45°。
4.根据权利要求1或2所述的PMOS器件集成工艺方法,其特征在于,第四步骤的相对于衬底表面成倾斜角度的离子注入的P型离子注入能量为5~150keV。
5.根据权利要求1或2所述的PMOS器件集成工艺方法,其特征在于,高压PMOS器件的轻掺杂扩散注入区的掺杂体浓度为1e17~1e19cm-3。
6.根据权利要求1或2所述的PMOS器件集成工艺方法,其特征在于,所述P型衬底的掺杂体浓度为1e14~1e16cm-3,所述高压N阱区与低压N阱区的掺杂体浓度为1e16~1e18cm-3。
7.根据权利要求1或2所述的PMOS器件集成工艺方法,其特征在于,低压PMOS器件的轻掺杂扩散注入区的掺杂体浓度为1e17~1e19cm-3。
8.根据权利要求1或2所述的PMOS器件集成工艺方法,其特征在于,侧墙的成分为氧化硅或者氮化硅,侧墙的厚度为10A~1000A。
9.根据权利要求1或2所述的PMOS器件集成工艺方法,其特征在于,所述高压PMOS重掺杂的源漏区和低压PMOS重掺杂的源漏区体浓度为1e18~1e22cm-3。
10.一种采用根据权利要求1至9之一所述的PMOS器件集成工艺方法制成的PMOS器件。
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