CN106206514A - 作为垂直晶体管的局部互连件的顶部金属焊盘 - Google Patents

作为垂直晶体管的局部互连件的顶部金属焊盘 Download PDF

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Publication number
CN106206514A
CN106206514A CN201510262838.2A CN201510262838A CN106206514A CN 106206514 A CN106206514 A CN 106206514A CN 201510262838 A CN201510262838 A CN 201510262838A CN 106206514 A CN106206514 A CN 106206514A
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Prior art keywords
source
drain
vertical transistor
semiconductor channel
drain pad
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CN201510262838.2A
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CN106206514B (zh
Inventor
连万益
邱奕勋
游家权
黄禹轩
王志豪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
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    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
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Abstract

一种集成电路结构包括第一垂直晶体管和第二垂直晶体管。第一垂直晶体管包括第一半导体沟道、位于第一半导体沟道上方的第一顶部源极/漏极区以及覆盖第一顶部源极/漏极区的第一顶部源极/漏极焊盘。第二垂直晶体管包括第二半导体沟道、位于第二半导体沟道上方的第二顶部源极/漏极区以及覆盖第二顶部源极/漏极区的第二顶部源极/漏极焊盘。局部互连件互连第一顶部源极/漏极焊盘和第二顶部源极/漏极焊盘。第一顶部源极/漏极焊盘、第二顶部源极/漏极焊盘和局部互连件是连续区域的部分，在第一顶部源极/漏极焊盘、第二顶部源极/漏极焊盘和局部互连件之间没有可辨识的界面。本发明还涉及作为垂直晶体管的局部互连件的顶部金属焊盘。

Description

作为垂直晶体管的局部互连件的顶部金属焊盘
技术领域
本发明涉及集成电路器件，更具体地，涉及作为垂直晶体管的局部互连件的顶部金属焊盘。
背景技术
晶体管是现代集成电路的关键部件。为了满足越来越快的切换速度的需求，晶体管的驱动电流需要越来越高。同时，晶体管的栅极长度不断地按比例缩小。按比例缩小栅极长度导致称为“短沟道效应”的不期望的效应，由此栅极对电流的控制受到连累。除了短沟道效应之外，漏极诱导势垒降低(DIBL)和亚阈值斜率的降低均导致晶体管的性能的降低。
多栅极晶体管架构的使用可以通过改进栅极对沟道的静电控制来帮助减轻短沟道效应。因此发展了鳍式场效应晶体管(FinFET)。为了进一步提高沟道的控制以及降低短沟道效应，也发展了具有垂直全环栅结构的晶体管，其中，相应的晶体管也称为垂直全环栅(VGAA)晶体管。在VGAA晶体管中，栅极电介质和栅电极完全环绕沟道区。这种配置实现沟道的良好控制，并且降低了短沟道效应。
通过接触插塞和金属线连接至VGAA晶体管的源极区和漏极区。形成接触插塞以电连接至VGAA晶体管的顶部源极/漏极区、底部源极/漏极区和栅极。金属线用于互连接触插塞。当需要局部互连件以电互连相邻的VGAA晶体管的顶部源极/漏极区时，局部互连件包括接触插塞和使接触插塞互连的金属线。
发明内容
为了解决现有技术中存在的问题，本发明提供了一种集成电路结构，包括：第一垂直晶体管，包括：第一半导体沟道；第一顶部源极/漏极区，位于所述第一半导体沟道上方；和第一顶部源极/漏极焊盘，覆盖所述第一顶部源极/漏极区；第二垂直晶体管，包括：第二半导体沟道；第二顶部源极/漏极区，位于所述第二半导体沟道上方；和第二顶部源极/漏极焊盘，覆盖所述第二顶部源极/漏极区；以及局部互连件，互连所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘，其中，所述第一顶部源极/漏极焊盘、所述第二顶部源极/漏极焊盘和所述局部互连件是连续区域的部分，在所述第一顶部源极/漏极焊盘、所述第二顶部源极/漏极焊盘和所述局部互连件之间没有可辨识的界面。
在上述集成电路结构中，其中，所述局部互连件、所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘中的每个均包括导电阻挡层和位于所述导电阻挡层上方的顶部金属层。
在上述集成电路结构中，其中，所述局部互连件、所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘中的每个均包括导电阻挡层和位于所述导电阻挡层上方的顶部金属层，其中，所述集成电路结构还包括：金属硅化物层，位于所述局部互连件、所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘中的每个下面并且与所述局部互连件、所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘中的每个接触。
在上述集成电路结构中，其中，所述第一垂直晶体管和所述第二垂直晶体管具有相反的导电类型。
在上述集成电路结构中，其中，所述第一垂直晶体管和所述第二垂直晶体管具有相同的导电类型。
在上述集成电路结构中，其中，所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘比所述局部互连件宽。
在上述集成电路结构中，其中，所述集成电路结构还包括：第一栅极电介质，环绕所述第一半导体沟道；第一栅电极，环绕所述第一栅极电介质；第二栅极电介质，环绕所述第二半导体沟道；以及第二栅电极，环绕所述第二栅极电介质。
根据本发明的另一实施例，提供了一种集成电路结构，包括：第一垂直晶体管，包括：第一半导体沟道；第一顶部源极/漏极区，位于所述第一半导体沟道上方；第一栅极电介质，环绕所述第一半导体沟道；和第一栅电极，环绕所述第一栅极电介质；第二垂直晶体管，包括：第二半导体沟道；第二顶部源极/漏极区，位于所述第二半导体沟道上方；第二栅极电介质，环绕所述第二半导体沟道；和第二栅电极，环绕所述第二栅极电介质；介电区，位于所述第一栅电极和所述第二栅电极之间并且使所述第一栅电极和所述第二栅电极彼此分隔开；以及导电部件，包括：第一部分，具有与所述第一顶部源极/漏极区的顶面接触的第一底面；第二部分，具有与所述第二顶部源极/漏极区的顶面接触的第二底面；和第三部分，具有与所述介电区的顶面接触的第三底面，其中，所述第三部分互连所述第一部分和所述第二部分。
在上述集成电路结构中，其中，所述导电部件包括硅化物层，其中，所述第一底面、所述第二底面和所述第三底面是所述硅化物层的底面。
在上述集成电路结构中，其中，所述导电部件包括硅化物层，其中，所述第一底面、所述第二底面和所述第三底面是所述硅化物层的底面，其中，所述导电部件还包括位于所述硅化物层上方并且电连接至所述硅化物层的导电阻挡层，其中，所述导电阻挡层和所述硅化物层是共端点的。
在上述集成电路结构中，其中，所述导电部件包括硅化物层，其中，所述第一底面、所述第二底面和所述第三底面是所述硅化物层的底面，其中，所述导电部件还包括位于所述硅化物层上方并且电连接至所述硅化物层的顶部金属层，其中，所述顶部金属层和所述硅化物层是共端点的。
在上述集成电路结构中，其中，所述第一垂直晶体管和所述第二垂直晶体管具有相反的导电类型。
在上述集成电路结构中，其中，所述第一垂直晶体管和所述第二垂直晶体管具有相同的导电类型。
在上述集成电路结构中，其中，所述导电部件覆盖整个所述第一半导体沟道和整个所述第二半导体沟道。
根据本发明的又一实施例，提供了一种方法，包括：形成第一垂直晶体管，所述第一垂直晶体管包括：第一半导体沟道；和第一顶部源极/漏极区，位于所述第一半导体沟道上方；形成第二垂直晶体管，所述第二垂直晶体管包括：第二半导体沟道；和第二顶部源极/漏极区，位于所述第二半导体沟道上方；在所述第一垂直晶体管和所述第二垂直晶体管上方以及在所述第一垂直晶体管和所述第二垂直晶体管之间的区域上方形成导电层；以及图案化所述导电层，其中，所述导电层的剩余部分包括：第一部分，具有与所述第一顶部源极/漏极区的顶面接触的第一底面；第二部分，具有与所述第二顶部源极/漏极区的顶面接触的第二底面，和第三部分，互连所述第一部分和所述第二部分。
在上述方法中，其中，所述方法还包括：在所述第一垂直晶体管和所述第二垂直晶体管之间形成使所述第一垂直晶体管和所述第二垂直晶体管彼此分隔开的介电区，其中，所述导电层的所述剩余部分的所述第三部分具有与所述介电区接触的底面。
在上述方法中，其中，形成所述导电层包括：毯式形成导电阻挡层；以及在所述导电阻挡层上方毯式形成顶部金属层，其中，在所述图案化中图案化所述导电阻挡层和所述顶部金属层。
在上述方法中，其中，形成所述导电层包括：毯式形成导电阻挡层；以及在所述导电阻挡层上方毯式形成顶部金属层，其中，在所述图案化中图案化所述导电阻挡层和所述顶部金属层，其中，形成所述导电层还包括：在毯式形成所述导电阻挡层之前，在所述第一垂直晶体管和所述第二垂直晶体管上方形成硅化物层。
在上述方法中，其中，所述第一垂直晶体管和所述第二垂直晶体管具有相反的导电类型。
在上述方法中，其中，所述第一垂直晶体管和所述第二垂直晶体管具有相同的导电类型。
附图说明
当结合附图进行阅读时，从以下详细描述可最佳理解本发明的各方面。应该强调，根据工业中的标准实践，各个部件未按比例绘制并且仅用于说明的目的。实际上，为了清楚的讨论，各个部件的尺寸可以任意地增大或减小。
图1示出了根据一些实施例的相邻的垂直全环栅(VGAA)晶体管以及用于连接相邻的VGAA晶体管的局部互连件的顶视图；
图2A至图7C示出了根据一些实施例的在形成VGAA晶体管的局部互连件中的中间阶段的截面图；
图8至图11示出了根据一些实施例的VGAA晶体管的一些示例性局部互连件；以及
图12示出了根据一些实施例的用于形成VGAA晶体管的部分和局部互连件的工艺流程图。
具体实施方式
以下公开内容提供了许多用于实现本发明的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然，这些仅仅是实例，而不旨在限制本发明。例如，在以下描述中，在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例，并且也可以包括在第一部件和第二部件之间可以形成额外的部件，从而使得第一部件和第二部件可以不直接接触的实施例。此外，本发明可在各个实例中重复参考标号和/或字符。该重复是为了简单和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且，为便于描述，在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等的空间相对术语，以描述如图所示的一个元件或部件与另一个(或另一些)元件或部件的关系。除了图中所示的方位外，空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其他方式定向(旋转90度或在其他方位上)，而本文使用的空间相对描述符可以同样地作相应的解释。
根据各个示例性实施例提供了用于互连垂直全环栅(VGAA)晶体管的顶部源极/漏极区的局部互连件及其形成方法。示出了形成局部互连件的中间阶段。讨论了实施例的变化。贯穿各个视图和说明性实施例，相同的参考标号用于标示相同的元件。
图1示出了多个VGAA晶体管100、200、300和400的顶视图。根据本发明的一些实施例，VGAA晶体管100、300是n型垂直晶体管，而VGAA晶体管200和400是p型垂直晶体管。互连VGAA晶体管100和200以形成一对，并且互连VGAA晶体管300和400以形成一对。在一些示例性实施例中，对100/200和对300/400中的一对或两对用于诸如反相器的电路中，其中，VGAA晶体管100和200的漏极区电连接(短路)，和/或VGAA晶体管300和400的漏极区电连接(短路)。
VGAA晶体管100包括垂直纳米线102，垂直纳米线102可以形成VGAA晶体管100的沟道区以及可能形成源极和/或漏极区的部分。栅极电介质104形成环绕VGAA晶体管100的沟道区的环。栅电极106进一步形成环绕栅极电介质104的环。顶部源极/漏极焊盘108位于顶部源极/漏极区120(图2B)上方并且电连接至顶部源极/漏极区120。使用虚线示出了纳米线102、栅极电介质104和栅电极106以表明它们位于顶部源极/漏极焊盘108下面。
类似地，VGAA晶体管200包括垂直纳米线202、栅极电介质204、栅电极206和顶部源极/漏极焊盘208。栅极电介质204形成环绕VGAA晶体管200的沟道区的环。栅电极206进一步形成环绕栅极电介质204的环。顶部源极/漏极焊盘208位于顶部源极/漏极区220(图2B)上方并且电连接至顶部源极/漏极区220。VGAA晶体管300包括垂直纳米线303、栅极电介质304、栅电极306和顶部源极/漏极焊盘308。栅极电介质304形成环绕VGAA晶体管300的沟道区的环。栅电极306进一步形成环绕栅极电介质304的环。顶部源极/漏极焊盘308位于相应的顶部源极/漏极区(未示出)上方并且电连接至相应的顶部源极/漏极区。VGAA晶体管400包括垂直纳米线402、栅极电介质404、栅电极406和顶部源极/漏极焊盘408。栅极电介质404形成环绕VGAA晶体管400的沟道区的环。栅电极406进一步形成环绕栅极电介质404的环。顶部源极/漏极焊盘408位于相应的顶部源极/漏极区(未示出)上方并且电连接至相应的顶部源极/漏极区。
顶部源极/漏极焊盘108和顶部源极/漏极焊盘208通过局部互连件210互连。根据本发明的一些实施例，顶部源极/漏极焊盘108和208以及局部互连件210形成连续的导电区，在它们之间没有中断和可辨识的界面。此外，顶部源极/漏极焊盘108和208以及局部互连件210具有相同的结构并且由相同的导电材料形成。例如，顶部源极/漏极焊盘108和208以及局部互连件210可以由单个导电层或多个导电子层形成。当包括多个导电子层时，位于顶部源极/漏极焊盘108和208以及局部互连件210中的相应子层由相同的材料形成。
类似地，顶部源极/漏极焊盘308和顶部源极/漏极焊盘408通过局部互连件410互连，其中，顶部源极/漏极焊盘308和408以及局部互连件410形成连续的导电区，在它们之间没有中断和可辨识的界面。
图2A至图7C示出了根据一些实施例的在形成图1中示出的结构中的中间阶段的截面图。也在图12中示出的工艺流程中示意性地示出了图2A至图7C中示出的步骤。在随后的讨论中，参照图12中的工艺步骤讨论图2A至图7C中示出的工艺步骤。
图2A至图7C中的每个图号包括数字和之后的字母“A”、“B”或“C”。包括字母“A”的图示出了从包含图1中的线A-A的平面截取的截面图。包括字母“B”的图示出了从包含图1中的线B-B的平面截取的截面图。包括字母“C”的图示出了从包含图1中的线C-C的平面截取的截面图。图2A至图7C示出了VGAA晶体管100和200的截面图。此外，图1也示出了线B’-B’，其平面穿过VGAA晶体管300和400。从包含线B’-B’的平面截取的截面图可以与包含线B-B的平面中示出的截面图基本相同。因此，从包含线B’-B’的平面截取的截面图未示出，并且可以从字符包括字母“B”的图找到。
图2A示出了初始结构的形成中的截面图，其中，从包含图1中的线A-A的平面获得该截面图。通过注入半导体衬底20形成底部源极/漏极区312和112(以及212(图2B))。根据一些实施例，半导体衬底20是硅衬底、硅锗衬底或由其他半导体材料形成的衬底。可以通过以诸如磷或砷的n型杂质注入半导体衬底20的部分来形成底部源极/漏极区312和112。在衬底20中形成诸如浅沟槽隔离(STI)区22的隔离区以将相邻的有源区分隔开。如图1所示，根据本发明的一些实施例，STI区22环绕晶体管100、200、300和400的底部源极/漏极区，其中，STI区22的部分可以直接延伸至局部互连件210和410下面以形成全环。
图2B示出了VGAA晶体管100和200的形成，其中，从包含图1中的线B-B的平面获得该截面图。相应的工艺步骤示出为图12中示出的工艺流程中的步骤702。该截面图示出了每个VGAA晶体管100和200的一半。VGAA晶体管100包括底部源极/漏极区112，取决于相应的VGAA晶体管100的功能，底部源极/漏极区112可以是源极区或漏极区。在底部源极/漏极区112的顶面处形成硅化物区114，硅化物区114可以包括硅化镍、硅化钴等。在底部源极/漏极区112上方形成底部源极/漏极延伸区116。沟道区118位于底部源极/漏极延伸区116上方。顶部源极/漏极区120位于沟道区118上方，并且也是n型区。顶部源极/漏极区120可以包括源极/漏极延伸区，源极/漏极延伸区是轻掺杂和/或重掺杂的源极/漏极区，其中，源极/漏极延伸区的掺杂浓度低于重掺杂的顶部源极/漏极区的掺杂浓度。根据本发明的一些实施例，底部源极/漏极延伸区116、沟道区118和顶部源极/漏极区120组合形成垂直纳米线102。
VGAA晶体管200包括底部源极/漏极区212，取决于相应的VGAA晶体管200的功能，底部源极/漏极区212可以是源极区或漏极区。在底部源极/漏极区212的顶面处形成硅化物区214，硅化物区214可以包括硅化镍、硅化钴等。在底部源极/漏极区212上方形成底部源极/漏极延伸区216。沟道区218位于底部源极/漏极延伸区216上方。顶部源极/漏极区220形成在沟道区218上方。顶部源极/漏极区220可以包括源极/漏极延伸区，源极/漏极延伸区是轻掺杂和/或重掺杂的源极/漏极区，其中，源极/漏极延伸区的掺杂浓度低于重掺杂的顶部源极/漏极区的掺杂浓度。根据本发明的一些实施例，底部源极/漏极延伸区216、沟道区218和顶部源极/漏极区220组合形成垂直纳米线202。底部源极/漏极区212和顶部源极/漏极区220是p型区。
纳米线102和202由半导体材料形成，半导体材料可以包括SiGe或诸如InAs、GaSb、GaN、InP、GaAs、InSb或InGaSb的III-V族化合物半导体。可以通过外延形成包括相应的底部源极/漏极延伸区、沟道区和顶部源极/漏极区的纳米线102和202。
栅极电介质104和204形成分别环绕相应的沟道区118和218的环。根据一些实施例，每个栅极电介质104和204包括单个介电层。在可选实施例中，每个栅极电介质104和204包括多于一个的层。栅极电介质104和204可以由诸如氧化铪、氧化镧、氧化铝、氧化锆等的高k介电材料形成。栅电极106和206环绕相应的栅极电介质104和204。栅电极106和206可以是金属栅电极，其中，根据期望的功函数选择栅电极106和206的材料。例如，栅电极106可以具有介于约4.1eV和约4.5eV的范围内的低功函数，并且栅电极206可以具有介于约4.5eV和约4.9eV的范围内的高功函数。在截面图中，栅极电介质104和204以及金属栅电极106和206的一些层可以具有L形。
形成介电区24、26和28以使包括区域106、206、112、212、114、214、118和218的多个导电部件彼此分隔开。介电区24、26和28可以由氧化硅、氮化硅、氮氧化硅、碳氧化硅等形成。
如图2A中所示，栅极电介质104和金属栅电极106的一些层可以具有延伸至图2A中示出的截面图的水平部分，其中，在这些区域中，栅极电介质104分别位于相应的底部源极/漏极区112和212上方。
图2C示出了初始结构的截面图，其中，从包含图1中的线C-C的平面获得该截面图。图2C中示出的结构类似于该步骤中的图2B中示出的结构。
接下来，参照图3A，形成顶部源极/漏极硅化物层32。相应的工艺步骤示出为图12中示出的工艺流程中的步骤704。根据本发明的一些实施例，顶部源极/漏极硅化物层32包括可以通过沉积步骤形成的硅化钛、硅化钴等。可选地，通过沉积硅层以及随后硅化硅层来形成顶部源极/漏极硅化物层32。根据本发明的一些实施例，顶部源极/漏极硅化物层32从VGAA晶体管100正上方连续延伸至VGAA晶体管200正上方。根据可选实施例，顶部源极/漏极硅化物层32形成为离散的区域，其中每个顶部源极/漏极区120和220具有位于其上的一个离散的硅化物层，并且位于不同的VGAA晶体管100和200上方的硅化物层彼此物理分隔开。
图3A也示出了导电阻挡层34的形成。相应的工艺步骤示出为图12中示出的工艺流程中的步骤706。根据一些实施例，导电阻挡层34包括钛层和位于钛层上方的氮化钛层。根据本发明的可选实施例，导电阻挡层34包括钽层和位于钽层上方的氮化钽层。可以通过沉积诸如钛层或钽层的金属层以及然后氮化金属层的顶部、留下未氮化的底部来形成导电阻挡层34。用于形成导电阻挡层34的沉积可以包括化学汽相沉积方法中的一种。也如图3B和图3C所示，导电阻挡层34直接延伸至VGAA晶体管100和200上方。
图4A、图4B和图4C示出了顶部金属层36的形成。相应的工艺步骤示出为图12中示出的工艺流程中的步骤708。根据本发明的一些实施例，顶部金属层36由钨、镍、钴、铝、铜、它们的合金和/或它们的复合层形成。
图4A、图4B和图4C进一步示出了硬掩模层38的形成。相应的工艺步骤示出为图12中示出的工艺流程中的步骤710。硬掩模层38可以由氮化硅或适合于用作蚀刻掩模的其他材料形成。如图4C所示，顶部金属层36和硬掩模层38直接延伸在VGAA晶体管100和200上方。如图4A和图4B所示，顶部金属层36和硬掩模层38也直接延伸在使VGAA晶体管100和200彼此分隔开的STI区22和介电区26(图4C)的部分上方。
接下来，如图5A、图5B和图5C以及图6A、图6B和图6C所示，实施图案化步骤以图案化导电部件32、34和36。参照图5A、图5B和图5C，在曝光和显影步骤中形成(施加)并且图案化光刻胶40。接下来，图案化的光刻胶40用于图案化下面的硬掩模层38。相应的工艺步骤示出为图12中示出的工艺流程中的步骤712。图案化的硬掩模层38进一步用于图案化下面的包括顶部金属层36、导电阻挡层34和顶部源极/漏极硅化物层32的导电层。相应的工艺步骤示出为图12中示出的工艺流程中的步骤714。图6A、图6B和图6C中示出了产生的结构。根据一些实施例，在暴露下面的诸如介电区26的介电层之后停止图案化。
图6C示出了在图案化步骤之后的结构的截面图，其中，从包含图1中的线C-C的平面获得该截面图。在图案化步骤之后，去除硬掩模层38。也将去除光刻胶40(如果在图案化步骤之后剩余)。如图6C所示，在图案化之后，直接位于顶部源极/漏极区120上方的顶部金属层36和导电阻挡层34的一些部分保留，并且形成顶部源极/漏极焊盘108。顶部源极/漏极焊盘108通过顶部源极/漏极硅化物区132电连接至顶部源极/漏极区120，顶部源极/漏极硅化物区132是顶部硅化物层32的剩余部分。直接位于顶部源极/漏极区220上方的顶部金属层36和导电阻挡层34的剩余部分也形成顶部源极/漏极焊盘208。顶部源极/漏极焊盘208通过顶部源极/漏极硅化物区232电连接至顶部源极/漏极区220，顶部源极/漏极硅化物区232也是顶部硅化物层32的剩余部分。
参照图6B，图6B是从包含图1中的线B-B的相同平面获得的，在图案化之后留下顶部金属层36和导电阻挡层34的部分以形成局部互连件210，局部互连件210将顶部源极/漏极焊盘108电连接至顶部源极/漏极焊盘208。如图1所示，局部互连件210可以比顶部源极/漏极焊盘108和208更窄。由于在与形成顶部源极/漏极焊盘108和208的相同的工艺步骤中形成局部互连件210，所以局部互连件210和顶部源极/漏极焊盘108和208连续地连接以形成连续的导电区，其中，在它们之间未形成可辨识的界面。而且，局部互连件210和顶部源极/漏极焊盘108和208由相同的材料形成，具有相同数量的子层并且带有由相同的同质的导电材料形成的相应的子层。
图6A示出了图案化步骤之后的结构的截面图，其中，从包含图1中的线A-A的平面获得该截面图。图6A示出了彼此分隔开的局部互连件210和410(也参照图1)。
图7A、图7B和图7C示出了介电层42和导电部件44(图7B)的形成。相应的工艺步骤示出为图12中示出的工艺流程中的步骤716。根据本发明的一些实施例，介电层42是层间电介质(ILD)，ILD可以包括使用例如可流动化学汽相沉积(FCVD)形成的可流动氧化物。ILD 42也可以包括磷硅酸盐玻璃(PSG)、硼硅酸盐玻璃(BSG)、硼掺杂的磷硅酸盐玻璃(BPSG)、正硅酸乙酯(TEOS)氧化物等。可以实施诸如化学机械抛光(CMP)步骤的平坦化以使ILD 42的顶面平齐。
在介电层42中形成导电部件44(图7B)。根据本发明的一些实施例，导电部件44是底部金属化层中的金属线，金属线可以包括铜，并且可以使用镶嵌工艺形成。在可选实施例中，导电部件44是接触插塞或导电通孔，其也可以包括钨、钴、铝、镍、铜等。导电部件44直接形成在顶部源极/漏极焊盘108和208中的一个上方并且因此通过局部互连件210(图7B)电连接至顶部源极/漏极焊盘108和208。
图8至图11示出了根据各个示例性实施例的使相邻的VGAA晶体管的顶部源极/漏极焊盘互连的局部互连件。参照图8，通过局部互连件210A互连n型VGAA晶体管100的顶部源极/漏极焊盘108和n型VGAA晶体管300的顶部源极/漏极焊盘308，局部互连件210A与顶部源极/漏极焊盘108、208、308和408同时形成。根据可选实施例(未示出)，也可以形成局部互连件210A以互连诸如晶体管200和400的两个p型VGAA晶体管的顶部源极/漏极焊盘。局部互连件210A与顶部源极/漏极焊盘108、208、308和408同时形成。
在图9中，通过局部互连件210A互连n型VGAA晶体管100的顶部源极/漏极焊盘108和n型VGAA晶体管300的顶部源极/漏极焊盘308。进一步通过局部互连件210B互连n型VGAA晶体管300的顶部源极/漏极焊盘308和p型VGAA晶体管400的顶部源极/漏极焊盘408。局部互连件210A和210B与顶部源极/漏极焊盘108、208、308和408同时形成。
在图10中，通过局部互连件210A互连n型VGAA晶体管100的顶部源极/漏极焊盘108和n型VGAA晶体管300的顶部源极/漏极焊盘308。进一步通过局部互连件210C互连n型VGAA晶体管100的顶部源极/漏极焊盘108和p型VGAA晶体管200的顶部源极/漏极焊盘208。此外，通过局部互连件210D互连p型VGAA晶体管200的顶部源极/漏极焊盘208和p型VGAA晶体管400的顶部源极/漏极焊盘408。局部互连件210A、210C和210D与顶部源极/漏极焊盘108、208、308和408同时形成。
图11示出了形成为彼此接近的n型VGAA晶体管100、300和500以及p型VGAA晶体管200、400和600的顶视图。通过局部互连件210A互连n型VGAA晶体管100的顶部源极/漏极焊盘108和n型VGAA晶体管300的顶部源极/漏极焊盘308。进一步通过局部互连件210C互连n型VGAA晶体管100的顶部源极/漏极焊盘108和p型VGAA晶体管200的顶部源极/漏极焊盘208。此外，通过局部互连件210E互连p型VGAA晶体管200的顶部源极/漏极焊盘208和p型VGAA晶体管600的顶部源极/漏极焊盘608。局部互连件210A、210C和210E与顶部源极/漏极焊盘108、208、308、408、508和608同时形成。
本发明的实施例具有一些有利特征。在传统的结构中，通过形成接触插塞和金属线制成相邻的VGAA晶体管的顶部源极/漏极区(或焊盘)的互连。因此，由于接触插塞和金属线之间的界面处的接触电阻，局部互连件的电阻高。此外，涉及更多的工艺步骤和更高的制造成本。在本发明的实施例中，顶部源极/漏极焊盘和局部互连件形成为连续的区域，并且因此消除了传统的局部互连件中的界面处的接触电阻。此外，由于减少的工艺步骤而简化了工艺。
根据本发明的一些实施例，一种集成电路结构包括第一垂直晶体管和第二垂直晶体管。第一垂直晶体管包括第一半导体沟道、位于第一半导体沟道上方的第一顶部源极/漏极区以及覆盖第一顶部源极/漏极区的第一顶部源极/漏极焊盘。第二垂直晶体管包括第二半导体沟道、位于第二半导体沟道上方的第二顶部源极/漏极区以及覆盖第二顶部源极/漏极区的第二顶部源极/漏极焊盘。局部互连件互连第一顶部源极/漏极焊盘和第二顶部源极/漏极焊盘。第一顶部源极/漏极焊盘、第二顶部源极/漏极焊盘和局部互连件是连续区域的部分，在第一顶部源极/漏极焊盘、第二顶部源极/漏极焊盘和局部互连件之间没有可辨识的界面。
根据本发明的可选实施例，一种集成电路结构包括第一垂直晶体管和第二垂直晶体管。第一垂直晶体管包括第一半导体沟道、位于第一半导体沟道上方的第一顶部源极/漏极区、环绕第一半导体沟道的第一栅极电介质以及环绕第一栅极电介质的第一栅电极。第二垂直晶体管包括第二半导体沟道、位于第二半导体沟道上方的第二顶部源极/漏极区、环绕第二半导体沟道的第二栅极电介质以及环绕第二栅极电介质的第二栅电极。介电区位于第一栅电极和第二栅电极之间并且使第一栅电极和第二栅电极彼此分隔开。该集成电路结构还包括导电部件，导电部件包括具有与第一顶部源极/漏极区的顶面接触的第一底面的第一部分、具有与第二顶部源极/漏极区的顶面接触的第二底面的第二部分、以及具有与介电区的顶面接触的第三底面的第三部分，其中，第三部分互连第一部分和第二部分。
根据本发明的又可选实施例，一种方法包括形成第一垂直晶体管以及形成第二垂直晶体管，第一垂直晶体管包括第一半导体沟道和位于第一半导体沟道上方的第一顶部源极/漏极区，第二垂直晶体管包括第二半导体沟道和位于第二半导体沟道上方的第二顶部源极/漏极区。在第一垂直晶体管和第二垂直晶体管上方以及在第一垂直晶体管和第二垂直晶体管之间的区域上方形成导电层。图案化导电层，其中，导电层的剩余部分包括具有与第一顶部源极/漏极区的顶面接触的第一底面的第一部分、具有与第二顶部源极/漏极区的顶面接触的第二底面的第二部分、以及互连第一部分和第二部分的第三部分。
上面概述了若干实施例的特征，使得本领域技术人员可以更好地理解本发明的方面。本领域技术人员应该理解，他们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其他工艺和结构。本领域技术人员也应该意识到，这种等同构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，本文中他们可以做出多种变化、替换以及改变。

Claims (10)

1.一种集成电路结构，包括：
第一垂直晶体管，包括：
第一半导体沟道；
第一顶部源极/漏极区，位于所述第一半导体沟道上方；和
第一顶部源极/漏极焊盘，覆盖所述第一顶部源极/漏极区；
第二垂直晶体管，包括：
第二半导体沟道；
第二顶部源极/漏极区，位于所述第二半导体沟道上方；和
第二顶部源极/漏极焊盘，覆盖所述第二顶部源极/漏极区；以及
局部互连件，互连所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘，其中，所述第一顶部源极/漏极焊盘、所述第二顶部源极/漏极焊盘和所述局部互连件是连续区域的部分，在所述第一顶部源极/漏极焊盘、所述第二顶部源极/漏极焊盘和所述局部互连件之间没有可辨识的界面。
2.根据权利要求1所述的集成电路结构，其中，所述局部互连件、所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘中的每个均包括导电阻挡层和位于所述导电阻挡层上方的顶部金属层。
3.根据权利要求2所述的集成电路结构，还包括：
金属硅化物层，位于所述局部互连件、所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘中的每个下面并且与所述局部互连件、所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘中的每个接触。
4.根据权利要求1所述的集成电路结构，其中，所述第一垂直晶体管和所述第二垂直晶体管具有相反的导电类型。
5.根据权利要求1所述的集成电路结构，其中，所述第一垂直晶体管和所述第二垂直晶体管具有相同的导电类型。
6.根据权利要求1所述的集成电路结构，其中，所述第一顶部源极/漏极焊盘和所述第二顶部源极/漏极焊盘比所述局部互连件宽。
7.根据权利要求1所述的集成电路结构，还包括：
第一栅极电介质，环绕所述第一半导体沟道；
第一栅电极，环绕所述第一栅极电介质；
第二栅极电介质，环绕所述第二半导体沟道；以及
第二栅电极，环绕所述第二栅极电介质。
8.一种集成电路结构，包括：
第一垂直晶体管，包括：
第一半导体沟道；
第一顶部源极/漏极区，位于所述第一半导体沟道上方；
第一栅极电介质，环绕所述第一半导体沟道；和
第一栅电极，环绕所述第一栅极电介质；
第二垂直晶体管，包括：
第二半导体沟道；
第二顶部源极/漏极区，位于所述第二半导体沟道上方；
第二栅极电介质，环绕所述第二半导体沟道；和
第二栅电极，环绕所述第二栅极电介质；
介电区，位于所述第一栅电极和所述第二栅电极之间并且使所述第一栅电极和所述第二栅电极彼此分隔开；以及
导电部件，包括：
第一部分，具有与所述第一顶部源极/漏极区的顶面接触的第一底面；
第二部分，具有与所述第二顶部源极/漏极区的顶面接触的第二底面；和
第三部分，具有与所述介电区的顶面接触的第三底面，其中，所述第三部分互连所述第一部分和所述第二部分。
9.根据权利要求8所述的集成电路结构，其中，所述导电部件包括硅化物层，其中，所述第一底面、所述第二底面和所述第三底面是所述硅化物层的底面。
10.一种方法，包括：
形成第一垂直晶体管，所述第一垂直晶体管包括：
第一半导体沟道；和
第一顶部源极/漏极区，位于所述第一半导体沟道上方；
形成第二垂直晶体管，所述第二垂直晶体管包括：
第二半导体沟道；和
第二顶部源极/漏极区，位于所述第二半导体沟道上方；
在所述第一垂直晶体管和所述第二垂直晶体管上方以及在所述第一垂直晶体管和所述第二垂直晶体管之间的区域上方形成导电层；以及
图案化所述导电层，其中，所述导电层的剩余部分包括：
第一部分，具有与所述第一顶部源极/漏极区的顶面接触的第一底面；
第二部分，具有与所述第二顶部源极/漏极区的顶面接触的第二底面，和
第三部分，互连所述第一部分和所述第二部分。
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US9349859B1 (en) 2016-05-24
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US20170084753A1 (en) 2017-03-23
US20160247720A1 (en) 2016-08-25
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