CN111048579A - 一种新型数字门集成电路的结构 - Google Patents
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Abstract
一种新型数字门集成电路的结构，涉及半导体器件及集成电路技术领域。本发明的一种新型数字门集成电路的结构为纵向N型或P型TMOS，在纵向上分别设置有源极区域、半导体沟道区域以及漏极区域；在水平方向上四周环绕着栅极区域，栅极与沟道半导体区之间设置有栅介质层，底部漏极区域可通过引线孔从外侧引出。可用此基本单元构成与门、与非门、或非门。本发明所要解决的关键技术问题是：提供一种新型数字门集成电路的结构，该结构的栅极环绕器件体区，当栅极加上合适的偏置时，会形成四面沟道，加大了栅控能力，提高了导通时的电流密度。且新结构的沟道区不由光刻工艺完成，沟道长度不再受到光刻精度的限制。同时，通过采用窄禁带材料做源区并在漏区前端加入N‑漂移区结构，实现器件的小面积、大电流、低导通电阻，从而提高集成电路的集成度。
Description
技术领域
本发明涉及微电子技术和半导体技术。
背景技术
几十年来，微电子的研究者设计者一直在努力跟上摩尔定律的脚步，而近几年，我们越来越靠近摩尔定律的天花板。数字电路架构本身的优化并不能长久的解决这个问题，改变器件本身才是实现突破的长久之计[1]。
硅和锗就是人们最早发现的半导体材料，被公认为是第一代半导体材料，两者性质相似，但锗的禁带宽度小于硅的禁带宽度。SiGe/Si异质结材料具有很多独特的性质。外延SiGe合金使得在不改变现有工艺线宽的基础上大大改善Si材料的性能，高性能的应变SiGe外延层能够将能带工程的概念引入到传统的Si基材料中去，实现一些硅材料的突破[2]。在发明人李平教授、李肇基教授已成功申请的专利“窄禁带源漏区金属氧化物半导体场效应晶体管及集成电路”中就提出了，采用不同于器件衬底材料的窄禁带异质材料作为器件的源区或者源、漏区，使器件中的寄生BJT发射结成为异质结，并且有β<<1的特点，可以从器件上彻底消除寄生 BJT对BVDS的影响[3]。
FinFET，中文名叫鳍式场效应晶体管，它是一次MOS管器件结构的革新，它是由加州大学伯克利分校的胡正明教授提出的[4]，结构如图15所示。FinFET的最大特点是，沟道区域是一个被栅极包裹的鳍状半导体，沿源漏方向的鳍的长度，为沟道长度。从而形成了一个三面环绕的栅结构，大大提高了栅极对沟道的控制力，有效地抑制了短沟道效应。FinFET沟道一般是轻掺杂甚至不掺杂的，避免了离散的掺杂原子的散射作用，同重掺杂的平面器件相比，载流子迁移率将会大大提高。FINFET器件可以使用比传统更厚的栅氧化物，使得FinFET器件的栅漏电流也会减小。FINFET在20nm技术节点后取代了传统的平面CMOS开始被大芯片生产商选择，现在广泛采用的是7nm工艺，台积电预计明年7月开始大批量生产5nm工艺芯片[5]。但是，FINFET的工艺依旧依赖多次曝光等方法实现超小尺寸工艺，即在小尺寸下依旧需要较为复杂的工艺。
Reference
[1]A.K.Kuna,K.Kandpal and K.B.R.Teja,"An investigation of FinFETbased digital circuits for low power applications,"2017InternationalConference on Circuit,Power and Computing Technologies(ICCPCT),Kollam, 2017,pp.1-6.doi:10.1109/ICCPCT.2017.8074280
[2]高速NPN锗硅异质结双极晶体管的设计与制作[J].钱文生,刘冬华,陈帆,陈雄斌,石晶,段文婷,胡君,黄景丰.固体电子学研究与进展.2012(05)
[3]李平；李肇基.窄禁带源漏去金属氧化物半导体场效应晶体管级集成电路：中国， CN96117551.6[P].1997.11.19.
[4]Yu E,Chang L,Ahmed S,et al.FinFET scaling to 10nm gate length[J].Int Electron Devices Meeting,2002:251--254.
[5]"7nm Technology".TSMC.Retrieved 30June 2019.
发明内容
本发明所要解决的技术问题是：提供一种新型数字门集成电路的结构，即非门、或非门、与非门，实现器件的小面积、大电流、低导通电阻，从而提高集成电路的集成度。
本发明解决所述技术问题采用的技术方案是：一种新型数字门集成电路的结构，由一种新型MOS管结构构成，结构为纵向结构，在纵向上分别设置有源极区域、半导体沟道区域以及漏极区域；在水平方向上四周环绕着栅极区域，栅极与沟道半导体区之间设置有栅介质层，底部漏极区域可通过引线孔从外侧引出，由此四面环栅的NMOS管和PMOS管级联形成非门、或非门、与非门，其特征在于，所述源极区域可以用单晶Ge、多晶Ge、赝晶Ge、SiGe、碲镉汞、InP等窄禁带半导体材料。所述MOS管在外圈的四面均有氧化层、多晶硅层，这样可以在提供四面的沟道。所述栅介质层为SiO2、HfO2等常规栅介质材料。所述源极和漏极为金属电极，所述栅电极为N+多晶硅或者金属电极或者以上两者的结合。所述PMOS管P- 轻掺杂层、NMOS管N-轻掺杂层，作为轻掺杂漏极。
如图1、2所示，第一，新结构采用了窄禁带半导体材料锗作为源区，使器件中的寄生 BJT发射结成为异质结，并且有β<<1的特点，可以从器件上彻底消除寄生BJT对BVDS的影响，所以不再需要将衬底与源区短接到地(对于P型MOSFET为VDD)的结构。
第二，该结构的栅极环绕器件体区，所以当栅极加上合适的偏置时，会形成四面沟道，这样不但可以像FINFET一样通过多面栅结构而加大栅控能力，甚至优于FINFET的三面沟道，加大了栅控能力，提高了导通时的电流密度，减小了导通电阻。
第三，新结构的沟道区不由光刻工艺完成，所以沟道长度不再受到光刻精度的限制。新结构中形成沟道的体区由外延工艺完成，外延层厚度即为沟道长度，所以省去了光刻所需的大量花费，以及为了达到所需精度而进行的如多次曝光等复杂工艺流程。现阶段，分子束外延工艺技术已能制备薄到几十个原子层的单晶薄膜，可以实现极短沟道长度。
第四，新结构采用了功率MOS结构，即在漏区的前端加入了N-漂移区结构，所以在耐压方面有着极大的提升，并且也能够有效抑制短沟道效应。如今，在极短沟道器件方面，因为FINFET能够有效抑制短沟道效应，所以不管是研究还是市场都以FINFET为主，但是，其短沟道效应的抑制原理是鳍形结构栅的控制能力强，所以FINFET依旧遵循着摩尔定律，在电场强度和电流密度保持不变的前提下，电压与尺寸需等比例缩小，即器件的工作电压受到尺寸的限制。但是，新结构主要由N-漂移区耐压，器件的击穿电压不再与沟道长度有关，即突破了摩尔定律的限制，同时N-区天然地形成了LDD结构，能够有效的抑制短沟道效应。
如图3所示，非门中，M1和M2的栅极可以共用。如图7所示，或非门中，M1和M4， M2和M3的栅极可以两两共用。如图11所示，与非门中，M1和M4，M2和M3的栅极可以两两共用。因此，不需要像FINFET，用金属互联线再连接栅极，节省了工艺成本和面积。
如图7所示，或非门中，M3和M4的漏极可以共用衬底。如图11所示，与非门中，M3 和M4的漏极可以共用衬底。因此，不需要金属互联线连接，节省了工艺成本和面积。
与现有的技术相比，本发明的亮点为：
1.新结构使用窄禁带的锗作为源区，消除了MOS型器件中固有的寄生BJT的影响，节省了大量用于衬底接触而开孔的面积。
2.使用锗作为源区时采用了外延工艺，由于锗和硅本身存在应力，所以可以不用特别制备单晶或者赝晶，而直接使用多晶以优化工艺流程。
3.可以使用除了锗以外的其他窄禁带的材料作为源区，如GeSi、HgTe、InP等等，不同材料会在器件性能上造成一定的差异，可以按需求选择材料，增加了器件设计的灵活度和研究性。
4.新结构在导通时形成四面沟道，可以有效的增加栅极对沟道的控制作用。
5.新结构的沟道长度不再依赖光刻工艺，由外延工艺完成。可以在实现极短沟道长度的同时，简化工艺，降低成本，大大提高集成度。
6.新结构采用了N-漂移区结构，使得电压可以不再和尺寸等比例减小。同时，天然形成的LDD结构也能够在小尺寸小有效的抑制短沟道效应。
7.新的非门、与非门、或非门中的MOS管的栅极可以两两共用，与非门、或非门中也有衬底的共用，这可以减少了金属线的使用，节约工艺成本和面积。
附图说明
图1为新型的PMOS管的基本结构；
图2为新型的NMOS管的基本结构；
图3为新器件结构构成的非门的剖面图；
图4为数字电路中非门电路图；
图5为新器件结构构成的非门的外部整体结构图；
图6为新器件结构构成的非门的俯视图；
图7为新器件结构构成的或非门的剖面图；
图8为数字电路中或非门电路图；
图9为新器件结构构成的或非门的外部整体结构图；
图10为新器件结构构成的或非门的俯视图；
图11为新器件结构构成的与非门的剖面图；
图12为数字电路中与非门电路图；
图13为新器件结构构成的与非门的外部整体结构图；
图14为新器件结构构成的与非门的俯视图；
图15为FINFET的基本结构；
图16为本发明非门工艺实现流程的示意图。
各图标号，101是SiGe(锗硅)，102是介质层SiO2(二氧化硅等常规介质材料)，103是Si(硅)，104是金属电极W(钨)，105是polycrystalline silicon(多晶硅)，106是金属引线W(钨)。
具体实施方式
一种新型数字门集成电路的结构，由一种新型MOS管结构构成，结构为纵向结构，在纵向上分别设置有源极区域、半导体沟道区域以及漏极区域；在水平方向上四周环绕着栅极区域，栅极与沟道半导体区之间设置有栅介质层，底部漏极区域可通过引线孔从外侧引出，由此四面环栅的NMOS管和PMOS管级联形成非门、或非门、与非门，其特征在于，所述源极区域可以用单晶Ge、多晶Ge、赝晶Ge、SiGe、碲镉汞、InP等窄禁带半导体材料。所述MOS管在外圈的四面均有氧化层、多晶硅层，这样可以在提供四面的沟道。所述栅介质层为 SiO2、HfO2等常规栅介质材料。所述源极和漏极为金属电极，所述栅电极为N+多晶硅或者金属电极或者以上两者的结合。所述PMOS管P-轻掺杂层、NMOS管N-轻掺杂层，作为轻掺杂漏极。
参见图16
实施例1：本发明非门工艺实现流程：
(a)硅晶圆准备；
(b)生长一层牺牲材料(如氮化硅等)；
(c)外延生长PMOS晶体管漏极、沟道、源极；
(d)剥离，再次生长牺牲材料；
(e)外延生长NMOS晶体管漏极、沟道、源极；
(f)剥离后涂胶并光刻；
(g)用光刻胶做掩膜，向下腐蚀外延生长的掺杂SiGe层和掺杂Si层；
(h)各项异性生长SiO2，再生长一层多晶硅做栅电极，洗掉光刻胶；
(i)再次涂胶，光刻；
(j)生长金属，制作金属引线孔。
Claims (6)
1.一种新型数字门集成电路的结构，由一种新型MOS管结构构成，结构为纵向结构，在纵向上分别设置有源极区域、半导体沟道区域以及漏极区域；在水平方向上四周环绕着栅极区域，栅极与沟道半导体区之间设置有栅介质层，底部漏极区域可通过引线孔从外侧引出，由此四面环栅的NMOS管和PMOS管级联形成非门、或非门、与非门，其特征在于，所述源极区域可以用单晶Ge、多晶Ge、赝晶Ge、SiGe、碲镉汞、InP等窄禁带半导体材料。
2.如权利要求1所述一种新型数字门集成电路的结构，其特征在于，所述MOS管在外圈的四面均有氧化层、多晶硅层，这样可以在提供四面的沟道。
3.如权利要求1所述一种新型数字门集成电路的结构，其特征在于，所述栅介质层为SiO2、HfO2等常规栅介质材料。
4.如权利要求1所述一种新型数字门集成电路的结构，其特征在于，所述源极和漏极为金属电极，所述栅电极为N+多晶硅或者金属电极或者以上两者的结合。
5.如权利要求1所述一种新型数字门集成电路的结构，其特征在于，所述沟道半导体区包括两个第一导电类型区和一个第二导电类型区，一个第一导电类型区设置于源极和第二导电类型区之间，另一个第一导电类型区设置于漏极和第二导电类型区之间，且在靠近第二导电类型的一侧设有轻掺杂的第一导电类型区作为漂移区；第一导电类型区的材质为P型半导体，第二导电类型区的材质为N型半导体；或者，第一导电类型区的材质为N型半导体，第二导电类型区的材质为P型半导体。
6.如权利要求1所述一种新型数字门集成电路的结构，其特征在于，所述PMOS管P-轻掺杂层、NMOS管N-轻掺杂层，作为轻掺杂漏极。
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| CN112366204A (zh) * | 2020-11-10 | 2021-02-12 | 电子科技大学 | 一种高集成度纳米墙结构sram及实现方法 |
| CN113013234A (zh) * | 2021-03-08 | 2021-06-22 | 电子科技大学 | 一种源区自对准垂直沟道mos集成电路单元及其实现方法 |
| CN114823861A (zh) * | 2022-04-12 | 2022-07-29 | 电子科技大学 | 一种漏区自对准垂直沟道mos集成电路单元结构及其实现方法 |
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