TWI408808B - 同軸電晶體結構 - Google Patents

同軸電晶體結構 Download PDF

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TWI408808B
TWI408808B TW096139774A TW96139774A TWI408808B TW I408808 B TWI408808 B TW I408808B TW 096139774 A TW096139774 A TW 096139774A TW 96139774 A TW96139774 A TW 96139774A TW I408808 B TWI408808 B TW I408808B
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coaxial
conductor
transistor
source
substrate
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TW200919721A (en
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Chun Chu Yang
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Chun Chu Yang
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Priority to JP2008271746A priority patent/JP2009105407A/ja
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Priority to US13/214,784 priority patent/US8395223B2/en
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Description

同軸電晶體結構
本發明係有關於一種同軸電晶體(Coaxial Transistor)且更具體而言，係使用於提高積體電路集積度(Integration)的同軸結構金屬－氧化層－半導體場效電晶體及其完全對稱之互補型金屬－氧化層－半導體場效電晶體技術。
電晶體“Transistor”源於Transfer－Resistor，原為“調動電阻者；移動或轉移電阻者”之意，意譯為“調阻體”可望字知義。電晶體在習知的電子技術領域己明確表現其優越的“調整內建電阻(Build in Resistor)大小，使通過電流可大可小”之雙極性接面電晶體(Bipolar Junction Transistor，簡稱BJT)功能；或在習知的積體數位邏輯電子技術領域的“調整內建電阻，極大化使電流阻斷成為斷路(off)或極小化使電流暢通成為接通(on)”之單極性電晶體(Unipolar Transistor)功能，例如接面場效電晶體(Junction Field－Effect Transistor,簡稱JFET)、金屬－半導體場效應電晶體(Metal－Semiconductor Field－Effect Transistor,MESFET)或金屬－氧化層－半導體場效電晶體(Metal－Oxide－Semiconductor Field－Effect Transistor,MOSFET簡稱金氧半場效電晶體MOS)。電晶體調整內建電阻的控制能力來自結構內pn接面形成內建電場(Built－In Potential)之順偏壓或逆偏壓之起始安排及選擇，係由射極(Emitter,E)、基極(Base,B)及集極(Collector,C)組成BJT電晶體之基極偏壓來控制電阻大小；或由源極(Source,S)、閘極(Gate,G)及汲極(Drain,D)組成諸FET之閘極偏壓來控制載子(Carrier,電子或電洞)之通(ON)與斷(OFF)。之後發展的MOS為避免電位漂浮(Floating)另增一基體(Body,B)而成一四端點電晶體。基極或閘極正如同水龍頭調整水流量大小或通－斷之功能。
在習知積體電路元件製作形態，上述不論三端點或四端點電晶體各極之材料單體，皆以擴散、沈積、離子植入或磊晶等單元半導體製程，形成具備長寬深度之方形佈置分佈形狀來製成，並能以三極平行介面形成上下或左右達成電晶體調整電阻作用者。因此元件與元件區格，偃然成為馬賽克式方形塊組成的積體電路結構。舉例如圖1所示，圖1－1為一CMOS反相器(Inverter)頂視圖，圖1－2為一對照橫截面圖。
1947年W.Shockley、Bardeen及Brattain在美國貝爾實驗室發明電晶體，其為點接觸式(Point Contact)鍺接面電晶體。此為美國專利US 2,569,347“Circuit Element Utilizing Semiconductive Material”Sept.25,1951公告所記。然於1960年代初期，以數位電腦微小化的需要下，將多數電晶體密集製造在基板上的想法；卻被發明電晶體之貝爾實驗室視為極端可笑的創意。時至今日，微電子技術已不斷地進步；貝爾實驗室的幽默成為追求不可能任務研究者背後的創造動力。
習知BJT的電流密度高、反應速度快之優點，在類比電路應用雖可大量使用；但應用在數位邏輯電路的反相器、電晶體－電晶體邏輯電路(Transistor－Transistor Logic,TTL)和射極耦合邏輯電路(Emitter－Coupled Logic,ECL)時，則受限於三極的面積，使BJT在積體電路的集積度方面無法和以電場電壓控制通斷的場效應(Field－Effect,FET)電晶體相比。因以基極電流控制集射極電流的BJT結構，基極實體層無論如何地薄均無法減免其做為載子交換體而必須存在的遺憾；而FET卻可將閘極往上方之空間移出，來以電壓控制源極與汲極間電流之通斷，使得FET在數位積體電路的集積度勝過BJT。又FET中習知金屬－氧化層－半導體場效電晶體MOSFET(以下簡稱MOS)，因具有更高集積度、更低消耗功率、更高輸入阻抗和更低輸入電流等優點而成為數位邏輯電路中最受青睬的元件結構。但N通道MOS(以下簡稱NMOS)主要導通之N通道載子的電子移動率遠大於P通道MOS(以下簡稱PMOS)電洞之移動率，若摻雜濃度相同且閘極寬長比相同時，NMOS之操作速度遠比PMOS快速；因此在高N－型摻雜濃度及高精準摻雜輪廓控制度之離子植入技術開發後，NMOS取代了PMOS。
如圖1－1及圖1－2所示，將一習知PMOS 103及一習知NMOS 101兩者串接以組成習知互補型金屬－氧化層－半導體場效電晶體(Complementary Metal－Oxide－Semiconductor Field－Effect Transistor，CMOSFET，以下簡稱CMOS)，其兩者閘極相接做數位邏輯電路訊號輸入端102、兩者串接之汲極與源極連線做為訊號輸出端104，並將兩者各接上VDD 高電位105及VSS 低電位106的雙態邏輯準位。當共同閘極輸入高或低電壓時，則兩者其中一條通道處於導通，而另一通道呈關閉狀態。亦即CMOS輸出端將隨NMOS和PMOS所接之高準位或低準位切換。理論上CMOS無靜態功率消耗，但只有PMOS和NMOS切換在同時導通的暫態瞬間，才產生動態的功率消耗。因此，1980年代後CMOS的發明，更成為數位邏輯電子產品更低耗能及快速運算的電晶體結構，貢獻良多；但由於習知CMOS電晶體結構係由NMOS及PMOS串接組成，不論是由單井或雙井結構所組成的CMOS，先天上串接連成一個pnpn的閘流體(Thyristor)寄生結構，並將產生閂鎖(Latch－up)效應，使得CMOS電壓控制功能有暫時性或永久失去的可能，甚或電流突增燒毀電路之缺點。
舉一具N型井CMOS反相器結構的閂鎖狀態說明，如圖2所示。圖2－1為N－井CMOS晶片的橫截面圖，圖2－2為其等效電路圖。Q⊥ 為垂直向寄生的PNP雙載子電晶體，是由PMOS電晶體的P＋ 源極、N型井及P型基板形成。Q∥ 為橫向寄生的NPN雙載子電晶體，是由NMOS電晶體的N＋ 源極、P型基板及N型井形成。橫向NPN的集極經由N型井連接垂直PNP的基極。垂直PNP的集極與橫向NPN的基極由P型基板相連。可見P型基板兼具(NPN的)基極、(PNP的)集極和NPN基極至PNP集極的連接介質等三種功能；而N井亦兼具(PNP的)基極、(NPN的)集極和PNP基極至NPN集極的連接線等三種功能，如此的P基板和N井(如同基板功能)變成重複的集基極共用方式(載子同源)，構成閂鎖主因(根除方法為徹底切割，將N井不要做在P基板上)。圖中Rw為N井至PMOS之源極P＋ 間之串連電阻，簡稱N井電阻，Rsub為P型基板至NMOS汲極N＋ 間之串連電阻，簡稱基板電阻。今舉例閂鎖發生的某一時刻，其可能來自於電壓的突波如電源開啟、游離事件或某些其它暫態，而產生足夠大的電流流經NPN電晶體的集極(n井和pnp之基極共用，亦即又當npn集極兼當pnp之基極－－－可能重複作用之衝突)，造成流經井電阻Rw電流偏壓PNP電晶體Q⊥ 的基射極。若此偏壓足夠迫使PNP電晶體之集極啟動產生電流流動。則流經基板電阻Rsub的電流能再偏壓NPN電晶體Q∥ 的基射極，使得Q∥ 放大更多電流並再流入井電阻Rw以擴大Q⊥ 偏壓，循環吸造成正回饋電路的作用。除非電源移開；否則將不會關閉此閂鎖效應。
習知避免閂鎖發生最直接方法，係以(1)增加NMOS及PMOS兩電晶體距離、(2)增加基極摻雜濃度、(3)基板上使用磊晶層(Epitaxial Layer)提高橫向電阻產生的較高觸發偏壓準位、(4)縮短基體接點和源極接點距離(Butted Contact)、(5)深溝隔絕(Trench Isolation)、(6)使用護環(Guard Ring)吸收注入電荷以防止雙載子動作、(7)絕緣層上複晶(Silicon On Insulator,SOI)及(8)使用三維CMOS如3D CMOS之堆疊式(Stacked CMOS)結構的方法等技術來防止閂鎖。其中第一至六項方法可從圖1－2等效電路中所示將Rw及Rsub變大來延緩或避免Q⊥ 提早啟動及再阻止Q∥ 啟動的方法來了解。但因這六項方法均會降低電路密度(集積度)且降低電路切換速度；其雖可改善閂鎖現象；但卻一直無法根除，尤其是集積度要求提高時。第七項SOI方法係將MOS完全建立在絕緣層上，閘流體結構近乎消失，不可能產生耦合電流，可直接有效地解決閂鎖效應。絕緣層上複晶SOI法雖能防止閂鎖；但其依然是將PMOS及NMOS在平面上並排組成，無法達到提高集積度。第八項的3D CMOS係將一個MOS製成後的上方再製作一個MOS，中間隔一氧化層，如圖2所示。此方法可成功克服閂鎖效應，但乃需克服立體方塊元件光罩對準的困難及在氧化層上方再做矽半導體結晶技術的問題。
使用低耗能优點CMOS除需克服先天閂鎖效應外，隨積體電路集積度提高後所伴隨如何處理所增加高密度元件數目之切換速度問題，為一件更值得重視的事。
克服習知CMOS閂鎖效應並提高集積度為本發明主要目的。本發明首先將習知PMOS製成同軸化結構PMOS(簡稱CPMOS)的方法、及習知NMOS製成同軸化結構NMOS(簡稱CNMOS)的方法及再將兩者上下顛倒接合而成完全對稱的互補型同軸金屬氧化層半導體場效應電晶體結構等方法來徹底解決閂鎖效應，並可提高集積度及反應速度的目的。全對稱的同軸互補型金屬氧化層半導體場效電晶體簡稱為同軸互補型金氧半場效電晶體(Coaxial Complementary Metal－Oxide－Semiconductor Field－Effect Transistor,以下簡稱CCMOSFET或CCMOS)，本發明之CCMOS將兩軸心導體上下串接且閘極共用，各上下半導體元件係兼具自身同軸對稱且上下互補對稱之完全互補對稱結構。則其上下互補重疊堆疊如同習知堆疊式3D CMOS可提高集積度，且達到完全防止閂鎖效應並提升邏輯開關反應速度之目的。詳述如下：一、p通道金屬氧化層半導體場效電晶體結構同軸化方法。如圖3－1所示，此為一n型基板301或基板之n型井上製作同軸p通道加強型金氧半場效電晶體之舉例說明，同軸電晶體結構內容包括一p摻雜圓環形汲極半導體區302、一p摻雜圓環形源極半導體區303及一在同一基板或井上且介於圓環形源極和汲極半導體區之間所形成圓環形通道區304及此圓環形通道區上方且被一氧化物層305隔絕的圓環形多晶矽或導體閘極306、一連接源極並以自身基板或井當參考電位之基體307、一連接基體和圓環形源極的同軸外環形供電導體層308、一連接汲極(載子集中處)半導體之內軸心導體309等元件所組成，此同軸p通道金氧半場效應電晶體結構內各圓環形元件及圓環形各極，係以同軸結構型態組成，且環形閘極306之電壓，其控制電晶體產生電流流動之方向，為各半徑方向地由圓周外環導體層308往軸心導體309之半徑向內匯集型式所組成的同軸電晶體者。如圖4－2電流匯集至軸心導體圖所示(其流出或流入係視源極做為內部或外部位置視使用需要來決定；可如同習知PMOS原設定為上拉式輸出入可變化之安排)，異於習知源極至汲極電流流動，如圖4－1所示者。本發明利用本人己申請發明專利『申請發明專利案號：095146963號』之專利名稱：『折射率分佈在半徑上的同軸光導光纖及其同軸半導體光源與檢光器共構的同軸光導系統』中之同軸半導體結構原理，將習知PMOS製成同軸化結構的CPMOS。由於軸心對稱的結構所提供均勻內建電場下的直接驅動電流(Drift Current)等距環向匯集快速流動；避免擴散電流之影響，提高反應速度並可減少雜訊。因在同軸供電兩電極提供電壓形成電場之驅動下，電洞或電子走最近距離方向移動，也正好為各半徑的電場極化方向，亦即在其形成最大徑向電場作用中，載子依最大徑向電場推動方向移動可快匯集或發散最高電流。
二、n通道金屬氧化層半導體場效電晶體結構同軸化方法。如圖3－2所示，此為一p型基板311或基板之p型井上製作n通道加強型金氧半場效應電晶體之舉例說明，同軸電晶體結構內容包括一N摻雜圓環形汲極半導體區312、一N摻雜圓環形源極半導體區313及一在同一基板或井上且介於圓環形源極311和汲極半導體區312之間所形成圓環形通道區314及此圓環形通道區上方且被一氧化物層315隔絕的圓環形多晶矽或導體閘極316、一連接源極並以自身基板或井當參考電位之基體317、一連接基體和圓環形源極的同軸外環形供電導體層318、一連接汲極(載子集中處)半導體之內軸心導體319等各元件所組成，其同軸n通道金氧半場效電晶體結構內各圓環形元件及圓環形各極，係以同軸結構型態組成，且其環形閘極316之電壓，其控制電晶體產生電流流動方向，為各半徑外向地由軸心導體319均勻發散流出至圓周外環導體層318之半徑向外發散型式所組成的同軸電晶體。如圖4－－3所示為電流從軸心均勻往外發散(其流出或流入係視源極做為內部或外部位置視使用需要來決定；可如同習知NMOS原設定為下拉式輸出入可變化之安排)，異於習知源極至汲極電流流動，如圖4－1所示者。本發明利用本人己申請發明專利『申請發明專利案號：095146963號』之專利名稱：『折射率分佈在半徑上的同軸光導光纖及其同軸半導體光源與檢光器共構的同軸光導系統』中之同軸半導體結構原理，將習知NMOS製成同軸化結構的CNMOS。由於軸心對稱的結構所提供均勻內建電場下的直接驅動電流(Drift Current)等距環向匯集快速流動；避免擴散電流之影響，提高反應速度並可減少雜訊。因在同軸供電兩電極提供電壓形成電場之驅動下，電子載子走最近距離方向移動，也正好為各半徑的電場極化方向，亦即在其形成最大徑向電場作用中，載子依最大徑向電場推動方向移動可快速發散或匯集最高電流。
三、上下顛倒接合且完全對稱互補型金氧半場效電晶體結構同軸化的方法。如圖5所示，此CCMOS為一個由圖3－1之CPMOS顛倒在上及一個由圖3－2之CNMOS在下接合而成。兩軸心導體309及319上下串接後之連線可構成上501及下502之輸出端。其閘極共用構成一電壓輸入控制端503，504為VDD 高電位，505為VSS 低電位。本發明之CCMOS將兩軸心導體上下串接且閘極共用，各上下半導體元件不但兼具自身同軸對稱且上下完全互補對稱結構可以由圖6表示。由於上面之CPMOS之pnp電晶與下面一個CNMOS之npn電晶體各元件已擺脫共用互接且徹底分割，可完全解決閂鎖效應之發生。異於習知並排組成之CMOS結構；本發明為上下重疊組成而提高集積度。且本發明同軸化電晶體結構內pn接面形成內建電場(Built－In Potential)為同軸對稱均勻分佈之內建電場，載子流動為環向半徑向內匯集或向外發散之半徑向等距離流動方式，可獲得更高反應速度並降低雜訊。
總結以上，本發明將習知PMOS製成同軸化結構CPMOS的方法、及習知NMOS製成同軸化結構CNMOS的方法及再將兩者上下顛倒接合而成完全對稱的互補型同軸金屬氧化層半導體場效電晶體CCMOS結構等方法可徹底解決閂鎖效應，並可提高集積度及反應速度的目的。以如此同軸結構化的各種金氧半場效電晶體，同樣實現電晶體成為“調動電阻者；移動或轉移電阻者”之“調整內建電阻，極大化使電流阻斷成為斷路(off)或極小化使電流暢通(on)”目的。其電流等距匯集和發散動作，如同花開花謝最省力且符合自然原理所形成積體數位邏輯電子技術，這將使數位積體電路的應用更加完美。
以下舉例說明本發明的實施例：
實施例
CCMOSFET同軸互補金氧半場效電晶體組成的反相器參照圖7之同軸互補金氧半場效電晶體組成的反相器積體電路，此各反相器係為一個由圖3－1之CPMOS顛倒在上及一個由圖3－2之CNMOS在下接合而成CCMOS的結構以實現反相電路作用。兩軸心導體上下串接後之連線可構成上701及下702之輸出端。其閘極共用構成一電壓輸入控制端703。每一個CCMOS係將兩軸心導體上下串接且閘極共用，各上下半導體元件不但兼具自身同軸對稱且上下完全互補對稱而構成的同軸反相器。各反相器間以隔離層706隔離。當各反相器之輸入端輸入低電壓準位時，共同閘極之低電壓感應其上CPMOS之P通道接通電流，其源極704之正電洞載子源以高電壓VDD 供電，半徑向匯集電流至軸心串接電導體，以輸出高電壓準位至軸心導體輸出端701及702。亦即原為低電壓或低準位可上拉輸出高電壓或成高準位；當反相器之輸入端703輸入高電壓準位時，共同閘極之高電壓感應其下CNMOS之N通道接通電流，其源極705 VSS 之電子載子源負電壓供電，半徑向匯集電子流至軸心串接電導體輸出端701及702，輸出低電壓準位。亦即原為高電壓或高準位可下拉輸出低電壓或成為低準位。此源極VSS 低電壓若接地，則VSS 視為接地電壓。若為邏輯雙電壓準位，則為負電位。如此則實現反相電路作用，其積體電路組成的結構因同軸化且上下重疊堆疊式的型式，提高集積度。又因同軸化電晶體內均勻電場快速驅動電流其匯集與發散的自然力作用可更節省所消耗功率。
以上本發明實施例闡述各種細節所引用各參考編號之元件，皆可視為相同或功能上類似之元件，且意欲以極簡化的圖解方式來圖說實例所表示之主要實施特點；因此，此圖示並非意欲描繪出實際實施例之所有特點，亦並非意欲描繪所繪元件之相對尺寸及數量，故所示之圖並非按比例繪成，其係按本發明之同軸化電晶體結構的基本精神所繪成。
以上所舉例並圖示顯示本發明的同軸電晶體所製成的同軸金氧半場效電晶體及同軸互補型金氧半場效電晶體之反相器裝置，僅作為代表本發明同軸電晶體主要精神之同軸共構的主張，以說明其他可據以等效發揮同軸共構的電晶體功能及據以應用的各種樣態。
實例上所談，本同軸電晶體所組成的各種金氧半場效電晶體及反相器裝置，不但擁有高集積度、高反應速度及完全免除閂鎖效應，可用來表現在各種積體數位邏輯電路應用場合及各種高速且大量資訊儲存的記憶體結構，如同軸化之SRAM、同軸化之DRAM、同軸化之ROM..等同軸化之各種記憶體。甚或同軸雙異質接面雙極性電晶體(Coaxial Double Heterojunction Bipolar Transistor,DHBT)。則此各同軸化電晶體的產品皆可以較低成本量產，且可以達到同軸化省電結構達到節省能源的目的。
應可瞭解，上述每一元件之功能及其同軸使用電流通斷功能、或兩個或多個元件之功能及其同軸化上下堆疊量產，皆可單獨或共同有效應用在不同於上述類型之其它類型之同軸共構電晶體邏輯運算系統及製程系統中，而達到有益人類的綜效價值。
儘管本文係以同軸金氧半場效電晶體及其組成互補型金氧半場效電晶體和反相器結構圖解說明並闡述本發明之同軸電晶體結構；但此並非意欲僅將本發明侷限於此等圖示細節，因為在以不脫離本發明精神之任何方式之前提下，可對本發明實施各種修改及結構之改變。
無需再分析以上說明所全面披露本發明之要旨，其己可以使人們能夠應用現有知識在合併根據先前技術觀點，以合理構成本發明之一般或具體樣態之基本特徵之前提下，可輕易地將本發明修改用於各種應用或改用其他材料應用於本發明，且因此，此等修改應該且己意欲包含在隨附申請專利範圍之等效意義及範圍內。
101．．．NMOS
102．．．訊號輸入端
103．．．PMOS
104．．．訊號輸出端
105．．．VDD 高電位
106．．．VSS 低電位
301．．．n型基板
302．．．p摻雜圓環形汲極半導體區
303．．．p摻雜圓環形源極半導體區
304．．．圓環形通道區
305．．．氧化物層
306．．．圓環形多晶矽或導體閘極
307．．．基體
308．．．同軸外環形供電導體層
309．．．軸心導體
311．．．p型基板
312．．．n摻雜圓環形汲極半導體區
313．．．n摻雜圓環形源極半導體區
314．．．圓環形通道區
315．．．氧化物層
316．．．圓環形多晶矽或導體閘極
317．．．基體
318．．．同軸外環形供電導體層
319．．．軸心導體
501‧‧‧上輸出端
502‧‧‧下輸出端
503‧‧‧共閘極輸入端
504‧‧‧VDD 高電位
505‧‧‧VSS 低電位
701‧‧‧上輸出
702‧‧‧下輸出
703‧‧‧電壓輸入端
704‧‧‧高電壓VDD 供電
705‧‧‧低電壓VSS 位
706‧‧‧隔離層
圖1－1 為習知CMOS互補型金氧半場效電晶體積體電路反相器單元頂視結構示意圖圖1－2 為對照圖1－1習知CMOS互補型金氧半場效電晶體積體電路單元結構橫截面示意圖圖2－1 為習知CMOS反相器中產生閂鎖現象之晶片橫截面示意圖圖2－2 為習知CMOS反相器中產生閂鎖現象之等效電路示意圖圖3－1 為同軸p通道金屬氧化物半導體場效電晶體結構剖面示意圖圖3－2 為同軸n通道金屬氧化物半導體場效電晶體結構剖面示意圖圖4－1 為習知頂視源極至汲極電流流動示意圖圖4－2 為電流匯集至軸心導體示意圖圖4－3 為為電流從軸心均勻往外發散示意圖圖5 為同軸互補型金氧半場效應電晶體結構剖面示意圖圖6 為同軸化完全對稱互補型金氧半場效電晶體橫截面結構示意圖圖7 為同軸互補金氧半場效電晶體組成的反相器實施例圖
301．．．n型基板
302．．．p摻雜圓環形汲極半導體區
303．．．p摻雜圓環形源極半導體區
304．．．圓環形通道區
305．．．氧化物層
306．．．圓環形多晶矽或導體閘極
307．．．基體
308．．．同軸外環形供電導體層
309．．．軸心導體
311．．．p型基板
312．．．n摻雜圓環形汲極半導體區
313．．．n摻雜圓環形源極半導體區
314．．．圓環形通道區
315．．．氧化物層
316．．．圓環形多晶矽或導體閘極
317．．．基體
318．．．同軸外環形供電導體層
319．．．軸心導體

Claims (6)

  1. 一種同軸p通道金屬-氧化層-半導體場效電晶體結構，為一n型基板或基板之n型井上製作加強型或空乏型同軸電晶體結構，內容包括：一p摻雜圓環形汲極半導體區；及一p摻雜圓環形源極半導體區；及一在同一基板或井上且介於圓環形源極和汲極半導體區之間所形成圓環形通道區及此圓環形通道區上方且被一氧化層隔絕的圓環形多晶矽或導體閘極；及一連接源極並以自身基板或井當參考電位之基體；及一連接基體和圓環形源極的同軸外環形供電導體層；及一連接汲極(載子集中處)半導體之內軸心導體；或其他作為必要電晶體功用的圓環形元件等材料所組成，其特徵為同軸p通道金氧半場效電晶體結構內各圓環形元件及圓環形各極，係以同軸結構型態組成及p摻雜圓環形汲極半導體區係以 側面連接內軸心導體(laterally formed in contact with the inner axial conductor)，且其環形閘極之電壓控制電晶體產生電流流動方向，為各半徑方向地由圓周外環導體層往軸心導體之半徑向匯集型式所組成的同軸電晶體者。
  2. 如申請專利範圍第1項所述之同軸電晶體，源極連接供電之軸心導體；且汲極連接同軸的外環導體並與基體連接做參考電位，其特徵係於p摻雜圓環形源極半導體區以側面連接供電之軸心導體且閘極之電壓控制電晶體產生電流流動方向，為各半徑方向地由軸心導體均勻發散流出至圓周外環導體層之半徑向發散型式所組成的同軸電晶體者。
  3. 一種同軸n通道金屬-氧化層-半導體場效電晶體結構，為一p型基板或基板之p型井上製作加強型或空乏型同軸電晶體結構，內容包括：一n摻雜圓環形汲極半導體區；及一n摻雜圓環形源極半導體區；及一在同一基板或井上且介於圓環形源極和汲極半導體區之間所形成圓環形通道區及此圓環形通道區上方且被一氧化層隔絕的圓環形多晶矽或導體閘極；及一連接源極並以自身基板或井當參考電位之基體；及一連接基體和圓環形源極的同軸外環形供電導體層；及一連接汲極(載子集中處)半導體之內軸心導體；或 其他作為必要電晶體功用的圓環形元件等材料所組成，其特徵為同軸n通道金氧半場效電晶體結構內各圓環形元件及圓環形各極，係以同軸結構型態組成及n摻雜圓環形汲極半導體區係以側面連接內軸心導體，且其環形閘極之電壓控制電晶體產生電流流動方向，為各半徑方向地由軸心導體均勻發散流出至圓周外環導體層之半徑向發散型式所組成的同軸電晶體者。
  4. 如申請專利範圍第3項所述之同軸電晶體，源極連接供電之軸心導體；且汲極連接同軸的外環導體並與基體連接做參考電位，其特徵係於n摻雜圓環形源極半導體區以側面連接供電之軸心導體且閘極之電壓控制電晶體產生電流流動方向，為各半徑方向地由圓周外環導體層往軸心導體之半徑向匯集型式所組成的同軸電晶體者。
  5. 一種同軸互補型金屬氧化層半導體場效電晶體結構(Coaxial Complementary Metal-Oxide-Semiconductor Field-Effect Transistor,CCMOSFET)，係由如申請專利範圍第1項之一個同軸P通道金氧半場效電晶體及如申請專利範圍第3項所述之一個同軸N通道金氧半場效電晶體等兩者上下顛倒接合而成，其特徵係以兩軸心導體上下串接且閘極共用，各上下半導體元件係完全互補對稱且各金氧半場效電晶體自身係以軸心同軸共構之型態組合結構者。
  6. 如申請專利範圍第5項要求的一種同軸互補型金氧半場效 電晶體反相器結構，包括：一共用閘極係做為反相器之輸入端；及一軸心串接連線做為反相器之輸出端，其特徵係當反相器之輸入端輸入低電壓準位時，共同閘極之低電壓感應P通道接通電流，其源極之正電洞載子源高電壓供電半徑向匯集電流至軸心串接電導體以輸出高電壓準位；當反相器之輸入端輸入高電壓準位時，共同閘極之高電壓感應N通道接通電流，其源極之電子載子源負電壓供電半徑向匯集電子流至軸心串接電導體以輸出低電壓準位者。
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Families Citing this family (10)

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Publication number Priority date Publication date Assignee Title
US9412442B2 (en) * 2012-04-27 2016-08-09 The Board Of Trustees Of The University Of Illinois Methods for forming a nanowire and apparatus thereof
US9337261B2 (en) 2013-04-10 2016-05-10 GlobalFoundries, Inc. Method of forming microelectronic or micromechanical structures
US9740875B2 (en) 2013-09-30 2017-08-22 Elwha Llc Mobile device sharing facilitation methods and systems featuring exclusive data presentation
US9838536B2 (en) 2013-09-30 2017-12-05 Elwha, Llc Mobile device sharing facilitation methods and systems
US9774728B2 (en) 2013-09-30 2017-09-26 Elwha Llc Mobile device sharing facilitation methods and systems in a context of plural communication records
US9813891B2 (en) 2013-09-30 2017-11-07 Elwha Llc Mobile device sharing facilitation methods and systems featuring a subset-specific source identification
US9805208B2 (en) 2013-09-30 2017-10-31 Elwha Llc Mobile device sharing facilitation methods and systems with recipient-dependent inclusion of a data selection
US9826439B2 (en) 2013-09-30 2017-11-21 Elwha Llc Mobile device sharing facilitation methods and systems operable in network equipment
CN114242790A (zh) * 2019-12-18 2022-03-25 电子科技大学 一种新型数字门集成电路的结构
US11908907B2 (en) * 2020-12-11 2024-02-20 International Business Machines Corporation VFET contact formation

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4143392A (en) * 1977-08-30 1979-03-06 Signetics Corporation Composite jfet-bipolar structure
US4876579A (en) * 1989-01-26 1989-10-24 Harris Corporation Low top gate resistance JFET structure
US5637891A (en) * 1994-12-08 1997-06-10 Goldstar Electron Co., Ltd. Charge coupled device having different insulators
US6525383B1 (en) * 1997-02-14 2003-02-25 Siemens Aktiengesellschaft Power MOSFET
US20070096174A1 (en) * 2005-11-01 2007-05-03 Denso Corporation Semiconductor device having PN junction diode and method for manufacturing the same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131573A (ja) * 1985-12-04 1987-06-13 Hitachi Ltd 半導体装置
JPH03196672A (ja) * 1989-12-26 1991-08-28 Nec Corp Ｃｍｏｓ集積回路
JPH05259398A (ja) * 1992-03-13 1993-10-08 Mazda Motor Corp 半導体装置およびその製造方法
KR0179799B1 (ko) * 1995-12-29 1999-03-20 문정환 반도체 소자 구조 및 그 제조방법
JP2005268662A (ja) * 2004-03-19 2005-09-29 Seiko Epson Corp ３次元デバイスの製造方法
JP4629490B2 (ja) * 2005-05-09 2011-02-09 三菱電機株式会社 誘電体分離型半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4143392A (en) * 1977-08-30 1979-03-06 Signetics Corporation Composite jfet-bipolar structure
US4876579A (en) * 1989-01-26 1989-10-24 Harris Corporation Low top gate resistance JFET structure
US5637891A (en) * 1994-12-08 1997-06-10 Goldstar Electron Co., Ltd. Charge coupled device having different insulators
US6525383B1 (en) * 1997-02-14 2003-02-25 Siemens Aktiengesellschaft Power MOSFET
US20070096174A1 (en) * 2005-11-01 2007-05-03 Denso Corporation Semiconductor device having PN junction diode and method for manufacturing the same

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