CN106158815B - 半导体衬底结构、半导体封装及其制造方法 - Google Patents

半导体衬底结构、半导体封装及其制造方法 Download PDF

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CN106158815B
CN106158815B CN201510196538.9A CN201510196538A CN106158815B CN 106158815 B CN106158815 B CN 106158815B CN 201510196538 A CN201510196538 A CN 201510196538A CN 106158815 B CN106158815 B CN 106158815B
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conductive
dielectric
semiconductor substrate
width
layer
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CN106158815A (zh
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陈天赐
陈光雄
王圣民
李育颖
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Abstract

本发明涉及一种半导体衬底结构、半导体封装及其制造方法。所述半导体衬底结构包含导电结构和电介质结构。所述导电结构具有第一导电表面和与所述第一导电表面相对的第二导电表面。所述电介质结构遮盖所述导电结构的至少一部分，且具有第一电介质表面和与所述第一电介质表面相对的第二电介质表面。所述第一导电表面并非从所述第一电介质表面突出，且所述第二导电表面从所述第二电介质表面凹进。所述电介质结构包含光敏树脂或由其形成，且所述电介质结构界定在所述第二电介质表面中的电介质开口以暴露所述第二导电表面的一部分。

Description

半导体衬底结构、半导体封装及其制造方法
技术领域
本发明涉及一种半导体衬底结构、半导体封装及其制造方法，且更确切地说，涉及一种包含光敏树脂的半导体衬底结构、包含所述半导体衬底结构的半导体封装以及其制造方法。
背景技术
半导体工业中的设计趋势包含半导体产品的重量减少以及小型化。然而，重量减轻以及小型化的技术可导致制造问题。举例来说，具有一个嵌入导电迹线层的薄半导体衬底可导致制造期间的低良率，这是因为可能难以处置薄半导体衬底结构。
因此，需要提供一种改良的半导体衬底结构、半导体封装及其制造方法。
发明内容
本发明的一个方面涉及一种半导体衬底结构。在一个实施例中，所述半导体衬底结构包括导电结构和电介质结构。导电结构具有第一导电表面和与第一导电表面相对的第二导电表面。电介质结构遮盖导电结构的至少一部分，且具有第一电介质表面和与第一电介质表面相对的第二电介质表面。第一导电表面并非自第一电介质表面突出，且第二导电表面自第二电介质表面凹进。电介质结构包含固化光敏树脂或由其形成，且电介质结构界定第二电介质表面中的电介质开口以暴露第二导电表面的一部分。
本发明的另一方面涉及一种半导体封装。在一个实施例中，所述半导体封装包括半导体衬底结构、半导体裸片以及模塑料。半导体衬底结构包括导电结构和电介质结构。导电结构具有第一导电表面和与第一导电表面相对的第二导电表面。电介质结构遮盖导电结构的至少一部分，且具有第一电介质表面和与第一电介质表面相对的第二电介质表面。第一导电表面并非自第一电介质表面突出，且第二导电表面自第二电介质表面凹进。电介质结构包含固化光敏树脂或由其形成，且电介质结构界定第二电介质表面中的电介质开口以暴露第二导电表面的一部分。半导体裸片电连接到第一导电表面。模塑料遮盖半导体裸片和半导体衬底结构的一部分。
本发明的另一方面涉及一种用于制造半导体衬底结构的方法。在一个实施例中，所述方法包括：(a)提供第一载体；(b)在第一载体上形成导电结构，其中导电结构具有第一导电表面和与第一导电表面相对的第二导电表面，且第一导电表面安置于第一载体上；(c)形成电介质结构以遮盖导电结构，其中电介质结构具有第一电介质表面和与第一电介质表面相对的第二电介质表面，电介质结构包含光敏树脂，且第一导电表面实质上与第一电介质表面共面；(d)在电介质结构的第二电介质表面中形成电介质开口以暴露第二导电表面的一部分；(e)去除第一载体，其中第一导电表面从第一电介质表面暴露；以及(f)在第二电介质表面上提供第二载体。
附图说明
图1说明根据本发明的实施例的半导体衬底结构的横截面图。
图1A说明图1的半导体衬底结构的区域A的部分放大视图。
图2说明根据本发明的另一实施例的半导体衬底结构的横截面图。
图3说明根据本发明的另一实施例的半导体衬底结构的横截面图。
图4说明根据本发明的另一实施例的半导体衬底结构的横截面图。
图5说明根据本发明的另一实施例的半导体衬底结构的横截面图。
图6说明根据本发明的另一实施例的半导体衬底结构的横截面图。
图7说明根据本发明的另一实施例的半导体衬底结构的横截面图。
图8说明根据本发明的另一实施例的半导体衬底结构的横截面图。
图9说明根据本发明的另一实施例的半导体衬底结构的横截面图。
图10说明根据本发明的实施例的半导体封装的横截面图。
图11说明根据本发明的另一实施例的半导体封装的横截面图。
图12说明根据本发明的另一实施例的半导体封装的横截面图。
图13说明根据本发明的另一实施例的半导体封装的横截面图。
图14说明根据本发明的另一实施例的半导体封装的横截面图。
图15说明根据本发明的另一实施例的半导体封装的横截面图。
图16A、图16B、图16C、图16D、图16E、图16F、图16G、图16H、图16I、图16J、图16K和图16L说明根据本发明的实施例制造半导体封装的方法。
图17A、图17B、图17C、图17D、图17E、图17F、图17G和图17H说明根据本发明的另一实施例的制造半导体封装的方法。
具体实施方式
如说明书中所描述和各图中所展示，相对于某一元件或元件的某一平面指定空间描述，例如，“在…上方”、“在…下方”、“向上”、“左”、“右”、“向下”、“顶部”、“底部”、“垂直”、“水平”、“侧面”、“较高”、“下部”、“上部”、“在…之上”、“在…之下”，等等。此外，应理解本文中所使用的空间描述仅出于说明的目的，且本文中所描述的结构的实际实施方案可以任何定向或方式在空间上布置，其限制条件为本发明的实施例的优点不因此布置而有偏差。
图1说明根据本发明的实施例的半导体衬底结构100A的横截面图。半导体衬底结构100A的厚度可在约20微米(μm)到约60μm的范围内；举例来说，在约20μm到约50μm范围内，在约20μm到约40μm范围内，或在约20μm到约30μm范围内。半导体衬底结构100A包含电介质结构104和一或多个导电结构106。在此实施例中，电介质结构104为电介质层110，且具有第一电介质表面112、与第一电介质表面112相对的第二电介质表面114，以及在第二电介质表面114中的一或多个电介质开口116。电介质层110的材料包含具有互穿聚合物网络(IPN)结构的固化光敏树脂或由其形成。光敏树脂包含基体树脂(例如，丙烯酸树脂或环氧树脂)和光引发剂。在一些实施例中，光敏树脂为来自太阳油墨制造有限公司(Taiyo Ink Mfg.Co.,Ltd)的CA-40 AUS320。
在此实施例中，导电结构106为单层金属层结构，并包括第一图案化导电层118。第一图案化导电层118包括一或多个接合垫131(例如，用于倒装芯片接合的凸块衬垫或用于线接合的手指衬垫)、一或多个球衬垫133以及第一导电迹线134。第一图案化导电层118具有第一导电表面122和与第一导电表面122相对的第二导电表面124。电介质结构104(电介质层110)遮盖导电结构106的至少一部分(第一图案化导电层118)。第一导电表面122并非从第一电介质表面112突出，这意味着第一导电表面122的部分或全部可实质上与第一电介质表面112共面，或从第一电介质表面112凹进。第二导电表面124从第二电介质表面114凹进。电介质开口116暴露第二导电表面124的部分。球衬垫133是第二导电表面124的暴露部分。
如针对图1的实施例所说明，第一导电表面122实质上与电介质层110的第一电介质表面112共面。接合垫131(例如，凸块衬垫或手指衬垫)各自具有沿第一导电表面122的上表面和沿第二导电表面124的下表面。接合垫131中的每一者的上表面从第一电介质表面112暴露，且接合垫131中的每一者的下表面由电介质结构104(电介质层110)遮盖。球衬垫133各自具有沿第一导电表面122的上表面和沿第二导电表面124的下表面。球衬垫133中的每一者的上表面从第一电介质表面112暴露，且球衬垫133中的每一者的下表面在电介质开口116中暴露。如所说明，第一导电迹线134连接接合垫131与球衬垫133。在此实施例中，第一导电迹线134可为细间距，例如，迹线中心之间的小于或等于约15μm，或小于或等于约10μm的间距。
图1A说明图1的半导体衬底结构100A的区域A的部分放大视图。界定电介质开口116的侧壁130为曲狀的。即，电介质开口116具有在第二电介质表面114处的第一宽度W1和在电介质开口116的中间部分处的第二宽度W2，且第一宽度W1大于第二宽度W2。举例来说，第一宽度W1与第二宽度W2之间的差可为至少约2μm，例如，至少约3μm、至少约4μm、至少约5μm或至少约10μm。作为另一实例，第一宽度W1与第二宽度W2的比率可为至少约1.05、至少约1.1、至少约1.2、至少约1.3、至少约1.4、至少约1.5或至少约2。参看图16H描述曲狀侧壁130的形成的实例。
图2说明根据本发明的另一实施例的半导体衬底结构100B的横截面图。除图2的实施例的第一导电表面122从第一电介质表面112凹进以外，此实施例的半导体衬底结构100B类似于图1中所说明的半导体衬底结构100A。在其它实施例中，第一导电表面122的部分从第一电介质表面112凹进，而第一导电表面122的其它部分实质上与第一电介质表面112共面。
图3说明根据本发明的另一实施例的半导体衬底结构100C的横截面图。除球衬垫133中的每一者包含在暴露于电介质开口116中的球衬垫133的下表面上的凹部132以外，此实施例的半导体衬底结构100C类似于图1中所说明的半导体衬底结构100A。参看图16H描述凹部132的形成的实例。
图4说明根据本发明的另一实施例的半导体衬底结构100D的横截面图。除阻焊层136安置在第一导电表面122和第一电介质表面112上以外，此实施例的半导体衬底结构100D类似于图1中所说明的半导体衬底结构100A。阻焊层136包含多个开口1361以暴露一或多个第一导电迹线134和一或多个接合垫131。阻焊层136的材料可与电介质层110的材料相同或不同。一般来讲，阻焊层136的材料可为(例如)预浸体、味之素累积膜(ABF)、光阻剂、液晶聚合物(LCP)、聚酰亚胺(PI)或光敏树脂中的一者或其组合。
图5说明根据本发明的另一实施例的半导体衬底结构100E的横截面图。除半导体衬底结构100E进一步包括阻焊层137和一或多个表面处理层(Surface Finish Layer)138以外，此实施例的半导体衬底结构100E类似于图1中所说明的半导体衬底结构100A。阻焊层137安置在第一导电表面122和第一电介质表面112上，并包含多个开口1371以暴露接合垫131(手指衬垫)。阻焊层137的材料可与电介质层110的材料相同或不同。一般来讲，阻焊层137的材料可为(例如)预浸体(Pre-preg)、味之素累积膜(Ajinomoto build-up film，ABF)、光阻剂、液晶聚合物(LCP)、聚酰亚胺(PI)或光敏树脂中的一者或其组合。表面处理层138安置在所暴露接合垫131上的开口1371中。表面处理层138可以由一或多个个别层形成，所述个别层的每一者可为(例如)镍、金、银或其合金。
图6说明根据本发明的另一实施例的半导体衬底结构100F的横截面图。除半导体衬底结构100F进一步包括一或多个导电柱128以外，此实施例的半导体衬底结构100F类似于图1中所说明的半导体衬底结构100A。导电柱128从第一导电表面122突出，且安置在接合垫131的对应者上，以便电连接到导电结构106。导电柱128的材料可为铜；然而，本发明并不限于此。在一个实施例中，晶种层990可安置在导电柱128下方，即晶种层990的一部分安置于每一导电柱128与其对应接合垫131之间。然而，可省去晶种层990。
图7说明根据本发明的另一实施例的半导体衬底结构100G的横截面图。除半导体衬底结构100G进一步包括一或多个表面处理层236和阻焊层139以外，此实施例的半导体衬底结构100G类似于图6中所说明的半导体衬底结构100F。表面处理层236安置在导电柱128的对应者上。在一些实施例中，如图7中所说明，在相应导电柱128下方的晶种层990部分的宽度小于相应导电柱128的宽度，因此，表面处理层236遮盖导电柱128的顶面和侧面以及导电柱128的底部表面的一部分，且进一步延伸至导电柱128与接合垫131之间的空间中。阻焊层139安置在第一导电表面122和第一电介质表面112上，且包含一个或多个开口1391以暴露导电柱128。阻焊层139的材料可与电介质层110的材料相同或不同。一般来讲，阻焊层139的材料可为(例如)预浸体、味之素累积膜(ABF)、光阻剂、液晶聚合物(LCP)、聚酰亚胺(PI)或光敏树脂中的一者或其组合。所述一或多个表面处理层236中的每一层可由(例如)镍、金、银或其合金形成。
图8说明根据本发明的另一实施例的半导体衬底结构100H的横截面图。除半导体衬底结构100H进一步包括阻焊层139和一或多个第一金属凸块228以外，此实施例的半导体衬底结构100H类似于图6中所说明的半导体衬底结构100F。第一金属凸块228安置在球衬垫133的相应者的上表面上。第一金属凸块228的材料可为铜；然而，本发明并不限于此。在一个实施例中，晶种层990可安置于第一金属凸块228下方，即晶种层990的一部分安置于每一第一金属凸块228与其相应球衬垫133之间。然而，可省去晶种层990。第一金属凸块228可提高球衬垫133的强度。因此，在提供模塑料以遮盖半导体衬底上的裸片的过程期间，球衬垫133发生开裂或其它损坏的风险减小。阻焊层139安置在第一导电表面122和第一电介质表面112上，并遮盖第一金属凸块228。阻焊层139包含开口1391以暴露一或多个导电柱128。阻焊层139的材料可与电介质层110的材料相同或不同。一般来讲，阻焊层139的材料可为(例如)预浸体、味之素累积膜(ABF)、光阻剂、液晶聚合物(LCP)、聚酰亚胺(PI)或光敏树脂中的一者或其组合。
图9说明根据本发明的另一实施例的半导体衬底结构100I的横截面图。此实施例的半导体衬底结构100I类似于图1中所说明的半导体衬底结构100A，且差异描述如下。半导体衬底结构100I的电介质结构304包含第一电介质层342和第二电介质层344。第一电介质层342具有第一电介质表面312(对应于电介质结构304的第一表面)和第三电介质表面350，且第二电介质层344具有第二电介质表面314(对应于电介质结构304的第二表面)和一或多个电介质开口316。第一电介质层342的材料可为(例如)预浸体、味之素累积膜(ABF)、光阻剂、液晶聚合物(LCP)、聚酰亚胺(PI)或光敏树脂中的一者或其组合。第二电介质层344的材料包含具有互穿聚合物网络(IPN)结构的固化光敏树脂或由其形成。光敏树脂包含基体树脂(例如，丙烯酸树脂或环氧树脂)和光引发剂。在一些实施例中，光敏树脂为来自太阳油墨制造有限公司的CA-40 AUS320。
半导体衬底结构100I的导电结构306包括第一图案化导电层318、一或多个导电通孔346和第二图案化导电层348。电介质结构304遮盖导电结构306的至少一部分。第一图案化导电层318具有第一导电表面322和一或多个接合垫331。第一导电表面322从第一电介质层342的第一电介质表面312暴露。在一些实施例(例如，图9中所说明的实施例)中，第一导电表面322实质上与第一电介质层342的第一电介质表面312共面，且接合垫331从第一电介质表面312暴露。在其它实施例中，第一导电表面322从第一电介质层342的第一电介质表面312凹进。第二图案化导电层348安置在第三电介质表面350上。第二图案化导电层348具有导电表面324和一或多个球衬垫352。第二导电表面324从第二电介质表面314凹进。一或多个电介质开口316暴露第二导电表面324的一部分。球衬垫352为第二导电表面324的暴露部分。球衬垫352在电介质开口316的相应者中暴露。界定电介质开口316的侧壁是曲狀的。导电通孔346延伸穿过电介质结构304的第一电介质层342并电连接第一图案化导电层318与第二图案化导电层348。
图10说明根据本发明的实施例的半导体封装200A的横截面图。半导体封装200A包括半导体衬底结构100A、一或多个焊料凸块560、半导体裸片562以及模塑料564。此实施例的半导体衬底结构100A与参看图1说明并描述的半导体衬底结构100A相同。焊料凸块560安置在电介质结构104的电介质开口116中，且物理上并电学上连接到球衬垫133的相应者。在此实施例中，由电介质开口116的曲狀侧壁130和由电介质开口116暴露的球衬垫133的底部表面界定的空间提供用于对应焊料凸块560的互锁功能。即，在焊料凸块560安置在电介质开口116中之后，焊料凸块560将具有符合曲狀侧壁130的颈部部分，且颈部部分可防止焊料凸块560与球衬垫133分隔。焊料凸块560从电介质结构104的第二电介质表面114突出。半导体裸片562安置在半导体衬底结构100A的第一衬底表面566(包含在此实施例中实质上彼此共面的第一电介质表面112和第一导电表面122)上，且电连接到接合垫131，以便电连接到导电结构106的第一导电表面122。
在此实施例中，半导体裸片562包含在其有源表面上的一或多个凸块下方金属化物(UBM)578和安置在UBM 578的相应者上的一或多个导电柱580。半导体裸片562经由半导体裸片562的导电柱580上的焊料539电学上并物理上连接到半导体衬底结构100A的第一导电表面122。模塑料564遮盖半导体裸片562、导电柱580、焊料539以及半导体衬底结构100A的第一衬底表面566的一部分。在此实施例中，导电柱580提供充分大空间，使得模塑料564可遮盖半导体裸片562的有源表面上的元件。因此，不需要昂贵的底部填充，借此减少制造成本。
图11说明根据本发明的另一实施例的半导体封装200B的横截面图。半导体封装200B包括半导体衬底结构100D、一或多个焊料凸块560、半导体裸片562和模塑料564。此实施例的半导体衬底结构100D与图4中所说明的半导体衬底结构100D相同。焊料凸块560安置在电介质结构104的电介质开口116中，且物理上并电学上连接到球衬垫133的相应者。半导体裸片562安置在半导体衬底结构100D的第一衬底表面566(包含在此实施例中实质上彼此共面的第一电介质表面112和第一导电表面122)上，且电连接到接合垫131，以便电连接到导电结构106的第一导电表面122。
在此实施例中，半导体裸片562包含在其有源表面上的一或多个UBM 578和安置在UBM 578的相应者上的一或多个导电柱580。半导体裸片562经由半导体裸片562的导电柱580上的焊料539电学上并物理上连接到半导体衬底结构100D的第一导电表面122。模塑料564遮盖半导体裸片562、导电柱580、焊料539以及半导体衬底结构100D的第一衬底表面566的一部分。
图12说明根据本发明的另一实施例的半导体封装200C的横截面图。半导体封装200C包括半导体衬底结构100E、一或多个焊料凸块560、半导体裸片562、一或多个接合线668和模塑料564。此实施例的半导体衬底结构100E与图5中所说明的半导体衬底结构100E相同。焊料凸块560安置在电介质结构104的电介质开口116中，且物理上并电学上连接到球衬垫133的相应者。半导体裸片562安置在半导体衬底结构100E的顶部表面上，并电连接到接合垫131，以便电连接到导电结构106的第一导电表面122。
在此实施例中，半导体裸片562的背面粘着在阻焊层137上，且半导体裸片562的有源表面经由接合线668电连接到半导体衬底结构100E的第一导电表面122上的表面处理层138。模塑料564遮盖半导体裸片562、接合线668、表面处理层138以及阻焊层137。
图13说明根据本发明的另一实施例的半导体封装200D的横截面图。此实施例的半导体封装200D类似于图10中所说明的半导体封装200A，且差异描述如下。半导体封装200D包括半导体衬底结构100F(图6)、一或多个焊料凸块560、半导体裸片562以及模塑料564。半导体衬底结构100F包含一或多个导电柱128，如参看图6所描述。导电柱128从第一导电表面122突出，且安置在接合垫131的相应者上。半导体裸片562的导电柱580上的焊料539物理上并电学上连接到半导体衬底结构100F的导电柱128。
图14说明根据本发明的另一实施例的半导体封装200E的横截面图。此实施例的半导体封装200E类似于图13中所说明的半导体封装200D，且差异描述如下。半导体封装200E包括半导体衬底结构100H(图8)、一或多个焊料凸块560、半导体裸片562以及模塑料564。半导体衬底结构100H包含阻焊层139和一或多个第一金属凸块228，如参看图8所描述。第一金属凸块228安置在球衬垫133的相应者的上表面上。第一金属凸块228可提高球衬垫133的强度。因此，在提供模塑料564以遮盖半导体衬底上的半导体裸片562的过程期间，球衬垫133发生开裂或其它损坏的风险减小。阻焊层139遮盖第一金属凸块228，且具有开口1391以暴露导电柱128。
图15说明根据本发明的另一实施例的半导体封装200F的横截面图。半导体封装200F包括半导体衬底结构100G(图7)、一或多个焊料凸块560、半导体裸片562、一或多个接合线668以及模塑料564。焊料凸块560安置在电介质结构104的电介质开口116中，且物理上并电学上连接到球衬垫133的相应者。半导体衬底结构100G包含一或多个表面处理层236和阻焊层139，如参看图7所描述。
半导体裸片562安置在半导体衬底结构100G的上表面上，并电连接到接合垫131，以便电连接到导电结构106的第一导电表面122。在此实施例中，半导体裸片562的背面粘着在阻焊层139上，且半导体裸片562的有源表面经由接合线668电连接到导电柱128上的表面处理层236。模塑料564遮盖半导体裸片562、接合线668、所述一或多个表面处理层236以及阻焊层139。
图16A、图16B、图16C、图16D、图16E、图16F、图16G、图16H、图16I、图16J、图16K和图16L说明根据本发明的实施例制造半导体封装的方法。
参看图16A，提供第一载体982。第一载体982具有第一表面984和与第一表面984相对的第二表面986。在一个实施例中，第一载体982包含双马来酰亚胺三嗪(BT)；然而，本发明并不限于此。导电膜988和晶种层990安置在第一表面984和第二表面986上。接着，光阻层992安置在晶种层990上。在一个实施例中，导电膜988为具有约18μm厚度的铜箔，晶种层990为具有约3μm厚度的铜箔，且光阻层992为层压干膜；然而，本发明并不限于此。
参看图16B，图案化光阻层992。图案化方法可包含曝光和显影，以便界定光阻层992中的图案开口994并暴露晶种层990。
参看图16C，第一图案化导电层118形成于从光阻层992的图案开口994暴露的晶种层990上。在一个实施例中，通过电镀形成第一图案化导电层118。在一个实施例中，第一图案化导电层118的厚度为约20μm，且第一图案化导电层118的材料为铜；然而，本发明并不限于此，且可使用(例如)其它金属或金属合金。在图16C的实施例中，第一图案化导电层118的导电迹线(例如，图1的第一导电迹线134)可经制造成细间距(例如，小于或等于15μm)。在此实施例中，第一图案化导电层118具有第一导电表面122和与第一导电表面122相对的第二导电表面124。第一导电表面122是在晶种层990处，且第二导电表面124由光阻层992暴露。
参看图16D，去除如图16C中所示的光阻层992。
参看图16E，电介质结构104经形成以遮盖晶种层990和第一图案化导电层118。在一些实施例中，电介质结构104为电介质层，其材料为包含基体树脂(例如，丙烯酸树脂或环氧树脂)和光引发剂的光敏树脂。在一些实施例中，光敏树脂为来自太阳油墨制造有限公司的CA-40 AUS320。电介质结构104具有第一电介质表面112和与第一电介质表面112相对的第二电介质表面114。第一导电表面122实质上与第一电介质表面112共面。
接着，预先固化电介质结构104。举例来说，光束施加到光敏树脂，使得通过将光引发剂与基体树脂反应而将光敏树脂部分地固化到B阶段状态。
参看图16F，电介质结构104经图案化以界定第二电介质表面114上的一或多个电介质开口116以暴露第二导电表面124的一部分。图案化可包含(例如)暴露并显影电介质结构104。电介质开口116是由侧壁130界定。
参看图16G，晶种层990与导电膜988分隔，使得两个衬底结构(上部衬底结构和下部衬底结构)与第一载体982分隔。
参看图16H，第二载体981经提供在第二电介质表面114上。在一些实施例中，第二载体981包括核心板983、第一金属层985和第二金属层987。在一个实施例中，核心板983包含双马来酰亚胺三嗪(BT)，且第一金属层985和第二金属层987为安置在核心板983两侧的铜箔。电介质结构104的第二电介质表面114附著或黏附到第一金属层985。
如上文所提，电介质结构104为当前在B阶段中的光敏树脂，使得电介质结构104可紧密地粘附到第二载体981。在一些实施例中，电介质结构104通过热按压而粘附到第二载体981，因此，光敏树脂经进一步热固化，使得光敏树脂发展到C阶段状态，并具有互穿聚合物网络(IPN)结构。界定电介质开口116的侧壁130归因于在第二载体981上按压的电介质结构104中的光敏树脂(在B阶段状态中)而弯曲(如针对图1A的实施例说明)：侧壁130的中间部分依靠压力挤压到电介质开口116中，且当固化到C阶段状态时保持所得曲状。
参看图16I，可完全或部分地去除如图16H中所示的晶种层990。在一个实施例中，通过快速蚀刻(Flash Etching)去除晶种层990。在此时刻之后，获得半导体衬底结构100A(图1)。第二载体981在后续囊封期间提高半导体衬底结构100A的刚性。在一个实施例中，在完全去除晶种层990之后，第一导电表面122可经进一步蚀刻，使得第一导电表面122从第一电介质表面112凹进，如针对图2的实施例所展示。
参看图16J，半导体裸片562安置在半导体衬底结构100A的第一衬底表面566(包含在此实施例中实质上彼此共面的第一电介质表面112和第一导电表面122)上，且电连接到接合垫131，以便电连接到导电结构106的第一导电表面122。在此实施例中，半导体裸片562包含在其有源表面上的一或多个UBM 578和安置在UBM 578的相应者上的一或多个导电柱580。半导体裸片562的导电柱580包含焊料539，且半导体裸片562经由焊料539电学上并物理上连接到半导体衬底结构100A的第一导电表面122。
参看图16K，模塑料564经施加以遮盖半导体裸片562和半导体衬底结构100A的第一衬底表面566。在此实施例中，模塑料564遮盖半导体裸片562、导电柱580、焊料539以及半导体衬底结构100A的第一衬底表面566的一部分。在此实施例中，导电柱580形成充分大空间，使得模塑料564可遮盖半导体裸片562的有源表面上的组件。因此，不需要昂贵的底部填充，借此减少制造成本。
参看图16L，去除第二载体981。在一些实施例中，电介质结构104与第一金属层985分隔，使得上部结构直接与第二载体981分隔。在其它实施例中，第一金属层985为包含外部金属层和内部金属层的双层结构，其中内部金属层安置于外部金属层与核心板983之间。电介质结构104粘附到外部金属层(图16H)。接着(图16L)，外部金属层通过剥离与内部金属层分隔，使得上部结构(包含外部金属层)与第二载体981分隔。接着(同样图16L)，通过蚀刻去除外部金属层。同时，用于外部金属层的蚀刻剂将进入电介质开口116以蚀刻球衬垫133的暴露表面以产生凹部132(如图3中)。
焊料凸块可安置在电介质结构104的电介质开口116中，以物理上并电学上连接到球衬垫133的相应者。焊料凸块可从电介质结构104的第二电介质表面114突出(例如，针对包含半导体衬底结构100A的半导体封装200A所展示，如图10中所示)。
图17A、图17B、图17C、图17D、图17E、图17F、图17G和图17H说明根据本发明的另一实施例的制造半导体封装的方法。此实施例的初始步骤与图16A到图16H相同，且以下步骤是在图16H之后。
参看图17A，光阻层992安置在晶种层990上。在一个实施例中，光阻层992为层压干膜；然而，本发明并不限于此。
参看图17B，光阻层992经图案化以界定多个开口994以暴露对应于接合垫131的晶种层990的一部分。图案化方法可包含(例如)暴露和显影光阻层992。接着，导电柱128形成于由开口994暴露的晶种层990上。导电柱128的材料可为(例如)铜或另一金属，或合金，其可通过电镀形成。
参看图17C，去除如图17B中所示的光阻层992。
参看图17D，可去除如图17C中所示的晶种层990。在一个实施例中，通过快速蚀刻去除晶种层990。由导电柱128遮盖的晶种层990的部分将不被完全蚀刻，且可变为导电柱128的一部分。在图17D中说明的实施例中，蚀刻晶种层990的一部分。这是因为晶种层990的晶格不同于导电柱128的晶格，并且，蚀刻剂中的晶种层990的蚀刻速率大于导电柱128的蚀刻速率。因此，大多数晶种层990被蚀刻，且导电柱128可充当用于在导电柱128下方的晶种层990的部分的遮罩。因此，在蚀刻之后，保持在导电柱128下方的晶种层990部分的宽度小于导电柱128的宽度，如图17D中所示。
参看图17E，阻焊层139形成于第一衬底表面566(包含在此实施例中实质上彼此共面的第一电介质表面112和第一导电表面122)上。阻焊层139界定一个或多个开口1391以暴露导电柱128。阻焊层139的材料可与电介质层110的材料相同或不同。
参看图17F，一或多个表面处理层236形成于导电柱128的相应者上。因为在相应导电柱128下方的晶种层990部分的宽度小于相应导电柱128的宽度，所以表面处理层236遮盖导电柱128的顶面和侧面以及导电柱128的底部表面的一部分，且进一步延伸到导电柱128与接合垫131之间的空间中。表面处理层236可通过电镀形成。表面处理层236中的每一者的材料可包含金、银或镍或其合金；然而，本发明并不限于此。在此时刻之后，获得半导体衬底结构100G(图7)，其连接到第二载体981。
参看图17G，半导体裸片562安置在半导体衬底结构100G的顶部表面上，且电连接到接合垫131，以便电连接到导电结构106的第一导电表面122。在此实施例中，半导体裸片562的背面粘着在阻焊层139上，且半导体裸片562的有源表面经由接合线668电连接到半导体衬底结构100G的导电柱128上的表面处理层236。
参看图17H，模塑料564经施加以遮盖半导体裸片562、接合线668、表面处理层236和阻焊层139。在线接合(图17G)和模制(图17H)之后，去除第二载体981。在一些实施例中，电介质结构104与第一金属层985分隔，使得上部结构与第二载体981分隔。焊料凸块可安置在电介质结构104的电介质开口116中，以物理上并电学上连接到球衬垫133的相应者，例如针对如图15中所示的半导体封装200F所展示。
如本文中所使用且不另外定义，术语“大致”、“实质上”和“约”用于描述并考虑较小变化。当与事件或情形结合使用时，所述术语可以是指其中事件或情形明确发生的情况以及其中事件或情形极近似于发生的情况。举例来说，所述术语可以是指小于或等于±10％，如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％。若两个表面之间的位移(例如)不大于1μm、不大于0.5μm或不大于0.2μm，则可认为这两个表面共面或实质上共面。
另外，有时在本文中按范围格式呈现量、比率及其它数值。应理解，此类范围格式是为了便利及简洁起见而使用，且应灵活地理解，不仅包含明确地指定为范围限制的数值，而且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值及子范围一般。
虽然已参考本发明的特定实施例描述并说明本发明，但这些描述和说明并不限制本发明。所属领域的技术人员应理解，在不脱离如所附权利要求书界定的本发明的真实精神及范围的情况下，可做出各种改变且可用等效物替代。所述图示可能未必按比例绘制。归因于制造工艺和公差，本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可做出修改，以使特定情况、材料、物质组成、方法或工艺适应于本发明的目标、精神及范围。所有此类修改都希望属于在此所附权利要求书的范围内。虽然本文揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序及分组并非本发明的限制。

Claims (20)

1.一种半导体衬底结构，其包括：
导电结构，其具有第一导电表面和与所述第一导电表面相对的第二导电表面，其中所述导电结构包括至少一个导电迹线；以及
电介质结构，其遮盖所述导电结构的至少一部分，并具有第一电介质表面和与所述第一电介质表面相对的第二电介质表面，其中所述第一导电表面并非从所述第一电介质表面突出，所述第二导电表面从所述第二电介质表面凹进，所述电介质结构为电介质层，所述电介质层包含固化光敏树脂或由其形成，且所述电介质结构界定在所述第二电介质表面中的电介质开口以暴露所述第二导电表面的一部分，其中界定所述电介质开口的侧壁为曲状的，所述电介质开口具有在所述第二电介质表面处的第一宽度和在所述电介质开口的中间部分处的第二宽度，所述第一宽度大于所述第二宽度，且所述电介质开口的所述侧壁的整体在横截面中具有连续的曲率。
2.根据权利要求1所述的半导体衬底结构，其中所述第一导电表面从所述第一电介质表面凹进。
3.根据权利要求1所述的半导体衬底结构，其中所述半导体衬底结构的厚度介于约20μm到约60μm的范围内。
4.根据权利要求1所述的半导体衬底结构，其中所述导电结构包含球衬垫和安置在所述球衬垫的第一表面上的金属凸块，且其中所述电介质开口暴露所述球衬垫的第二表面的一部分。
5.根据权利要求1所述的半导体衬底结构，其中所述导电结构进一步包含接合垫和安置在所述接合垫的表面上的导电柱。
6.根据权利要求5所述的半导体衬底结构，其中所述导电结构进一步包含晶种层和表面处理层，所述晶种层的一部分安置于所述导电柱与所述接合垫之间，所述晶种层部分的宽度小于所述导电柱的宽度，且所述表面处理层遮盖所述导电柱并延伸到所述导电柱与所述接合垫之间的空间中。
7.根据权利要求1所述的半导体衬底结构，其中所述导电结构进一步包含在其所述第二导电表面上的凹部。
8.根据权利要求1所述的半导体衬底结构，其中所述导电结构包含多个导电迹线，且所述导电迹线之间的间距小于或等于15μm。
9.根据权利要求1所述的半导体衬底结构，其中所述导电结构包含至少一个接合垫及至少一个球衬垫，且所述导电迹线连接所述接合垫与所述球衬垫。
10.根据权利要求1所述的半导体衬底结构，其中所述电介质开口具有在所述第二导电表面处的第三宽度，且所述第三宽度大于所述第二宽度。
11.一种半导体封装，其包括：
半导体衬底结构，其包括：
导电结构，其具有第一导电表面和与所述第一导电表面相对的第二导电表面；以及
电介质结构，其遮盖所述导电结构的至少一部分，并具有第一电介质表面和与所述第一电介质表面相对的第二电介质表面，其中所述第一导电表面并非从所述第一电介质表面突出，所述第二导电表面从所述第二电介质表面凹进，其中所述电介质结构包含固化光敏树脂或由其形成，且所述电介质结构界定在所述第二电介质表面中的电介质开口以暴露所述第二导电表面的一部分，其中界定所述电介质开口的侧壁为曲状的，所述电介质开口具有在所述第二电介质表面处的第一宽度和在所述电介质开口的中间部分处的第二宽度，所述第一宽度大于所述第二宽度，且所述电介质开口的所述侧壁的整体在横截面中具有连续的曲率；
半导体裸片，其电连接到所述第一导电表面；以及
模塑料，其遮盖所述半导体裸片和所述半导体衬底结构的一部分。
12.根据权利要求11所述的半导体封装，其中所述第一导电表面从所述第一电介质表面凹进。
13.根据权利要求11所述的半导体封装，其中所述半导体衬底结构的厚度是介于约20μm到约60μm范围内。
14.根据权利要求11所述的半导体封装，其中所述导电结构进一步具有球衬垫和安置在所述球衬垫的第一表面上的第一金属凸块，且所述电介质开口暴露所述球衬垫的第二表面的一部分。
15.根据权利要求11所述的半导体封装，其中所述导电结构进一步具有接合垫和安置在所述接合垫的第一表面上的导电柱。
16.根据权利要求15所述的半导体封装，其中所述导电结构进一步具有晶种层和表面处理层，所述晶种层的一部分安置于所述导电柱与所述接合垫之间，所述晶种层部分的宽度小于所述导电柱的宽度，且所述表面处理层遮盖所述导电柱并延伸到所述导电柱与所述接合垫之间的空间中。
17.根据权利要求11所述的半导体封装，其中所述导电结构进一步包含在其所述第二导电表面上的凹部。
18.一种半导体衬底结构，其包括：
图案化导电层，其具有第一导电表面和与所述第一导电表面相对的第二导电表面，其中所述图案化导电层包括至少一个导电迹线；以及电介质层，其遮盖所述图案化导电层的至少一部分，并具有第一电介质表面和与所述第一电介质表面相对的第二电介质表面，其中所述第一导电表面并非从所述第一电介质表面突出，所述第二导电表面从所述第二电介质表面凹进，其中所述电介质层为电介质层，所述电介质层包含固化光敏树脂或由其形成，所述电介质层界定在所述第二电介质表面中的电介质开口以暴露所述第二导电表面的一部分，所述电介质开口的侧壁的整体在横截面中具有连续的曲率，所述电介质开口具有在所述第二电介质表面处的第一宽度、在所述电介质开口的中间部分处的第二宽度和在所述第二导电表面处的第三宽度，所述第一宽度大于所述第二宽度，且所述第三宽度大于所述第二宽度。
19.根据权利要求18所述的半导体衬底结构，其中所述第一宽度与所述第二宽度的比率至少为1.1。
20.根据权利要求18所述的半导体衬底结构，其中所述第一导电表面实质上与所述第一电介质表面共面。
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