CN106158773B - 具有嵌入组件的半导体封装及其制造方法 - Google Patents

具有嵌入组件的半导体封装及其制造方法 Download PDF

Info

Publication number
CN106158773B
CN106158773B CN201510145566.8A CN201510145566A CN106158773B CN 106158773 B CN106158773 B CN 106158773B CN 201510145566 A CN201510145566 A CN 201510145566A CN 106158773 B CN106158773 B CN 106158773B
Authority
CN
China
Prior art keywords
layer
encapsulated
patterned conductive
semiconductor packages
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201510145566.8A
Other languages
English (en)
Other versions
CN106158773A (zh
Inventor
施佑霖
李志成
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Publication of CN106158773A publication Critical patent/CN106158773A/zh
Application granted granted Critical
Publication of CN106158773B publication Critical patent/CN106158773B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

本发明涉及半导体封装及其制作方法。所述半导体封装包含囊封层、电介质层、组件和第一经图案化导电层。所述囊封层具有第一表面。所述组件在所述囊封层内且具有前表面和所述前表面上的多个衬垫。所述电介质层在所述囊封层的所述第一表面上，且界定多个通孔；其中所述组件的所述多个衬垫抵靠所述电介质层；且其中所述电介质层具有与所述囊封层的所述第一表面相对的第二表面。多个通孔中的每一者从所述电介质层的所述第二表面延伸到所述多个所述衬垫中的相应一者。所述第一经图案化导电层在所述电介质层内且包围所述通孔。

Description

具有嵌入组件的半导体封装及其制造方法
技术领域
本发明涉及半导体封装及其制造方法，且更具体地说涉及具有嵌入组件的半导体封装及其制造方法。
背景技术
在至少部分地由针对较小尺寸和增强的处理速度的需求的驱动下，半导体装置变得越来越复杂。同时，存在使包含这些半导体装置的许多电子产品进一步小型化的需求。半导体装置通常经封装，且随后可安装在包含电路的衬底上，例如电路板。这导致由半导体装置封装和衬底两者占据空间，且导致半导体装置封装占据衬底上的表面积。另外，作为单独的过程执行封装、板制造和装备可引起成本。所希望的是减少衬底上由半导体装置占据的空间，且简化并组合应用于半导体装置和衬底的封装、板制造和装配过程。
发明内容
根据本发明的实施例，一种半导体封装包含囊封层、电介质层、组件和第一经图案化导电层。所述囊封层具有第一表面。所述组件在所述囊封层内且具有前表面且包括所述前表面上的多个衬垫。所述电介质层在所述囊封层的所述第一表面上，且界定多个通孔；其中所述组件的所述多个衬垫抵靠所述电介质层；且其中所述电介质层具有与所述囊封层的所述第一表面相对的第二表面。多个通孔中的每一者从所述电介质层的所述第二表面延伸到所述多个所述衬垫中的相应一者。所述第一经图案化导电层在所述电介质层内且包围所述通孔。
根据本发明的另一实施例，一种半导体封装包含裸片、囊封层、第一电介质层、多个导电部件和经图案化导电层。所述裸片包括裸片主体和多个衬垫，所述裸片主体具有其上安置所述多个衬垫的前表面。所述囊封层囊封上表面，所述囊封层掩埋所述裸片主体且从所述囊封层的上表面暴露所述裸片主体的前表面。所述第一电介质层安置在所述囊封层的上表面上且覆盖所述多个衬垫。所述多个导电部件穿透所述第一电介质层。所述经图案化导电层嵌入所述第一电介质层中且通过所述导电部件电连接到所述衬垫。
根据本发明的实施例，一种制作半导体封装的方法包含：(a)形成第一经图案化导电层；(b)形成囊封所述第一经图案化导电层的电介质粘合层；(c)将包括多个衬垫的裸片附接到所述电介质粘合层；(d)形成囊封所述裸片的囊封层；以及(e)在所述电介质粘合层中形成电连接到所述多个衬垫的多个导电通孔。
附图说明
图1图解说明根据本发明的实施例的半导体封装的横截面图；
图2A、图2B、图2C、图2D、图2E、图2F、图2G、图2H、图2I、图2J、图2K和图2L图解说明根据本发明的实施例的制造方法；
图3图解说明根据本发明的另一实施例的半导体封装的横截面图；以及
图4图解说明根据本发明的另一实施例的半导体封装的横截面图。
贯穿图式及详细描述使用共同参考数字以指示相同或类似元件。从以下结合附图做出的详细描述，本发明将是显而易见的。
具体实施方式
已经提出具有嵌入的半导体装置的各种衬底，所谓的芯片嵌入衬底，其中半导体装置或芯片首先埋入衬底中且随后在后续过程中制造重新路由结构。重新路由结构可包含再分布层(RDL)和从RDL延伸且在厚支撑层的表面处作为接触结构终止的互连件(例如，导电柱)，用于下一层级封装结构。RDL可由形成于嵌入半导体装置上方的钝化层支撑。聚合层沉积在RDL上方，且经蚀刻或钻孔以提供通孔以用于以金属包覆填充从而形成在所述通孔的开口上方延伸且超出所述开口的互连件(即，导电柱)。附接到所述柱的突出末端的焊料凸块是通过无电电镀、丝网或模板印刷形成。
因为钝化层的顶表面由于延伸超出半导体装置的表面的嵌入半导体装置的衬垫而是不光滑的，所以高分辨率光刻并不有效形成所述通孔和RDL。因此，RDL的间距受限。此外，不能形成RDL可导致封装衬底的损耗，包含埋入封装衬底中的相对高成本半导体装置。
本文所描述的是半导体封装及其制作方法，其中可使用高分辨率技术来减少通孔宽度，减少衬垫间距，改善产量，且减少制造成本。
图1图解说明根据本发明的实施例的半导体封装的横截面图。所述半导体封装1包含囊封层14、电介质层12、裸片13(或其它组件)、经图案化导电层11、经图案化导电层15、经图案化导电层16、焊料光致抗蚀剂层17和多个电连接元件18。
囊封层14包含表面141。囊封层14可包含但不限于模制化合物或预先浸渍复合纤维(例如，预先浸渍物)。模制化合物的实例可包含(但不限于)具有分散于其中的填充剂的环氧树脂。预先浸渍物的实例可包含(但不限于)通过堆叠或层压许多预先浸渍材料/片形成的多层结构。
裸片13可为但不限于形成于硅衬底上或硅衬底中的集成电路(IC)。裸片13包含裸片主体13a、前表面132和安置在前表面132上的多个衬垫131。裸片主体13a埋入或囊封在囊封层14中，且前表面132和衬垫131从囊封层14的表面141暴露以使得前表面132可与囊封层14的表面141共面。电介质层12安置在囊封层14的表面141上以及裸片13的前表面132和衬垫131上。裸片13夹在囊封层14与电介质层12之间以使得所述多个衬垫131埋入或囊封在电介质层12中。在另一实施例中，可存在衬垫131上的钝化层，且衬垫131不埋入电介质层12。电介质层12包含多个通孔12O和与表面141相对的表面121。所述多个通孔12O从表面121形成到电介质层12中。电介质层12可包含疏水性材料。电介质层12可为粘合剂以提供裸片13与电介质层12之间的接合以及囊封层14与电介质层12之间的接合。因此，电介质层12直接接触裸片13的前表面132和衬垫131。电介质层12还直接接触囊封层14的表面141。
经图案化导电层11嵌入在电介质层12中。经图案化导电层11可为但不限于再分布层(RDL)。经图案化导电层11邻近于电介质层12的表面121。经图案化导电层11包含与电介质层12的表面121共面的表面11a。经图案化导电层11可包含但不限于铜(Cu)。因为经图案化导电层11嵌入在电介质层12中，所以可实现近似2μm的最小线宽度和近似2μm的最小线到线空间(间距)。
经图案化导电层11的一部分111包围通孔12O。经图案化导电层11的部分111可具有环状轮廓，其具有对准到通孔12O的开口。经图案化导电层11的部分111可紧紧地且侧向地包围通孔12O中的每一者。经图案化导电层11的部分111与多个衬垫131之间的电介质层12侧向地包围通孔12O中的每一者。经图案化导电层11的部分111和电介质层12的一部分形成通孔12O中的每一者的侧壁。多个衬垫131中的每一者形成通孔12O的底部。通孔12O可具有较小直径且可接近地定位在一起。举例来说，通孔12O可具有等于或小于大约70μm的宽度，且衬垫131之间的对应间距可等于或小于大约150μm。对于另一实例，通孔12O可具有等于或小于大约15μm的宽度，且衬垫131之间的对应间距可等于或小于大约40μm。通孔12O的宽度可为其它值，例如等于或小于例如大约60μm、55μm、50μm、45μm、40μm、35μm、30μm、25μm或20μm。衬垫131之间的间距也可为其它值，例如等于或小于例如大约140μm、130μm、120μm、110μm、100μm、90μm、80μm、70μm、60μm和50μm。
经图案化导电层15连续地且保形地形成于电介质层12的表面121上，且形成于通孔12O中的每一者的侧壁和底部上。经图案化导电层15可为但不限于晶种层，其可包含(例如)无电沉积铜层或钛铜(TiCu)层或其它金属或金属合金层。经图案化导电层15可安置在经图案化导电层11的部分111之上。经图案化导电层15接触通孔12O中的每一者的底部，换句话说，经图案化导电层15接触多个衬垫131中的每一者。
经图案化导电层16安置在经图案化导电层15上，进而形成导体，包含通孔12O中的导电通孔16a且进一步包含延伸超出电介质层12的表面121的额外部分16b(例如经图案化导电层16的部分16b形成在电介质层12的表面121上方或从其突出)。所述导体的导电通孔16a和额外部分16b可一体地形成。经图案化导电层16可包含除所描述导体外的结构。经图案化导电层16可包含电镀铜层。经图案化导电层15和经图案化导电层16的导体(即，导电部分16a和额外部分16b)一起形成穿过电介质层12且电连接经图案化导电层11和衬垫131的导电部件。
例如焊料光致抗蚀剂层等第二电介质层17安置在电介质层12上。第二电介质层17覆盖电介质层12、经图案化导电层11和经图案化导电层16。第二电介质层17包含许多开口17O以暴露经图案化导电层11的一部分112。
所述多个电连接元件18中的每一者安置在形成于第二电介质层17中的开口17O中的一者中。电连接元件18可包含(但不限于)焊料凸块或焊料球。电连接元件18中的每一者接触经图案化导电层11的相应部分112。
图2A、图2B、图2C、图2D、图2E、图2F、图2G、图2H、图2I、图2J、图2K和图2L图解说明根据本发明的实施例的制造方法。
参考图2A，提供载体30和金属层31。载体30可选自(但不限于)硅、塑料或金属面板。载体30可促进其上的后续过程。
金属层31可为(但不限于)相对薄铜片或铜箔。金属层31可(例如)为近似2μm厚度。
图2B是说明形成于金属层31上的经图案化导电层11的俯视图。图2C是从图2B中所示的线AA'取得的横截面图。参考图2C，经图案化导电层11可(例如)通过光刻或电镀技术形成。经图案化导电层11可为但不限于相对平坦且平滑的再分布层(RDL)。经图案化导电层11可包含但不限于铜或另一金属或合金。经图案化导电层11可包含促进后续过程中的通孔形成的部分111。经图案化导电层11的部分111可具有环状轮廓，其具有开口以界定后续过程中的通孔的形状和位置。如果在经图案化导电层11形成之后，通过自动光学检查(AOI)或其它检查技术识别经图案化导电层11中的缺陷，那么针对具有缺陷的特定装置不执行进一步过程(例如裸片附接)以节省制造成本。因此，总产量比率升高。
参考图2D，电介质粘合层12形成于金属层31上以掩埋或覆盖经图案化导电层11。电介质粘合层12可(例如)通过将电介质粘合材料层压到经图案化导电层11而形成。
图2E是说明包括多个裸片衬垫131的裸片13的俯视图，其中裸片13和裸片衬垫131接合到电介质粘合层12。图2F是从图2E中所示的线BB'取得的横截面图。参考图2F，裸片13可(例如)通过裸片接合设备放置或按压到电介质粘合层12上。裸片接合设备可将裸片13附接到电介质粘合层12以使得衬垫131埋入电介质粘合层12中。电介质层12可固定裸片13且提供与经图案化导电层11的充分电绝缘。举例来说，电介质层12可具有从近似5μm到近似30μm的厚度以提供充分电绝缘；然而在其它实施例中电介质层12的厚度可在另一范围内。
电介质粘合层12可在裸片13的接合过程之后加热或固化。经加热电介质粘合层12变成固化或硬化的，并且因此可提供衬垫131与电介质粘合层12之间的接合以及裸片13的前表面132与电介质粘合层12之间的接合。
参考图2G，囊封层14形成在电介质粘合层12上以囊封裸片13。用于形成囊封层14的技术可为但不限于模制技术，其在模制模具(未图示)的帮助下使用模制化合物来囊封裸片13。在本发明的另一个实施例中，由预先浸渍复合纤维(预先浸渍物)制成的薄片可堆叠或层压到电介质粘合层12和裸片13以形成囊封层14。
参考图2H，使金属层31、经图案化导电层11、电介质粘合层12、裸片13和囊封层14与载体30分离，且随后移除金属层31。换句话说，例如通过机械地移除载体30而从金属层31和形成于其上的结构移除载体30。在载体30的移除之后，例如通过使用蚀刻技术移除金属层31。
参考图2I，许多通孔12O形成于电介质粘合层12中以暴露裸片13的衬垫131。经图案化导电层11的部分111的环状轮廓可为掩模以促进通孔12O的形成。举例来说，经图案化导电层11的部分111的内轮缘可帮助激光钻孔设备精确地移除由此包围的电介质粘合层12。
参考图2J，经图案化导电层15连续地且保形地形成于电介质粘合层12的表面121上，且沿着通孔12O中的每一者的侧壁和底部形成。经图案化导电层15可由(例如)溅镀技术形成。经图案化导电层15可为但不限于可由(例如)TiCu制成的晶种层15。图案化掩模15M可通过经图案化导电层15上的光刻技术形成。掩模15M暴露经图案化导电层15的部分。
参考图2K，经图案化导电层16可形成于经图案化导电层15的暴露部分上，且随后移除经图案化掩模15M。经图案化导电层16包含形成于通孔12O中和覆盖经图案化导电层11的部分111的晶种层15上的导体。经图案化导电层16可(例如)通过电镀技术形成。可在经图案化导电层16的形成之后移除经图案化掩模15M和晶种层15的部分。
参考图2L，例如焊料光致抗蚀剂层等第二电介质层17可形成于电介质粘合层12上。第二电介质层17可经涂布或层压在电介质粘合层12上。可形成许多开口17O以暴露经图案化导电层11的一部分112。
在开口17O中可形成多个电连接元件18(图2L中未图示)以形成如图1所示的半导体封装结构1。电连接元件18可包含(但不限于)焊料凸块或焊料球。电连接元件18可通过焊料凸块/球植入而形成。
图3图解说明根据本发明的另一实施例的半导体封装结构的横截面图。半导体封装结构3可类似于参考图1所描述且图解说明的半导体封装结构1，不同的是经图案化导电层15的部分151和经图案化导电层16的部分161可形成于经图案化导电层11的相应部分112上。经图案化导电层15的部分151和经图案化导电层16的部分161可安置在开口17O中。在此实施例中，电连接元件18中的每一者覆盖经图案化导电层15的相应部分151和经图案化导电层16的相应部分161。经图案化导电层15的部分151和经图案化导电层16的部分161可增强电连接元件18的导电性。
F1G 4图解说明根据本发明的另一实施例的半导体封装结构的横截面图。半导体封装结构4可类似于参考图3所描述且图解说明的半导体封装结构3，不同的是经图案化导电层15的部分152和经图案化导电层16的部分162可安置在经图案化导电层11上。与参考图3图解说明且描述的半导体封装结构3相比，经图案化导电层15的部分152和经图案化导电层16的部分162可提供电流可通过其传递到经图案化导电层11的较大导电区域。因此，经图案化导电层11的导电性增强。在电镀经图案化导电层16的操作期间，如果待电镀图案具有相对较小电镀区域，那么可能不容易形成均匀的层。经图案化导电层15的部分152和经图案化导电层16的部分162也可改善电镀经图案化导电层16的操作的质量(如图2J和图2K中所示)，因为其电镀区域增加或放大。
如本文中所使用，术语“大体上”、“实质的”、“近似”及“大约”用以描述及考虑小变化。当与事件或情形结合使用时，所述术语可以指其中事件或情形明确发生的情况以及其中事件或情形极接近于发生的情况。举例来说，所述术语可以指小于或等于±10％，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％。
另外，有时在本文中按范围格式呈现量、比率及其它数值。应理解，此类范围格式是用于便利及简洁起见，且应灵活地理解，不仅包含明确地指定为范围限制的数值，而且包含涵盖于所述范围内的所有个别数值或子范围，如同明确地指定每一数值及子范围一般。
在一些实施例中，如果两个表面之间的移位较小，例如不大于1μm、不大于5μm或不大于10μm，那么所述两个表面可视为共面或大体上共面的。
虽然已参考本发明的特定实施例描述及说明本发明，但这些描述及说明并不限制本发明。所属领域的技术人员应理解，在不脱离如所附权利要求书界定的本发明的真实精神及范围的情况下，可做出各种改变且可取代等效物。所述说明可能未必按比例绘制。归因于制造工艺及公差，本发明中的艺术再现与实际设备之间可存在区别。可存在并未特定说明的本发明的其它实施例。应将本说明书及图式视为说明性的而非限制性的。可做出修改，以使特定情况、材料、物质组成、方法或工艺适应于本发明的目标、精神及范围。所有所述修改都打算属于在此所附权利要求书的范围内。虽然本文揭示的方法已参考按特定次序执行的特定操作加以描述，但应理解，可在不脱离本发明的教示的情况下组合、细分或重新排序这些操作以形成等效方法。因此，除非本文中特别指示，否则操作的次序及分组并非本发明的限制。

Claims (18)

1.一种半导体封装，其包括：
囊封层，其具有第一表面，所述囊封层包括第一材料；
所述囊封层内的组件，所述组件具有前表面且包括所述前表面上的多个衬垫；
所述囊封层的所述第一表面上的电介质层，所述电介质层包括第二材料，且所述电介质层界定多个通孔；其中所述第一材料不同于所述第二材料；其中所述组件的所述多个衬垫抵靠所述电介质层；且其中所述电介质层具有与所述囊封层的所述第一表面相对的第二表面，且所述多个通孔中的每一者从所述电介质层的所述第二表面延伸到所述多个衬垫中的相应一者；以及
第一经图案化导电层，其嵌入在所述电介质层的所述第二表面且包围所述通孔。
2.根据权利要求1所述的半导体封装，其中所述第一经图案化导电层具有与所述电介质层的所述第二表面共面的第三表面。
3.根据权利要求1所述的半导体封装，其中所述囊封层覆盖所述组件的侧表面和底部表面。
4.根据权利要求1所述的半导体封装，其中所述第一经图案化导电层的第一部分和所述电介质层的一部分形成所述通孔中的每一者的侧壁，其中所述多个衬垫中的每一者形成对应通孔的底部。
5.根据权利要求4所述的半导体封装，其进一步包括连续地且保形地形成于所述电介质层的所述第二表面上以及所述通孔的所述侧壁和所述底部上的第二经图案化导电层。
6.根据权利要求5所述的半导体封装，其进一步包括安置在所述第二经图案化导电层上的第三经图案化导电层。
7.根据权利要求6所述的半导体封装，其中所述第三经图案化导电层延伸超出所述电介质层的所述第二表面。
8.根据权利要求1所述的半导体封装，其中所述组件的所述前表面与所述囊封层的所述第一表面共面。
9.根据权利要求1所述的半导体封装，其中所述第一经图案化导电层界定开口，每一开口与相应的通孔对准以使所述第一经图案化导电层围绕所述相应的通孔。
10.一种半导体封装，其包括：
裸片，其包括裸片主体和多个衬垫，所述裸片主体具有其上安置所述多个衬垫的前表面；
囊封层，其具有上表面，所述囊封层囊封所述裸片主体同时从所述囊封层的所述上表面暴露所述裸片主体的所述前表面，所述囊封层包括第一材料；
第一电介质层，其安置在所述囊封层的所述上表面上且覆盖所述多个衬垫，所述第一电介质层包括不同于所述第一材料的第二材料；其中所述第一电介质层具有与所述囊封层的所述上表面相对的上表面；
多个导电部件，其穿透所述第一电介质层，以及
经图案化导电层，其嵌入所述第一电介质层的所述上表面且通过所述导电部件电连接到所述衬垫。
11.根据权利要求10所述的半导体封装，其中所述经图案化导电层的上表面与所述第一电介质层的所述上表面共面。
12.根据权利要求10所述的半导体封装，其中所述经图案化导电层包含多个环，每一环界定导电部件的外围。
13.根据权利要求12所述的半导体封装，其中所述导电部件中的每一者直接连接所述环中的各自一者和所述衬垫中的各自一者。
14.根据权利要求13所述的半导体封装，其中所述导电部件包含直接连接所述环和所述衬垫的无电沉积铜层。
15.根据权利要求12所述的半导体封装，其中所述导电部件包含无电沉积铜层和电镀铜层。
16.根据权利要求10所述的半导体封装，其进一步包括覆盖所述第一电介质层且暴露所述经图案化导电层的一部分的第二电介质层。
17.根据权利要求16所述的半导体封装，其进一步包括位于所述经图案化导电层的暴露部分上的第二经图案化导电层。
18.一种半导体封装，其包括：
裸片，其包括裸片主体和多个衬垫，所述裸片主体具有其上安置所述多个衬垫的前表面；
囊封层，其具有上表面，所述囊封层囊封所述裸片主体同时从所述囊封层的所述上表面暴露所述裸片主体的所述前表面；
第一电介质层，其安置在所述囊封层的所述上表面上且覆盖所述多个衬垫；
多个导电部件，其穿透所述第一电介质层，以及
经图案化导电层，其嵌入所述第一电介质层且通过所述导电部件电连接到所述衬垫，
其中所述经图案化导电层包括多个环，每一环围绕相应的导电部件的外围；且其中所述导电部件中的每一者直接连接所述环中的各自一者和所述衬垫中的各自一者。
CN201510145566.8A 2014-11-07 2015-03-31 具有嵌入组件的半导体封装及其制造方法 Active CN106158773B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/536,253 US9721799B2 (en) 2014-11-07 2014-11-07 Semiconductor package with reduced via hole width and reduced pad patch and manufacturing method thereof
US14/536,253 2014-11-07

Publications (2)

Publication Number Publication Date
CN106158773A CN106158773A (zh) 2016-11-23
CN106158773B true CN106158773B (zh) 2018-12-14

Family

ID=55912831

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201510145566.8A Active CN106158773B (zh) 2014-11-07 2015-03-31 具有嵌入组件的半导体封装及其制造方法

Country Status (2)

Country Link
US (1) US9721799B2 (zh)
CN (1) CN106158773B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20170047276A1 (en) * 2015-08-13 2017-02-16 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US9870997B2 (en) * 2016-05-24 2018-01-16 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same
US11014806B2 (en) * 2017-05-18 2021-05-25 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
US10418314B2 (en) * 2017-11-01 2019-09-17 Advanced Semiconductor Engineering, Inc. External connection pad for semiconductor device package
US11004779B2 (en) 2018-02-09 2021-05-11 Advanced Semiconductor Engineering, Inc. Semiconductor device package and a method of manufacturing the same
CN110642220A (zh) * 2018-06-27 2020-01-03 日月光半导体制造股份有限公司 半导体装置封装和其制造方法
US10755994B2 (en) * 2018-10-29 2020-08-25 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor substrate
US10811365B2 (en) 2018-12-28 2020-10-20 Micron Technology, Inc. Semiconductor devices having crack-inhibiting structures
US10784212B2 (en) 2018-12-28 2020-09-22 Micron Technology, Inc. Semiconductor devices having crack-inhibiting structures
CN110164839B (zh) * 2019-05-27 2020-01-31 广东工业大学 一种高密度线路嵌入转移的扇出型封装结构与方法

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1640216A (zh) * 2002-02-22 2005-07-13 株式会社藤仓 多层线路基板、多层线路基板用基材、印刷线路基板及其制造方法
CN101542507A (zh) * 2006-10-20 2009-09-23 桑迪士克股份有限公司 便携式存储器装置及其方法
CN102099911A (zh) * 2008-07-17 2011-06-15 飞兆半导体公司 使用预模制载体的嵌入式裸片封装及工艺流程
CN102214624A (zh) * 2011-05-17 2011-10-12 北京大学 一种具有通孔的半导体结构及其制造方法
CN103021982A (zh) * 2011-09-23 2013-04-03 德州仪器公司 集成电路及制造方法
CN103247600A (zh) * 2012-02-02 2013-08-14 三星电子株式会社 通孔连接结构、具有该结构的半导体器件及其制造方法
CN103730427A (zh) * 2012-10-11 2014-04-16 德州仪器公司 囊封用于集成电路的封装
CN103918074A (zh) * 2011-11-22 2014-07-09 德州仪器公司 微型表面安装装置封装

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5250843A (en) 1991-03-27 1993-10-05 Integrated System Assemblies Corp. Multichip integrated circuit modules
KR20010061784A (ko) 1999-12-29 2001-07-07 박종섭 칩 스캐일 패키지 및 그의 제조 방법
KR100890534B1 (ko) 2000-02-25 2009-03-27 이비덴 가부시키가이샤 다층프린트배선판 및 다층프린트배선판의 제조방법
US6423570B1 (en) 2000-10-18 2002-07-23 Intel Corporation Method to protect an encapsulated die package during back grinding with a solder metallization layer and devices formed thereby
JP3492348B2 (ja) 2001-12-26 2004-02-03 新光電気工業株式会社 半導体装置用パッケージの製造方法
US6680529B2 (en) 2002-02-15 2004-01-20 Advanced Semiconductor Engineering, Inc. Semiconductor build-up package
US6701614B2 (en) * 2002-02-15 2004-03-09 Advanced Semiconductor Engineering Inc. Method for making a build-up package of a semiconductor
TW563233B (en) * 2002-09-11 2003-11-21 Advanced Semiconductor Eng Process and structure for semiconductor package
JP4489411B2 (ja) 2003-01-23 2010-06-23 新光電気工業株式会社 電子部品実装構造の製造方法
FI115601B (fi) 2003-04-01 2005-05-31 Imbera Electronics Oy Menetelmä elektroniikkamoduulin valmistamiseksi ja elektroniikkamoduuli
US6873040B2 (en) * 2003-07-08 2005-03-29 Texas Instruments Incorporated Semiconductor packages for enhanced number of terminals, speed and power performance
US20080150159A1 (en) * 2004-02-11 2008-06-26 Irwin Aberin Semiconductor Package with Perforated Substrate
TWI244186B (en) * 2005-03-02 2005-11-21 Advanced Semiconductor Eng Semiconductor package and method for manufacturing the same
JP4016039B2 (ja) 2005-06-02 2007-12-05 新光電気工業株式会社 配線基板および配線基板の製造方法
US7667338B2 (en) 2006-08-08 2010-02-23 Lin Paul T Package with solder-filled via holes in molding layers
US7651889B2 (en) 2007-09-13 2010-01-26 Freescale Semiconductor, Inc. Electromagnetic shield formation for integrated circuit die package
JP5395360B2 (ja) 2008-02-25 2014-01-22 新光電気工業株式会社 電子部品内蔵基板の製造方法
US8466553B2 (en) * 2010-10-12 2013-06-18 Advanced Semiconductor Engineering, Inc. Semiconductor device and semiconductor package having the same
US9385009B2 (en) * 2011-09-23 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming stacked vias within interconnect structure for Fo-WLCSP
US9070692B2 (en) * 2013-01-12 2015-06-30 Avalanche Technology, Inc. Shields for magnetic memory chip packages

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1640216A (zh) * 2002-02-22 2005-07-13 株式会社藤仓 多层线路基板、多层线路基板用基材、印刷线路基板及其制造方法
CN101542507A (zh) * 2006-10-20 2009-09-23 桑迪士克股份有限公司 便携式存储器装置及其方法
CN102099911A (zh) * 2008-07-17 2011-06-15 飞兆半导体公司 使用预模制载体的嵌入式裸片封装及工艺流程
CN102214624A (zh) * 2011-05-17 2011-10-12 北京大学 一种具有通孔的半导体结构及其制造方法
CN103021982A (zh) * 2011-09-23 2013-04-03 德州仪器公司 集成电路及制造方法
CN103918074A (zh) * 2011-11-22 2014-07-09 德州仪器公司 微型表面安装装置封装
CN103247600A (zh) * 2012-02-02 2013-08-14 三星电子株式会社 通孔连接结构、具有该结构的半导体器件及其制造方法
CN103730427A (zh) * 2012-10-11 2014-04-16 德州仪器公司 囊封用于集成电路的封装

Also Published As

Publication number Publication date
US20160133537A1 (en) 2016-05-12
CN106158773A (zh) 2016-11-23
US9721799B2 (en) 2017-08-01

Similar Documents

Publication Publication Date Title
CN106158773B (zh) 具有嵌入组件的半导体封装及其制造方法
US10079156B2 (en) Semiconductor package including dielectric layers defining via holes extending to component pads
CN106158814B (zh) 具有包埋无源组件的电路板和其制造方法
US20130256884A1 (en) Grid fan-out wafer level package and methods of manufacturing a grid fan-out wafer level package
CN106158774B (zh) 半导体封装结构及其制造方法
US10049950B2 (en) Multi-layer substrate for semiconductor packaging
CN108962876A (zh) Pop结构及其形成方法
US9462704B1 (en) Extended landing pad substrate package structure and method
CN106158815A (zh) 半导体衬底结构、半导体封装及其制造方法
US11462455B2 (en) Semiconductor package device and method of manufacturing the same
US11145621B2 (en) Semiconductor package device and method of manufacturing the same
CN101567355B (zh) 半导体封装基板及其制法
TWI671864B (zh) 半導體封裝基板及其製造方法
CN109712941A (zh) 衬底结构、包含衬底结构的半导体封装结构，以及制造半导体封装结构的半导体工艺
US10334728B2 (en) Reduced-dimension via-land structure and method of making the same
CN102136459B (zh) 封装结构及其制法
CN108172561B (zh) 承载基板与其封装结构，及半导体封装元件的制作方法
US8686568B2 (en) Semiconductor package substrates having layered circuit segments, and related methods
CN105990307B (zh) 封装基板及包含该封装基板的封装结构及其制作方法
CN104409365B (zh) 一种bga基板的制作方法
KR102141102B1 (ko) 반도체 패키지 기판 제조방법 및 이를 이용하여 제조된 반도체 패키지 기판
CN110943051A (zh) 半导体封装装置和其制造方法
US20180063951A1 (en) Printed circuit board (pcb) and pcb assembly having an encapsulating mold material on a bottom surface thereof and methods for molding an encapsulating mold material on a bottom surface of a pcb
CN107527824B (zh) 具有散热片的封装载板及其制备方法
KR101865873B1 (ko) 반도체 패키지 기판의 제조 방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant