CN106097683A - Distribution electric quantity parameter acquisition system - Google Patents
Distribution electric quantity parameter acquisition system Download PDFInfo
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- CN106097683A CN106097683A CN201610447962.0A CN201610447962A CN106097683A CN 106097683 A CN106097683 A CN 106097683A CN 201610447962 A CN201610447962 A CN 201610447962A CN 106097683 A CN106097683 A CN 106097683A
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C17/00—Arrangements for transmitting signals characterised by the use of a wireless electrical link
- G08C17/02—Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C19/00—Electric signal transmission systems
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- Computer Networks & Wireless Communication (AREA)
- Remote Monitoring And Control Of Power-Distribution Networks (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
The invention relates to a power distribution electric quantity parameter acquisition system which comprises a plurality of electric quantity monitoring meters and a main controller, wherein each power distribution line and main electric equipment are respectively provided with one electric quantity monitoring meter, the electric quantity monitoring meters monitor the operation real-time parameters of the power distribution lines, the electric quantity data acquired by the electric quantity monitoring meters are transmitted to the main controller for processing through power line communication, and the main controller is connected with a dispatching room through a GSM network.
Description
(1) technical field:
The present invention relates to a kind of distribution electrical parameter acquisition system, comprise multiple stage electric quantity monitoring instrument and a main controller,
Every distribution line and primary electricity using device all configure an electric quantity monitoring instrument, the fortune of electric quantity monitoring instrument monitoring distribution line
Row real-time parameter, the electric quantity data gathered by power line communication send to main controller process, main controller by GSM net with
Control room contacts.
(2) background technology:
Thered is provided the control system of power supply by power network, its each electronic equipment or intermodule are all to be communicated by special circuit,
Correct the timing time of each electronic equipment or electronic module, reach to run simultaneously purpose.Owing to using special circuit communication to make
Wiring complicates and increases cost, if timing time is not corrected by line traffic, then due to tradition timing error, runs number
After hour, its accumulation timing error can make system control action inconsistent, is likely to result in system crash, often changes at some and sets
Meter, its products application of occasion that wiring installation amount is big is restricted.
(3) summary of the invention:
When needing the electrical parameter measuring each bar distribution line it is necessary to gather distribution electrical parameter, it is used for optimizing distribution
System, the reasonable arrangement equipment operation time.The present invention relates to a kind of distribution electrical parameter acquisition system, comprise multiple stage electric quantity monitoring
Instrument and a main controller, every distribution line and primary electricity using device all configure an electric quantity monitoring instrument, every electricity prison
Surveying instrument and comprise one or several voltage transformer summation current transformer, the operation of electric quantity monitoring instrument monitoring distribution line is real-time
Parameter, mainly has: circuit three-phase voltage, three-phase current, active power, reactive power, power factor, by electric quantity monitoring instrument
ADC carries out synchronized sampling, can realize the voltage of homophase, current synchronization sampling, and sampled signal carries out conditioning conversion, then by it
The electric quantity data gathered sends main controller to by electric lines of force half wave communication and processes, and main controller is contacted with control room by GSM net,
Control room is according to each Workshop Production of electric quantity data reasonable arrangement gathered.Each electric quantity monitoring instrument and main controller are all connected to same electricity
On power netting twine and arrange main switch, installing an isolating diode after main switch, system uses half wave communication half-wave to power.
Each electric quantity monitoring instrument and main controller are respectively mounted cycle discriminator circuit, keep system acting for producing the lock in time of system
Unanimously, communications electronics switch, a switch drive module are respectively installed in its telecommunication circuit simultaneously.During communication, connect communication electricity
Son switch, otherwise, main controller first sends instruction to each electric quantity monitoring instrument, turns off communications electronics switch.
Communication is consistent for a long time by controlling lock in time with holding action, main controller and each electric quantity monitoring instrument, its communication
The switch drive module of electrical switch is to be followed by the CLK end of d type flip flop through resistance blood pressure lowering, dividing potential drop from electric power netting twine, d type flip flop
The external interrupt mouth (INT0 or INT1) of Q termination single-chip microcomputer, this external interrupt mouth is set to level triggers.The D termination of d type flip flop
Ground, its S end connects with the I/O mouth of single-chip microcomputer, and original state S end puts 1.When the positive square-wave signal of CLK end arrives, its rising edge
Making d type flip flop set to 0, external interrupt mouth low level produces interrupts, and first makes S end set to 0 and make d type flip flop put 1 in interrupt service routine
I.e. Q end is 1 to close interruption, then communicates, and communications electronics switch is connected to single-chip microcomputer corresponding port according to used communication mode,
And carrying out signal condition, before sign off, S end puts 1 communication making out next cycle of interrupt latency, and so go round and begin again realization half
Wave communication.
System is provided with SMS R-T unit, utilizes GSM network, communicate, at present receiving and dispatching short message mode
The SMS messaging service of GSM remains the SMS of the highest a kind of short message service GSM of domestic popularity rate itself and possesses data transmission merit
Can, the transmission of a message just constitutes and once communicates, and the transmission of message is by the SMS service center being in outside GSM
(SMSC) relay, the SMS service SMS of GSM it need not dial and can set up connection, user adds information to be sent out
Stay of two nights data are sent to short message service center, are then forwarded to the final stay of two nights after short message service center completes storage.So
When the no start of GSM terminal, information will not be lost.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three examination points and realizes sentencing the identification of cycle signal
Fixed, the recycling cycle time sets up lock in time, it is achieved main controller and the synchronous operation of each electric quantity monitoring instrument in system.
The cycle discriminator circuit structural representation of main controller and each electric quantity monitoring instrument is as in figure 2 it is shown, stagnant by two employings
Return the voltage comparator composition of comparator, each voltage comparator all comprises filter circuit, the benchmark electricity of its voltage comparator
Pressure is provided by mu balanced circuit.System arranges clock timer and synchrotimer.If be detected that adjacent two cycle signals
It is true, then takes out the clock timer timing time between these two adjacent cycle signal zero passages, when being sequentially stored in cycle
Between in memory element, this cycle time memory cell can deposit 100 cycle times, is often stored in a cycle time when being filled with,
The most first remove the cycle time being stored at first, and calculate meansigma methods Tz of the cycle time being stored in and preserve, utilize Tz value
Differentiating cycle signal to be identified, to reduce the impact of power network frequency fluctuation, use three examination points to reduce erroneous judgement may simultaneously
Property.
Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.Cycle in the cycle positive half cycle ascent stage
At zero passage, i.e. screening point 0 and arrange voltage zero-cross detection module, it uses cycle positive half-wave signal to enter through electric resistance partial pressure, diode
The clock end CLK, the Q of d type flip flop that send into d type flip flop after one step isolation negative half period, signal condition terminate single-chip microcomputer external interrupt
Mouthful, this external interrupt mouth is arranged to level triggers, the D end ground connection of d type flip flop, and S terminates single-chip processor i/o mouth, and this I/O mouth is put at ordinary times
1.When cycle positive half-wave zero cross signal arrives, cycle signal rising edge immediately after makes d type flip flop Q end be 0, outside single-chip microcomputer
Fracture low level in portion, thus produce interruption, interrupt service routine performs instruction: described I/O mouth sets to 0, closes interruption, meter
Time, described I/O mouth puts 1, opens interruption.Remaining two comparator is separately positioned on the cycle positive half cycle ascent stage, crest voltage
Point 1 and the examination point 2 at 50% to 70% place are screened by 35% to 50% place.
Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and starts timing, works as cycle
During voltage zero-cross, it is arranged on the output voltage of d type flip flop in the voltage zero-cross detection module V0 screening point 0 and jumps vanishing, produce
Raw interruption, records its zero crossing break period Th0；Hereafter, the output electricity of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning
Pressure, when week, wave voltage reached the threshold voltage of V1, output voltage saltus step from high to low, scanning records its bound-time Th1；
Voltage comparator V2 output voltage bound-time Th2 at point 2 screened in same scanning record, and with voltage zero-cross, Th0 is detected mould
Output voltage bound-time setting value Ts0 of block V0 is made comparisons；The output voltage bound-time of Th1 and voltage comparator V1
Output voltage bound-time setting value Ts2 of setting value Ts1 and Th2 and voltage comparator V2 is made comparisons respectively, if
In the range of allowable error, then this discriminator signal detected is true, is otherwise false.Above-mentioned judge discriminator signal as true time, calculate
During clock timer timing between this cycle signal zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time
Between Tzu, it is made comparisons with meansigma methods Tz of cycle time, if less than set cycle time error Tzv; cycle signal
Being true, at this moment preserve Tzu and take 20ms and be added with synchrotimer timing time, the value that will add up is stored in synchrotimer.
When clock timer starts timing with cycle voltage zero-cross, then timing is to opening the break period between 16ms to 18.5ms
Open interruption during setting value Tk, close during pass break period setting value Tn between clock timer timing to 25ms to 27ms and interrupt.
After system boot, clock timer starts timing, when first cycle voltage zero-cross being detected, is arranged on examination
The output voltage saltus step of the voltage zero-cross detection module V0 of point 0, thus produce interruption, take out the time of cycle voltage over zero
T0 preserves, and is reset by clock timer and starts timing, and at this moment cycle time voltage crosses zero Th0 is 0, and single-chip microcomputer is by above-mentioned simultaneously
Method scans and judges discriminator signal.Due to detection is first cycle, and clock timer is to open when cycle voltage zero-cross
Beginning timing, the value of its Th0, Th1 and Th2 must deduct open the difference of break period setting value Tk plus cycle time 20ms, as
Really three discriminator signals are true, and the time T0 of the cycle voltage over zero of taking-up is stored in synchrotimer as initial time,
I.e. for the first time open the break period takes Tk next time.Being otherwise fictitious time, now the clock timer time must continue detection plus T0.
When detecting first and during adjacent second cycle voltage zero-cross, owing to not preserving the cycle time of detection,
Therefore the clock timer timing time between twice cycle signal zero passage is to make comparisons with cycle time 20ms, it is determined that cycle signal
For true time, then it is to take 20ms to subtract the difference of Th0 and be added with synchrotimer timing time, preserves the standard cycle time i.e. for the first time
20ms, need to deduct its Th0 value, this is because detect that cycle signal is true time, all when opening interruption by clock meter the most every time
Time device reset after restart timing, and be when opening interruption, the standard cycle time to be counted in synchrotimer, open interruption
Rear clock timer reset, otherwise judges cycle signal as fictitious time, now the clock timer time must add T1=T0+Tk, continue
Continuous first cycle of detection the most again.After first cycle signal of detection is very, recover above-described cycle
Signal determining.
As it is shown in figure 1, if be detected that cycle signal is false, opens the break period and all open the break period at this next time
After, when meansigma methods Tz of time delay cycle time, open interruption, and have no progeny in opening time delay Tns time close and interrupt, pass is set when interrupting
Between be when cycle signal screen point 0 time do not produce interruption, at this moment must be at the setting time point more than Ts0 allowable error scope
Starting scanning, and scanning examination point 1 is with when screening point 2, voltage comparator output voltage does not produce saltus step, all interrupts in pass
Time Tns closes and interrupts and stop scanning, and Tns is:
Tns=Tn-Tk
If be detected that cycle signal is true, then next cycle is opened break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is all timing opens interruption to Tks, and weight after resetting
Newly start timing, close during timing to Tns and interrupt, so that the synchrotimer time is corrected by cycle time voltage crosses zero.
Repeat said process.If the upper cycle signal detected described in is true, and when this cycle judges, discriminator signal is
Vacation, or the cycle time detected compare with meansigma methods Tz of cycle time and exceed setting cycle time error Tzv, or clock meter
Time device timing to when closing break period setting value Tns, the voltage zero-cross detection module non-saltus step of V0 output voltage, in not producing
Disconnected, then close when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and stores, when opening interruption next time
Between be to open the break period in last time after Tz, open interruption, judge the cycle signal true and false, if false or this detection the most every time
Though discriminator signal is true but last time is false, then take N, will restore in memorizer after N+1, and clock timer has no progeny unclear zero in opening
Continuing timing, at this moment, next cycle of setting is opened the break period and is temporarily used out break period interim setting value Tkz instead:
Tkz=(N+1) × Tz
Meanwhile, next cycle pass break period temporarily uses instead and closes break period interim setting value Tnz:
Tnz=Tkz+Tns
When clock timer to after Tkz, scanning is screened the time of point and can be obtained by simple computation.If at this moment examined
It is true for measuring cycle signal, then take out N in memorizer and preserve, and by N zero setting in memorizer, make clock timer clocking value Ts
For (Ts-Tkz) → Ts, the value at this moment taking (N+1) × 20ms is added in synchrotimer, and recover to use setting value Tks with
Tns, recovered clock timer is had no progeny clearing in opening.
The system synchronization time is the time of synchrotimer, adds current the most just in time of clock timer of timing.
When judging to screen the some signal true and false, Th0, Th1, Th2 are by setting with voltage comparator output voltage bound-time
Definite value Ts0, Ts1, Ts2 make comparisons and see the most overproof, judge to screen a some signal true and false, can select: Th0, Th1, Th2 are
This cycle discriminator signal of true time is true, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 are true time, should
Cycle discriminator signal is true, depending on to judging that cycle signal true and false difference requires.
If system fault, when N is more than a setting value between 25 to 70, due to main controller and each electricity in system
Measuring instrument, the Tz value of its detection may be different with N value, at this moment, and power network frequency cumulative error, it is likely to result in synchrotimer
Time cannot by true cycle signal being detected time corrected, when detecting that cycle signal is true time, use clock timing
Device clocking value at Tkz is directly added in synchrotimer, to reduce the asynchronous time of system, and power network normal operation feelings
Under condition, N is much smaller than 25.
The cycle time error Tzv allowed and setting value flip-flop transition of voltage comparator output voltage, by test assessment
Take its meansigma methods to obtain.
(4) accompanying drawing explanation:
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structural representation；
Fig. 3 is the circuit structure block diagram of distribution electrical parameter acquisition system.
(5) detailed description of the invention:
Fig. 3 is the circuit structure block diagram of distribution electrical parameter acquisition system, including: main controller 10, communications electronics leave
Pass 11, switch drive module 12, SMS R-T unit 13, SIM 14, transformer 15, cycle screen electricity
Road 16, electric quantity monitoring instrument 17.Wherein communications electronics switch 11, switch drive module 12, cycle discriminator circuit
During in 16 and Fig. 2, single-chip microcomputer U0 is included in electric quantity monitoring instrument 17 and main controller 10 respectively.Transformer 15 wraps
Include voltage transformer summation current transformer.Wherein communications electronics switch 11 use bidirectional triode thyristor is as switch.
Fig. 2 is the structural representation of cycle discriminator circuit 16, by: input circuit S0, voltage zero-cross detection module
V0, voltage comparator V1 and voltage comparator V2 are constituted.Single-chip microcomputer U0 refers to electric quantity monitoring instrument 17 and master control
Single-chip microcomputer in device 10.Input circuit S0 for passing through resistance and the dividing potential drop of diode, conversion by mains AC voltage
For the input voltage that voltage comparator is the most stable.Single-chip microcomputer U0 uses 89C55WD, voltage comparator V1, voltage ratio
Using special voltage comparator LM393 compared with device V2, its reference voltage is that the mu balanced circuit using stabilivolt carrys out burning voltage
The threshold voltage of comparator.
When mains AC voltage cycle signal zero passage, the output voltage saltus step of voltage zero-cross detection module V0, single
Sheet machine U0 produces interruption, records the break period, and single-chip microcomputer U0 is additionally operable to scanning voltage comparator V1 and voltage ratio simultaneously
The relatively output voltage of device V2, records bound-time, is used for judging power network cycle signal thus produces when output voltage saltus step
Raw lock in time.
In SMS R-T unit, single chip computer89C51 realizes serial communication by I2C bus and main controller, this single-chip microcomputer
89C51 is connected also by serial line interface integrated circuit MAX232 and gsm module TC35i and carries out data exchange, gsm module chip
TC35i is RS232 data port, supports AT Command Set, wherein contains the control to SMS, and single chip computer89C51 is by GSM mould
Block sends a series of AT instruction, completes the initialization to gsm module and receiving short message.The transmitting-receiving of SMS uses TEXT pattern,
TEXT pattern is a kind of structural models based on ASCII character.
Claims (2)
1. distribution electrical parameter acquisition system, is characterized in that, its electric quantity data gathered is sent to by electric lines of force half wave communication
Main controller processes, and main controller is contacted with control room by GSM net, and control room is according to each workshop of electric quantity data reasonable arrangement gathered
Producing, each electric quantity monitoring instrument and main controller are all connected on same electric power netting twine and arrange main switch, install after main switch
One isolating diode, is respectively mounted cycle discriminator circuit in each electric quantity monitoring instrument and main controller, for producing the synchronization of system
Time, simultaneously communications electronics switch, switch drive module of each installation, main controller and each electric quantity monitoring in its telecommunication circuit
It is consistent for a long time by controlling lock in time with holding action that instrument communicates therebetween, and the switch drive module of its communications electronics switch is
It is followed by the CLK end of d type flip flop through resistance blood pressure lowering, dividing potential drop from electric power netting twine, the external interrupt mouth of the Q termination single-chip microcomputer of d type flip flop,
When the positive square-wave signal of CLK end arrives, its rising edge makes d type flip flop set to 0, and external interrupt mouth low level produces interrupts, and carries out
Communication, is provided with SMS R-T unit, utilizes GSM network in system, communicate receiving and dispatching short message mode；
Cycle discriminator circuit is the positive half cycle ascent stage utilizing power network cycle, takes three and screens the some realization knowledge to cycle signal
Not judging, the recycling cycle time sets up lock in time, and system arranges clock timer and synchrotimer, if be detected that phase
Two the cycle signals faced are very, then when taking out the clock timer timing between these two adjacent cycle signal zero passages
Between, sequentially it is stored in cycle time memory cell, is often stored in a cycle time when being filled with 100 cycle time, the most first removes
The cycle time being stored at first, and calculate meansigma methods Tz of the cycle time being stored in, utilize Tz value to differentiate cycle to be identified
Signal；
Two comparators are respectively used to screen point 1, screen point 2, at the cycle zero passage of cycle positive half cycle ascent stage, i.e. screen a little
0 arranges voltage zero-cross detection module, it use cycle positive half-wave signal through electric resistance partial pressure, diode isolate further negative half period,
The clock end CLK of d type flip flop is sent into after signal condition, when cycle positive half-wave zero cross signal arrives, cycle letter immediately after
Number rising edge makes d type flip flop Q end be 0, single-chip microcomputer external interrupt mouth low level, thus produces interruption, and remaining two comparator divides
Not being arranged on the cycle positive half cycle ascent stage, point 1 and the examination at 50% to 70% place are screened by 35% to 50% place of crest voltage
Point 2；
Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and starts timing, when week wave voltage
During zero passage, it is arranged on the output voltage of d type flip flop in the voltage zero-cross detection module screening point 0 and jumps vanishing, produce and interrupt, note
Record its zero crossing break period Th0；Hereafter, the output voltage of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning, works as cycle
When voltage reaches the threshold voltage of voltage comparator V1, output voltage saltus step from high to low, scanning records its bound-time
Th1；Same scanning record screens voltage comparator V2 output voltage bound-time Th2 at point 2, if described bound-time exists
In the range of allowable error, then this discriminator signal detected is true, is otherwise false, above-mentioned judges that discriminator signal, as true time, calculates
During clock timer timing between this cycle signal zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time
Between Tzu, it is made comparisons with meansigma methods Tz of cycle time, if less than set cycle time error Tzv; cycle signal
Being true, at this moment preserve Tzu and take 20ms and be added with synchrotimer timing time, the value that will add up is stored in synchrotimer；
When clock timer starts timing with cycle voltage zero-cross, then timing set to the break period of opening between 16ms to 18.5ms
Open interruption during value Tk, close during pass break period setting value Tn between clock timer timing to 25ms to 27ms and interrupt；
When first cycle voltage zero-cross being detected, the output voltage being arranged on the voltage zero-cross detection module screening point 0 is jumped
Becoming, thus produce interruption, the time T0 taking out cycle voltage over zero preserves, and is reset by clock timer and starts timing, this
Shi Zhoubo time voltage crosses zero Th0 is 0, and single-chip microcomputer scans as stated above and judges discriminator signal, its Th0, Th1 and Th2's
Value must deduct open the difference of break period setting value Tk plus cycle time 20ms, if three discriminator signals are true, takes out
The time T0 of cycle voltage over zero be stored in synchrotimer as initial time, open the break period the most for the first time next time
Taking Tk, be otherwise fictitious time, now the clock timer time must continue detection plus T0；
When first and adjacent second cycle voltage zero-cross being detected, it is determined that cycle signal is true time, then be to take 20ms to subtract
The difference of Th0 is added with synchrotimer timing time, and clock timer of having no progeny in opening resets, and otherwise judges that cycle signal is as false
Time, now the clock timer time must continue first cycle of detection the most again plus T1=T0+Tk, work as detection
First cycle signal be very after, recover above-described cycle signal determining；
If be detected that cycle signal is false, open the break period all after this opens the break period, when time delay cycle next time
Between meansigma methods Tz time open interruption, and have no progeny in opening time delay Tns time close and interrupt, arranging the pass break period is when cycle signal is discriminated
Not Wei fictitious time, close break period Tns close interrupt and stop scanning, Tns is:
Tns=Tn-Tk
If be detected that cycle signal is true, then next cycle is opened break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is all timing opens interruption to Tks, and again opens after resetting
Beginning timing, closes during timing to Tns and interrupts；
Repeat said process, if described in the upper cycle signal that detects be true, when this cycle judges, discriminator signal is false,
Then closing when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and stores, open the break period is next time
Opened the break period in last time after Tz, open interruption, judge the cycle signal true and false the most every time, if false or this detection is screened
Though signal is true but last time is false, then take N, will restore in memorizer after N+1, and clock timer is had no progeny unclear zero continuation in opening
Timing, at this moment, next cycle of setting is opened the break period and is temporarily used out break period interim setting value Tkz instead:
Tkz=(N+1) × Tz
Meanwhile, next cycle pass break period temporarily uses instead and closes break period interim setting value Tnz:
Tnz=Tkz+Tns
When clock timer to after Tkz, if at this moment detecting that cycle signal is true, then take out N in memorizer and preserve, and
By N zero setting in memorizer, the clock timer clocking value Ts is made to be: (Ts-Tkz) → Ts, the value at this moment taking (N+1) × 20ms adds
In synchrotimer, and recovering to use setting value Tks and Tns, recovered clock timer is had no progeny clearing in opening；
The system synchronization time is the time of synchrotimer, adds current the most just in time of clock timer of timing；
When judging to screen the some signal true and false, select: it is true that Th0, Th1, Th2 are this cycle discriminator signal of true time, or Th0 is
True and one of Th1, Th2 are true time, or Th1, Th2 are true time, and this cycle discriminator signal is true, depending on to judging that cycle signal is true
Depending on pseudo-different requirement, if N is more than a setting value between 25 to 70, use clock timer clocking value at Tkz
Directly it is added in synchrotimer.
Distribution electrical parameter acquisition system the most according to claim 1, it is characterised in that including:
Main controller 10, communications electronics switch 11, switch drive module 12, SMS R-T unit 13, SIM
14, transformer 15, cycle discriminator circuit 16, electric quantity monitoring instrument 17, wherein single-chip microcomputer U0 and communications electronics leave
Close 11, switch drive module 12 and cycle discriminator circuit 16 and be included in electric quantity monitoring instrument 17 and master control respectively
In device 10, transformer 15 includes voltage transformer summation current transformer；
Cycle discriminator circuit 16, by: input circuit S0, voltage zero-cross detection module V0, voltage comparator V1 and electricity
Pressure comparator V2 is constituted, and input circuit S0 for passing through resistance and the dividing potential drop of diode, conversion by mains AC voltage
For the input voltage that voltage comparator is the most stable；
In SMS R-T unit, single chip computer89C51 realizes serial communication by I2C bus and main controller, this single-chip microcomputer
89C51 is connected with gsm module TC35i also by serial port MAX232 and carries out data exchange.
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| CN201610447962.0A CN106097683B (en) | 2016-06-20 | 2016-06-20 | Distribution electric quantity parameter acquisition system |
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| CN2230929Y (en) * | 1994-10-06 | 1996-07-10 | 吴子方 | Electric meter |
| JP2001256583A (en) * | 2000-03-08 | 2001-09-21 | Toyo Keiki Co Ltd | Automatic meter reading system |
| CN101256210A (en) * | 2008-03-26 | 2008-09-03 | 首都师范大学 | Three-phase electric energy meter based on NIOS II microprocessor |
| JP2011250300A (en) * | 2010-05-28 | 2011-12-08 | Panasonic Electric Works Co Ltd | Remote meter reading system |
| JP2015186388A (en) * | 2014-03-25 | 2015-10-22 | 株式会社東芝 | Watt-hour meter for automatic meter reading system and power failure monitoring system |
-
2016
- 2016-06-20 CN CN201610447962.0A patent/CN106097683B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2230929Y (en) * | 1994-10-06 | 1996-07-10 | 吴子方 | Electric meter |
| JP2001256583A (en) * | 2000-03-08 | 2001-09-21 | Toyo Keiki Co Ltd | Automatic meter reading system |
| CN101256210A (en) * | 2008-03-26 | 2008-09-03 | 首都师范大学 | Three-phase electric energy meter based on NIOS II microprocessor |
| JP2011250300A (en) * | 2010-05-28 | 2011-12-08 | Panasonic Electric Works Co Ltd | Remote meter reading system |
| JP2015186388A (en) * | 2014-03-25 | 2015-10-22 | 株式会社東芝 | Watt-hour meter for automatic meter reading system and power failure monitoring system |
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| CN106097683B (en) | 2018-12-11 |
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