(3) summary of the invention:
When needing the electrical parameter measuring each bar distribution line it is necessary to gather distribution electrical parameter, it is used for optimizing distribution
System, the reasonable arrangement equipment operation time.The present invention relates to a kind of distribution electrical parameter acquisition system, comprise multiple stage electric quantity monitoring
Instrument and a main controller, every distribution line and primary electricity using device all configure an electric quantity monitoring instrument, every electricity prison
Surveying instrument and comprise one or several voltage transformer summation current transformer, the operation of electric quantity monitoring instrument monitoring distribution line is real-time
Parameter, mainly has: circuit three-phase voltage, three-phase current, active power, reactive power, power factor, by electric quantity monitoring instrument
ADC carries out synchronized sampling, can realize the voltage of homophase, current synchronization sampling, and sampled signal carries out conditioning conversion, then by it
The electric quantity data gathered sends main controller to by electric lines of force half wave communication and processes, and main controller is contacted with control room by GSM net,
Control room is according to each Workshop Production of electric quantity data reasonable arrangement gathered.Each electric quantity monitoring instrument and main controller are all connected to same electricity
On power netting twine and arrange main switch, installing an isolating diode after main switch, system uses half wave communication half-wave to power.
Each electric quantity monitoring instrument and main controller are respectively mounted cycle discriminator circuit, keep system acting for producing the lock in time of system
Unanimously, communications electronics switch, a switch drive module are respectively installed in its telecommunication circuit simultaneously.During communication, connect communication electricity
Son switch, otherwise, main controller first sends instruction to each electric quantity monitoring instrument, turns off communications electronics switch.
Communication is consistent for a long time by controlling lock in time with holding action, main controller and each electric quantity monitoring instrument, its communication
The switch drive module of electrical switch is to be followed by the CLK end of d type flip flop through resistance blood pressure lowering, dividing potential drop from electric power netting twine, d type flip flop
The external interrupt mouth (INT0 or INT1) of Q termination single-chip microcomputer, this external interrupt mouth is set to level triggers.The D termination of d type flip flop
Ground, its S end connects with the I/O mouth of single-chip microcomputer, and original state S end puts 1.When the positive square-wave signal of CLK end arrives, its rising edge
Making d type flip flop set to 0, external interrupt mouth low level produces interrupts, and first makes S end set to 0 and make d type flip flop put 1 in interrupt service routine
I.e. Q end is 1 to close interruption, then communicates, and communications electronics switch is connected to single-chip microcomputer corresponding port according to used communication mode,
And carrying out signal condition, before sign off, S end puts 1 communication making out next cycle of interrupt latency, and so go round and begin again realization half
Wave communication.
System is provided with SMS R-T unit, utilizes GSM network, communicate, at present receiving and dispatching short message mode
The SMS messaging service of GSM remains the SMS of the highest a kind of short message service GSM of domestic popularity rate itself and possesses data transmission merit
Can, the transmission of a message just constitutes and once communicates, and the transmission of message is by the SMS service center being in outside GSM
(SMSC) relay, the SMS service SMS of GSM it need not dial and can set up connection, user adds information to be sent out
Stay of two nights data are sent to short message service center, are then forwarded to the final stay of two nights after short message service center completes storage.So
When the no start of GSM terminal, information will not be lost.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three examination points and realizes sentencing the identification of cycle signal
Fixed, the recycling cycle time sets up lock in time, it is achieved main controller and the synchronous operation of each electric quantity monitoring instrument in system.
The cycle discriminator circuit structural representation of main controller and each electric quantity monitoring instrument is as in figure 2 it is shown, stagnant by two employings
Return the voltage comparator composition of comparator, each voltage comparator all comprises filter circuit, the benchmark electricity of its voltage comparator
Pressure is provided by mu balanced circuit.System arranges clock timer and synchrotimer.If be detected that adjacent two cycle signals
It is true, then takes out the clock timer timing time between these two adjacent cycle signal zero passages, when being sequentially stored in cycle
Between in memory element, this cycle time memory cell can deposit 100 cycle times, is often stored in a cycle time when being filled with,
The most first remove the cycle time being stored at first, and calculate meansigma methods Tz of the cycle time being stored in and preserve, utilize Tz value
Differentiating cycle signal to be identified, to reduce the impact of power network frequency fluctuation, use three examination points to reduce erroneous judgement may simultaneously
Property.
Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.Cycle in the cycle positive half cycle ascent stage
At zero passage, i.e. screening point 0 and arrange voltage zero-cross detection module, it uses cycle positive half-wave signal to enter through electric resistance partial pressure, diode
The clock end CLK, the Q of d type flip flop that send into d type flip flop after one step isolation negative half period, signal condition terminate single-chip microcomputer external interrupt
Mouthful, this external interrupt mouth is arranged to level triggers, the D end ground connection of d type flip flop, and S terminates single-chip processor i/o mouth, and this I/O mouth is put at ordinary times
1.When cycle positive half-wave zero cross signal arrives, cycle signal rising edge immediately after makes d type flip flop Q end be 0, outside single-chip microcomputer
Fracture low level in portion, thus produce interruption, interrupt service routine performs instruction: described I/O mouth sets to 0, closes interruption, meter
Time, described I/O mouth puts 1, opens interruption.Remaining two comparator is separately positioned on the cycle positive half cycle ascent stage, crest voltage
Point 1 and the examination point 2 at 50% to 70% place are screened by 35% to 50% place.
Cycle signal determining: single-chip microcomputer is had no progeny in the setting time opens, and clock timer resets and starts timing, works as cycle
During voltage zero-cross, it is arranged on the output voltage of d type flip flop in the voltage zero-cross detection module V0 screening point 0 and jumps vanishing, produce
Raw interruption, records its zero crossing break period Th0;Hereafter, the output electricity of voltage comparator V1 at point 1 is screened in single-chip microcomputer scanning
Pressure, when week, wave voltage reached the threshold voltage of V1, output voltage saltus step from high to low, scanning records its bound-time Th1;
Voltage comparator V2 output voltage bound-time Th2 at point 2 screened in same scanning record, and with voltage zero-cross, Th0 is detected mould
Output voltage bound-time setting value Ts0 of block V0 is made comparisons;The output voltage bound-time of Th1 and voltage comparator V1
Output voltage bound-time setting value Ts2 of setting value Ts1 and Th2 and voltage comparator V2 is made comparisons respectively, if
In the range of allowable error, then this discriminator signal detected is true, is otherwise false.Above-mentioned judge discriminator signal as true time, calculate
During clock timer timing between this cycle signal zero passage with the cycle signal zero passage that an adjacent front discriminator signal is true time
Between Tzu, it is made comparisons with meansigma methods Tz of cycle time, if less than set cycle time error Tzv; cycle signal
Being true, at this moment preserve Tzu and take 20ms and be added with synchrotimer timing time, the value that will add up is stored in synchrotimer.
When clock timer starts timing with cycle voltage zero-cross, then timing is to opening the break period between 16ms to 18.5ms
Open interruption during setting value Tk, close during pass break period setting value Tn between clock timer timing to 25ms to 27ms and interrupt.
After system boot, clock timer starts timing, when first cycle voltage zero-cross being detected, is arranged on examination
The output voltage saltus step of the voltage zero-cross detection module V0 of point 0, thus produce interruption, take out the time of cycle voltage over zero
T0 preserves, and is reset by clock timer and starts timing, and at this moment cycle time voltage crosses zero Th0 is 0, and single-chip microcomputer is by above-mentioned simultaneously
Method scans and judges discriminator signal.Due to detection is first cycle, and clock timer is to open when cycle voltage zero-cross
Beginning timing, the value of its Th0, Th1 and Th2 must deduct open the difference of break period setting value Tk plus cycle time 20ms, as
Really three discriminator signals are true, and the time T0 of the cycle voltage over zero of taking-up is stored in synchrotimer as initial time,
I.e. for the first time open the break period takes Tk next time.Being otherwise fictitious time, now the clock timer time must continue detection plus T0.
When detecting first and during adjacent second cycle voltage zero-cross, owing to not preserving the cycle time of detection,
Therefore the clock timer timing time between twice cycle signal zero passage is to make comparisons with cycle time 20ms, it is determined that cycle signal
For true time, then it is to take 20ms to subtract the difference of Th0 and be added with synchrotimer timing time, preserves the standard cycle time i.e. for the first time
20ms, need to deduct its Th0 value, this is because detect that cycle signal is true time, all when opening interruption by clock meter the most every time
Time device reset after restart timing, and be when opening interruption, the standard cycle time to be counted in synchrotimer, open interruption
Rear clock timer reset, otherwise judges cycle signal as fictitious time, now the clock timer time must add T1=T0+Tk, continue
Continuous first cycle of detection the most again.After first cycle signal of detection is very, recover above-described cycle
Signal determining.
As it is shown in figure 1, if be detected that cycle signal is false, opens the break period and all open the break period at this next time
After, when meansigma methods Tz of time delay cycle time, open interruption, and have no progeny in opening time delay Tns time close and interrupt, pass is set when interrupting
Between be when cycle signal screen point 0 time do not produce interruption, at this moment must be at the setting time point more than Ts0 allowable error scope
Starting scanning, and scanning examination point 1 is with when screening point 2, voltage comparator output voltage does not produce saltus step, all interrupts in pass
Time Tns closes and interrupts and stop scanning, and Tns is:
Tns=Tn-Tk
If be detected that cycle signal is true, then next cycle is opened break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is all timing opens interruption to Tks, and weight after resetting
Newly start timing, close during timing to Tns and interrupt, so that the synchrotimer time is corrected by cycle time voltage crosses zero.
Repeat said process.If the upper cycle signal detected described in is true, and when this cycle judges, discriminator signal is
Vacation, or the cycle time detected compare with meansigma methods Tz of cycle time and exceed setting cycle time error Tzv, or clock meter
Time device timing to when closing break period setting value Tns, the voltage zero-cross detection module non-saltus step of V0 output voltage, in not producing
Disconnected, then close when clock timer timing to Tns and interrupt, at this moment remember that not counting cycle N is 1 and stores, when opening interruption next time
Between be to open the break period in last time after Tz, open interruption, judge the cycle signal true and false, if false or this detection the most every time
Though discriminator signal is true but last time is false, then take N, will restore in memorizer after N+1, and clock timer has no progeny unclear zero in opening
Continuing timing, at this moment, next cycle of setting is opened the break period and is temporarily used out break period interim setting value Tkz instead:
Tkz=(N+1) × Tz
Meanwhile, next cycle pass break period temporarily uses instead and closes break period interim setting value Tnz:
Tnz=Tkz+Tns
When clock timer to after Tkz, scanning is screened the time of point and can be obtained by simple computation.If at this moment examined
It is true for measuring cycle signal, then take out N in memorizer and preserve, and by N zero setting in memorizer, make clock timer clocking value Ts
For (Ts-Tkz) → Ts, the value at this moment taking (N+1) × 20ms is added in synchrotimer, and recover to use setting value Tks with
Tns, recovered clock timer is had no progeny clearing in opening.
The system synchronization time is the time of synchrotimer, adds current the most just in time of clock timer of timing.
When judging to screen the some signal true and false, Th0, Th1, Th2 are by setting with voltage comparator output voltage bound-time
Definite value Ts0, Ts1, Ts2 make comparisons and see the most overproof, judge to screen a some signal true and false, can select: Th0, Th1, Th2 are
This cycle discriminator signal of true time is true, or Th0 is true, and one of Th1, Th2 are true time simultaneously, or Th1, Th2 are true time, should
Cycle discriminator signal is true, depending on to judging that cycle signal true and false difference requires.
If system fault, when N is more than a setting value between 25 to 70, due to main controller and each electricity in system
Measuring instrument, the Tz value of its detection may be different with N value, at this moment, and power network frequency cumulative error, it is likely to result in synchrotimer
Time cannot by true cycle signal being detected time corrected, when detecting that cycle signal is true time, use clock timing
Device clocking value at Tkz is directly added in synchrotimer, to reduce the asynchronous time of system, and power network normal operation feelings
Under condition, N is much smaller than 25.
The cycle time error Tzv allowed and setting value flip-flop transition of voltage comparator output voltage, by test assessment
Take its meansigma methods to obtain.