CN106102227B - Building roof control system of lamp decoration - Google Patents
Building roof control system of lamp decoration Download PDFInfo
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- CN106102227B CN106102227B CN201610454640.9A CN201610454640A CN106102227B CN 106102227 B CN106102227 B CN 106102227B CN 201610454640 A CN201610454640 A CN 201610454640A CN 106102227 B CN106102227 B CN 106102227B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
- H05B45/20—Controlling the colour of the light
- H05B45/24—Controlling the colour of the light using electrical feedback from LEDs or from LED modules
Abstract
The present invention relates to a kind of building roof control system of lamp decoration, it is made up of the LED billboard for standing on the building roof of sequential in building.Each billboard has controller to control lighting and changing colour for LED, and controller is connected to same power network in each billboard, common to complete overall light decorative effect under the software collaboration control of lock in time and each lamp controller without master controller.
Description
(1) technical field：
The present invention relates to a kind of building roof control system of lamp decoration, it is by standing on the building roof of sequential in building
LED billboard is constituted.Each billboard has controller to control lighting and changing colour for LED, and controller connects in each billboard
It is common to complete total under the software collaboration control of lock in time and each lamp controller without master controller in same power network
Body light decorative effect.
(2) background technology：
The control system of power supply is provided by power network, its each electronic equipment or intermodule are communicated by special circuit,
To correct the timing time of each electronic equipment or electronic module, synchronous operation purpose is reached.Due to being made using special circuit communication
Wiring complicates and increases cost, if timing time is not corrected by line traffic, due to traditional timing error, runs number
After hour, its accumulation timing error can make system control action inconsistent, be likely to result in system crash, often change and set at some
Meter, its products application of the big occasion of wiring installation amount is restricted.
(3) content of the invention：
The present invention relates to building roof control system of lamp decoration, being installed on roof has installation and safeguards simply and easily special
Point, it is made up of the LED billboard for standing on the building roof of sequential in building, expresses one wide by several LED billboards
Content is accused, the ad content is made up of pattern or Chinese character, each billboard has controller to control lighting and changing colour for LED.
Controller is connected to same power network in each billboard, with a power switch, without order wire, without master controller.Same
It is common to complete overall light decorative effect under the software collaboration control of step time and each lamp controller, for example gradually it is bright, gradually dark, bounce,
The various Display patterns such as pile up, and keep permanent synchronous rule to show.Its display pattern is selected, when being one section after firm start
Between, when each lamp controller sequentially shows varying number LED jointly, selection LED light quantity shutdown preservation, obtain with
This lights the corresponding display pattern of quantity, and it is that in the numbering period when can't detect grid cyclic wave signal, single-chip microcomputer is relied on
Numbering data are stored in nonvolatile storage by the energy storage of its power capacitor.
The present invention is taken three to screen point and is realized that the identification to cycle signal is sentenced using the positive half cycle ascent stage of power network cycle
It is fixed, recycle the cycle time to set up lock in time, realize the synchronous operation of controller in each LED billboard of system.
The cycle discriminator circuit structural representation of controller by two as shown in Fig. 2 use hysteresis ratio in each LED billboard
Voltage comparator compared with device is constituted, and includes filter circuit in each voltage comparator, the reference voltage of its voltage comparator by
Mu balanced circuit is provided.System sets clock timer and synchrotimer.It is if detecting two adjacent cycle signals
Very, then take out the clock timer timing time between this two adjacent cycle signal zero passages, sequentially be stored in the cycle time deposit
In storage unit, the cycle time memory cell can deposit 100 cycle times, a cycle time is often stored in when being filled with, first
The cycle time being stored at first is removed, and calculates the average value Tz of the cycle time of deposit and preserves, is differentiated using Tz values
Cycle signal to be identified, to reduce the influence of power network frequency fluctuation, while screening point reduction erroneous judgement possibility using three.
Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.In the cycle of cycle positive half cycle ascent stage
At zero passage, that is, screen point 0 and voltage zero-cross detection module is set, it is entered using cycle positive half-wave signal through electric resistance partial pressure, diode
The clock end CLK of d type flip flop, the Q termination single-chip microcomputer external interrupts of d type flip flop are sent into after one step isolation negative half period, signal condition
Mouthful, external interrupt mouth is arranged to level triggers, and the D ends ground connection of d type flip flop, S termination single-chip processor i/os mouthful are usually put for the I/O mouthfuls
1.When cycle positive half-wave zero cross signal arrives, cycle signal rising edge immediately after makes d type flip flop Q ends be outside 0, single-chip microcomputer
Fracture low level in portion, so that interruption is produced, the execute instruction in interrupt service routine：Described I/O mouthfuls set to 0, the Central Shanxi Plain is disconnected, meter
When, described I/O mouthfuls put 1, open interruption.Remaining two comparator is separately positioned on the cycle positive half cycle ascent stage, crest voltage
The examination point 1 and the examination point 2 at 50% to 70% place at 35% to 50% place.
Cycle signal determining：Single-chip microcomputer is after setting time opens interruption, and clock timer resets and starts timing, works as cycle
During voltage zero-cross, the output voltage for being arranged on d type flip flop in the voltage zero-cross inspection survey mould block ﹙ V0 ﹚ for screen point 0 jumps vanishing, production
It is raw to interrupt, record its zero crossing break period Th0；Hereafter, the output electricity of electricity pressure comparator ﹙ V1 ﹚ at point 1 is screened in single-chip microcomputer scanning
Pressure, when all wave voltages are reached to ﹙ V1 ﹚ threshold voltage, output voltage saltus step from high to low, scanning records its bound-time Th1；
Same scanning record screens electricity pressure comparator ﹙ V2 ﹚ output voltage bound-time Th2 at point 2, and Th0 and voltage zero-cross are detected into mould
Kuai ﹙ V0 ﹚ output voltage bound-time setting value Ts0 makes comparisons；Th1 and electricity pressure comparator ﹙ V1 ﹚ output voltage bound-time
Setting value Ts1 and Th2 makes comparisons respectively with electricity pressure comparator ﹙ V2 ﹚ output voltage bound-time setting value Ts2, if
In the range of allowable error, then the discriminator signal detected is true, is otherwise false.It is above-mentioned when judging discriminator signal to be true, calculate
During clock timer timing between cycle signal zero passage when this cycle signal zero passage and an adjacent preceding discriminator signal are true
Between Tzu, it is made comparisons with the average value Tz of cycle time, the cycle signal if no more than setting cycle time error Tzv
It is true, at this moment preserves Tzu and take 20ms to be added with synchrotimer timing time, in the value deposit synchrotimer that will add up.
When clock timer with cycle voltage zero-cross starts timing, then timing opens the break period to 16ms between 18.5ms
Open interruption during setting value Tk, clock timer timing to 25ms to Central Shanxi Plain during pass break period setting value Tn between 27ms is broken.
After system boot, clock timer starts timing, when detecting first cycle voltage zero-cross, is arranged on examination
The voltage zero-cross Jian of point 0 surveys Mo Kuai ﹙ V0 ﹚ output voltage saltus step, so as to produce interruption, takes out the time of cycle voltage over zero
T0 is preserved, and clock timer is reset and starts timing, and at this moment cycle time voltage crosses zero Th0 is 0, while single-chip microcomputer is by above-mentioned
Method scans and judges discriminator signal.What it is due to detection is first cycle, and clock timer is opened in cycle voltage zero-cross
Beginning timing, its Th0, Th1 and Th2 value must subtract open break period setting value Tk difference plus cycle time 20ms, such as
Really three discriminator signals are true, and the time T0 of the cycle voltage over zero of taking-up is stored in synchrotimer as initial time,
I.e. opening the break period for the first time takes Tk next time.Otherwise it is fictitious time, now the clock timer time must be plus T0, and continuation is detected.
When detecting first with second adjacent cycle voltage zero-cross, due to not preserving the cycle time of detection,
Therefore the clock timer timing time twice between cycle signal zero passage is made comparisons with cycle time 20ms, judges cycle signal
Then it is that the difference for taking 20ms to subtract Th0 is added with synchrotimer timing time when being true, i.e., preserves the standard cycle time for the first time
20ms, need to deduct its Th0 value, because when hereafter to detect cycle signal every time be true, by clock meter when opening interruption
When device reset after restart timing, and be that the standard cycle time is included in synchrotimer when opening interruption, open interruption
Clock timer is reset afterwards, otherwise judges cycle signal as fictitious time, now the clock timer time must plus T1=T0+Tk, after
It is continuous to detect first cycle again as stated above.After it is very to detect first cycle signal, recover above-described cycle
Signal determining.
If as shown in figure 1, it is false to detect cycle signal, the break period being opened next time and opens the break period at this
Afterwards, open interruptions during average value Tz through the cycle time that is delayed, and open interrupt after be delayed Tns when the Central Shanxi Plain break, when setting the Central Shanxi Plain to break
Between be when cycle signal screen point 0 when do not produce interruption, at this moment must be in the setting time point more than Ts0 allowable error scopes
When starting scanning, and scanning examination point 1 with point 2 is screened, voltage comparator output voltage does not produce saltus step, all breaks in the Central Shanxi Plain
The Central Shanxi Plain was broken and stopped scanning time Tns, and Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
Opened from first time after the break period takes Tk, clock timer is that timing is opened to Tks and weighed after interruptions, and clearing
New to start timing, timing is disconnected to Central Shanxi Plain during Tns, so that the synchrotimer time is corrected by cycle time voltage crosses zero.
Repeat said process.If the upper cycle signal detected is true, when this cycle judges, discriminator signal is
Vacation, or the cycle time detected are compared with the average value Tz of cycle time more than setting cycle time error Tzv, or clock meter
When device timing to close break period setting value Tns when, voltage zero-cross inspection survey the non-saltus step of mould block ﹙ V0 ﹚ output voltages, in not producing
Disconnected, then when clock timer timing is to Tns, the Central Shanxi Plain is broken, and at this moment remembers that not counting cycle N is 1 and stores, when opening interruption next time
Between be to open the break period in last time to open interruption after Tz, clock timer open interrupt after reset and timing, when timing is to Tns
The Central Shanxi Plain is broken, and the cycle signal true and false is hereafter judged every time, though if false or this detection discriminator signal be false true last time, then take
N, will be restored in memory after N+1.
When it is true to detect cycle signal, then takes out N in memory and preserve, and by N zero setting in memory, and recover to make
Setting value Tks is used, at this moment takes (N+1) × 20ms value to be added in synchrotimer.
The system synchronization time be synchrotimer time, along with currently just timing clock timer time.
When judging to screen the point signal true and false, Th0, Th1, Th2 are by being set with voltage comparator output voltage bound-time
Whether overproof definite value Ts0, Ts1, Ts2 make comparisons sees, to judge to screen the point signal true and false, can select：Th0, Th1, Th2 are
The cycle discriminator signal is true when true, or Th0 is true, while when one of Th1, Th2 are true, or Th1, Th2 are when being true, should
Cycle discriminator signal is true, depending on to judging that cycle signal true and false difference is required.
If system fault, when N is more than a setting value between 25 to 70, due in each LED billboard in system
Controller, its Tz value detected may be different with N values, at this moment, power network frequency accumulated error, when being likely to result in synchrotimer
Between corrected when can not be by detecting true cycle signal, when it is true to detect cycle signal, at this moment using clock meter
When device accumulative clocking value be directly added in synchrotimer, to reduce the asynchronous time of system, add up clocking value be N × Tz
+20ms.N is much smaller than 25 in the case of power network normal operation.
The cycle time error Tzv of permission and the flip-flop transition setting value of voltage comparator output voltage, by test assessment
Its average value is taken to obtain.
(4) illustrate：
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structural representation；
Fig. 3 is the circuit structure block diagram of building roof control system of lamp decoration.
(5) embodiment：
Fig. 3 is the circuit structure block diagram of building roof control system of lamp decoration, including:The ﹚ of Kong Qi ﹙ 11, cycle screen electricity
The ﹚ of 12 ﹚, Guang Gao Pai ﹙ of Lu ﹙ 13, wherein cycle screen Dan Pian Ji ﹙ U0 ﹚ in the ﹚ and Fig. 2 of electricity Lu ﹙ 12 and are respectively included in each Kong Qi ﹙
In 11 ﹚.
Fig. 2 is the structural representation that cycle screens the ﹚ of electricity Lu ﹙ 12, by：Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian and surveys Mo Kuai ﹙
V0 ﹚, electricity pressure comparator ﹙ V1 ﹚ and electricity pressure comparator ﹙ V2 ﹚ are constituted.Dan Pian Ji ﹙ U0 ﹚ refer to the single-chip microcomputer in each ﹚ of Kong Qi ﹙ 11.
Shu, which enters electricity Lu ﹙ S0 ﹚, to be used for partial pressure of the mains AC voltage by resistance and diode, is converted to voltage comparator suitable
Stable input voltage.Single piece machine ﹙ U0 ﹚ survey mould block ﹙ V0 ﹚, electricity pressure comparator ﹙ V1 ﹚, voltage using the inspection of 89C55WD voltage zero-cross
Bi compare Qi ﹙ V2 ﹚ use special voltage comparator LM339, and its reference voltage is come stable using the mu balanced circuit of voltage-stabiliser tube
The threshold voltage of voltage comparator.
When mains AC voltage cycle signal zero passage, voltage zero-cross Jian surveys Mo Kuai ﹙ V0 ﹚ output voltage saltus step, single
Pian Ji ﹙ U0 ﹚ produce interruption, the break period are recorded, while Dan Pian Ji ﹙ U0 ﹚ are additionally operable to scanning voltage Bi compare Qi ﹙ V1 ﹚ and voltage ratio
Compare Qi ﹙ V2 ﹚ output voltage, bound-time is recorded when output voltage saltus step, for judging power network cycle signal so as to produce
Raw lock in time.
Claims (2)
1. a kind of building roof control system of lamp decoration, it is characterized in that, in the software collaboration control of lock in time and each lamp controller
It is common to complete overall light decorative effect under system, keep permanent synchronous rule to show, the selection of its display pattern is after firm start
For a period of time, when each lamp controller sequentially shows varying number LED jointly, the quantity shutdown of lighting of selection LED is preserved,
Obtain with the display pattern that to light quantity corresponding, it is the monolithic in the numbering period when can't detect grid cyclic wave signal
Numbering data are stored in nonvolatile storage by machine by the energy storage of its power capacitor；
Cycle discriminator circuit is the positive half cycle ascent stage using power network cycle, takes three to screen knowledge of the point realization to cycle signal
Do not judge, recycle the cycle time to set up lock in time, system sets clock timer and synchrotimer, if detecting phase
Two adjacent cycle signals are true, then when taking out the clock timer timing between this two adjacent cycle signal zero passages
Between, sequentially it is stored in cycle time memory cell, a cycle time is often stored in when being filled with 100 cycle time, is first removed
The cycle time being stored at first, and the average value Tz of the cycle time of deposit is calculated, differentiate cycle to be identified using Tz values
Signal；
Two comparators are respectively used to screen point 1, screen point 2, at the cycle zero passage of cycle positive half cycle ascent stage, that is, screen a little
0 set voltage zero-cross detection module, it using cycle positive half-wave signal through electric resistance partial pressure, diode further isolate negative half period,
The clock end CLK of d type flip flop is sent into after signal condition, when cycle positive half-wave zero cross signal arrives, cycle letter immediately after
Number rising edge makes d type flip flop Q ends be 0, single-chip microcomputer external interrupt mouthful low level, so as to produce interruptions, remaining two comparator divides
Cycle positive half cycle ascent stage, the examination point 1 at 35% to 50% place of crest voltage and the examination at 50% to 70% place are not arranged on
Point 2；
Cycle signal determining：Single-chip microcomputer is after setting time opens interruption, and clock timer resets and starts timing, when all wave voltages
During zero passage, the output voltage for being arranged on d type flip flop in the voltage zero-cross detection module for screening point 0 jumps vanishing, produces interruption, note
Record its zero crossing break period Th0；Hereafter, the output voltage of electricity pressure comparator ﹙ V1 ﹚ at point 1 is screened in single-chip microcomputer scanning, works as cycle
When voltage reaches electricity pressure comparator ﹙ V1 ﹚ threshold voltage, output voltage saltus step from high to low, scanning records its bound-time
Th1；Same scanning record screens electricity pressure comparator ﹙ V2 ﹚ output voltage bound-time Th2 at point 2, if the bound-time
Th1 and Th2 are in the range of allowable error, then the discriminator signal detected is true, are otherwise vacation, above-mentioned to judge discriminator signal to be true
When, calculate the clock timer between cycle signal zero passage when this cycle signal zero passage and an adjacent preceding discriminator signal are true
Timing time Tzu, it is made comparisons with the average value Tz of cycle time, all if no more than setting cycle time error Tzv
Ripple signal is true, at this moment preserves Tzu and takes 20ms to be added with synchrotimer timing time, the value deposit time synchronisation that will add up
In device；
When clock timer with cycle voltage zero-cross starts timing, then timing opens break period setting to 16ms between 18.5ms
Open interruption during value Tk, clock timer timing to 25ms to Central Shanxi Plain during pass break period setting value Tn between 27ms is broken；
When detecting first cycle voltage zero-cross, the output voltage for being arranged on the voltage zero-cross detection module for screening point 0 is jumped
Become, so as to produce interruption, the time T0 for taking out cycle voltage over zero is preserved, and clock timer is reset and starts timing, this
Shi Zhoubo time voltage crosses zeros Th0 is 0, and single-chip microcomputer scans and judges discriminator signal as stated above, its Th0, Th1 and Th2's
Value must subtract open break period setting value Tk difference plus cycle time 20ms, if three discriminator signals are true, take out
Cycle voltage over zero time T0 as initial time be stored in synchrotimer in, next time i.e. open the break period for the first time
Tk is taken, is otherwise fictitious time, now the clock timer time must be plus T0, and continuation is detected；
Then it is to take 20ms to subtract when judging cycle signal to be true when detecting first and second adjacent cycle voltage zero-cross
Th0 difference is added with synchrotimer timing time, is opened clock timer after interruption and is reset, otherwise judges cycle signal as vacation
When, now the clock timer time must be plus T1=T0+Tk, and continuation detects first cycle again as stated above, works as detection
First cycle signal be very after, recover above-described cycle signal determining；
If it is false to detect cycle signal, the break period is opened next time after this opens the break period, during through delay cycle
Between average value Tz when open interruption, and open interrupt after be delayed Tns when the Central Shanxi Plain break, it is when cycle signal is discriminated to set and close the break period
Not Wei fictitious time, the break period Tns Central Shanxi Plain is disconnected and stop scanning closing, and Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
Opened from first time after the break period takes Tk, clock timer is opened again after timing opens interruption, and clearing to Tks
Beginning timing, timing is disconnected to Central Shanxi Plain during Tns；
Said process is repeated, if the upper cycle signal detected is true, when this cycle judges, discriminator signal is vacation,
Then when clock timer timing is to Tns, the Central Shanxi Plain is broken, and is at this moment remembered and is not counted cycle N 1 and to store, and is opened the break period next time and is
The break period was opened in last time interruption is opened after Tz, clock timer is reset and timing, timing to Central Shanxi Plain during Tns after interruption is opened
It is disconnected, the cycle signal true and false is hereafter judged every time, though if false or this detection discriminator signal be false true last time, then take N, will
Restored after N+1 in memory；
When it is true to detect cycle signal, then takes out N in memory and preserve, and by N zero setting in memory, and recover using setting
Definite value Tks, at this moment takes (N+1) × 20ms value to be added in synchrotimer；
The system synchronization time be synchrotimer time, along with currently just timing clock timer time；
When judging to screen the point signal true and false, selection：The cycle discriminator signal is true when Th0, Th1, Th2 are true, or Th0 is
Very, while when one of Th1, Th2 are true, or Th1, Th2, when being true, the cycle discriminator signal is true, depending on to judging cycle letter
Depending on number true and false difference is required, if N is more than a setting value between 25 to 70, using the accumulative clocking value of clock timer
Directly it is added in synchrotimer, it is N × Tz+20ms to add up clocking value.
2. building roof control system of lamp decoration according to claim 1, it is characterised in that including:
The ﹚ of Kong Qi ﹙ 11, cycle screen 12 ﹚, Guang Gao Pai ﹙ of electricity Lu ﹙ 13 ﹚, wherein Dan Pian Ji ﹙ U0 ﹚ and 12 ﹚ of cycle examination electricity Lu ﹙ are equal
It is separately contained in each ﹚ of Kong Qi ﹙ 11；
Wherein cycle screens the ﹚ of electricity Lu ﹙ 12, by：Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian and surveys Mo Kuai ﹙ V0 ﹚, screens voltage ratio at point 1
Constituted compared with electricity pressure comparator ﹙ V2 ﹚ at device ﹙ V1 ﹚ and examination point 2, Shu Ru electricity roads ﹙ S0 ﹚ by mains AC voltage for passing through electricity
Resistance and the partial pressure of diode, are converted to voltage comparator suitably stable input voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610454640.9A CN106102227B (en) | 2016-06-20 | 2016-06-20 | Building roof control system of lamp decoration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610454640.9A CN106102227B (en) | 2016-06-20 | 2016-06-20 | Building roof control system of lamp decoration |
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| Publication Number | Publication Date |
|---|---|
| CN106102227A CN106102227A (en) | 2016-11-09 |
| CN106102227B true CN106102227B (en) | 2017-08-25 |
Family
ID=57238691
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610454640.9A Active CN106102227B (en) | 2016-06-20 | 2016-06-20 | Building roof control system of lamp decoration |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102289194A (en) * | 2011-08-19 | 2011-12-21 | 深圳和而泰智能控制股份有限公司 | Method and device for operating clock |
| CN102841247A (en) * | 2012-08-30 | 2012-12-26 | 惠州三华工业有限公司 | Detection method for grid frequency |
| DE102013220397A1 (en) * | 2013-10-10 | 2015-04-16 | Ruling Technologies Sdn. Bhd. | Method and control device for operating at least one light source |
| CN205320328U (en) * | 2015-12-19 | 2016-06-15 | 赖春梅 | High -efficient stable LED intelligence back -porch phase cut light modulator |
-
2016
- 2016-06-20 CN CN201610454640.9A patent/CN106102227B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102289194A (en) * | 2011-08-19 | 2011-12-21 | 深圳和而泰智能控制股份有限公司 | Method and device for operating clock |
| CN102841247A (en) * | 2012-08-30 | 2012-12-26 | 惠州三华工业有限公司 | Detection method for grid frequency |
| DE102013220397A1 (en) * | 2013-10-10 | 2015-04-16 | Ruling Technologies Sdn. Bhd. | Method and control device for operating at least one light source |
| CN205320328U (en) * | 2015-12-19 | 2016-06-15 | 赖春梅 | High -efficient stable LED intelligence back -porch phase cut light modulator |
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| Publication number | Publication date |
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| CN106102227A (en) | 2016-11-09 |
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Effective date of registration: 20201117 Address after: 215400 No.1 Ziwei Road, Liuhe Town, Taicang City, Suzhou City, Jiangsu Province (Hall on the second floor of high level talent entrepreneurship center) Patentee after: Suzhou milli Culture Media Technology Co.,Ltd. Address before: 350004 No. 180 Jiangbian Road, Taijiang District, Fuzhou City, Fujian Province Patentee before: FUZHOU TAIJIANG DISTRICT SUPERMAN ELECTRONICS Co.,Ltd. |