CN105845049B - Stand column L ED billboard beside expressway - Google Patents
Stand column L ED billboard beside expressway Download PDFInfo
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- CN105845049B CN105845049B CN201610447930.0A CN201610447930A CN105845049B CN 105845049 B CN105845049 B CN 105845049B CN 201610447930 A CN201610447930 A CN 201610447930A CN 105845049 B CN105845049 B CN 105845049B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
- G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
- G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
Abstract
the invention relates to a post L ED billboard beside a highway, wherein each billboard is provided with a billboard controller for controlling the lightening and color changing of an L ED lamp, each billboard is connected to the same power grid, a communication line is not needed, a main controller is not needed, and under the cooperative control of synchronous time and software of each billboard controller, various display patterns of the overall lighting effect are jointly completed, and the long-term synchronous regular display is kept.
Description
(1) technical field：
The present invention relates to the column LED billboard by a kind of highway, each billboard has billboard controller control
LED light processed is lighted and changes colour.Each billboard is connected to same power network, without communication line, without master controller.When synchronous
Between and the software collaboration control of each billboard controller under, it is common to complete the various Display patterns of overall light decorative effect, and keep
Permanent synchronous rule is shown.
(2) background technology：
The control system of power supply is provided by power network, each electronic equipment or intermodule are communicated by special circuit,
The timing time of each electronic equipment or electronic module is corrected, reaches synchronous operation purpose.Due to being made using special circuit communication
Wiring complicates and increases cost, if timing time is not corrected by line traffic, due to traditional timing error, runs number
After hour, accumulation timing error can make system control action inconsistent, may cause system crash, and at some, often change is set
Meter, its products application of the big occasion of wiring installation amount are restricted.
(3) invention content：
Using the LED light of the LED light decoration system of preset collaboration synchronous control, such as internal control mode between existing each LED light
Decorations, it is to realize synchronous control, since the timing accumulated error of conventional timing mode is big, each LED light using conventional timing mode
It can only be limited in finite time and complete whole lamp decoration styles, light decorative effect cannot be made very complicated.The present invention relates to high speeds
The column LED billboard of road constitutes display system by several column LED billboards and expresses an ad content, the advertisement
Content is made of pattern or Chinese character, and each billboard has lighting and changing colour for billboard controller control LED light.The present invention is built
It the vertical synchronization time corrected by grid cyclic wave, enables the system to keep permanent synchronization, strong antijamming capability.Each billboard is connected to together
One power network, with a power switch, without communication line, without master controller.In synchronization time and each billboard controller
It is common to complete overall light decorative effect under software collaboration control, such as gradually bright, gradually dark, various Display patterns such as beat, pile up, and
Permanent synchronous rule is kept to show.Its display pattern selects, and is one section of specific time after rigid booting, each lamp controller according to
Sequence shows and (is chased, flicker, pile up, draw curtain etc.) when different modes jointly, then selects display mould corresponding with display mode
Formula shutdown preserves, it is in the number period when can't detect grid cyclic wave signal, and microcontroller relies on the energy storage of its power capacitor
Number data are stored in nonvolatile storage.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three to screen point and realize and sentences to the identification of cycle signal
It is fixed, recycle the cycle time to establish synchronization time, the synchronous operation of each billboard controller in realization system.
The cycle discriminator circuit structural schematic diagram of each billboard controller by two as shown in Fig. 2, use hysteresis loop comparator
Voltage comparator composition, include filter circuit in each voltage comparator, the reference voltage of voltage comparator is by voltage stabilizing
Circuit provides.Clock timer and synchrotimer is arranged in system.If detect two adjacent cycle signals be it is true,
The clock timer timing time between two adjacent cycle signal zero passages is taken out, cycle time memory cell is sequentially stored in
In, which can store 100 cycle times, and a cycle time is often stored in when being filled with, and first remove most
The cycle time being first stored in, and calculate the average value Tz of the cycle time of deposit and preserve, differentiated using Tz values to be identified
Cycle signal reduces erroneous judgement possibility to reduce the influence of power network frequency fluctuation, while screen point using three.
Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.In the cycle of cycle positive half cycle ascent stage
At zero passage, that is, screen point 0 setting a voltage zero-cross detection module, it using cycle positive half-wave signal through electric resistance partial pressure, diode into
The clock end CLK of feeding d type flip flop after negative half period, signal condition is isolated in one step, and the Q of d type flip flop terminates microcontroller external interrupt
Mouthful, which is arranged to level triggers, the ends the D ground connection of d type flip flop, and S terminates single-chip processor i/o mouth, usually sets for the I/O mouthfuls
1.When cycle positive half-wave zero cross signal arrives, cycle signal rising edge immediately after makes the ends d type flip flop Q be 0, outside microcontroller
Fracture low level in portion is interrupted to generate, is executed instruction in interrupt service routine：Described I/O mouthfuls set to 0, the Central Shanxi Plain is disconnected, meter
When, described I/O mouthfuls set 1, open interruption.Remaining two comparator is separately positioned on the cycle positive half cycle ascent stage, crest voltage
The examination point 2 of the examination point 1 and 50% to 70% place at 35% to 50% place.
Cycle signal determining：For microcontroller after setting time opens interruption, clock timer resets and starts timing, works as cycle
When voltage zero-cross, the output voltage jump that the d type flip flop in the voltage zero-cross inspection survey mould block ﹙ V0 ﹚ for screening point 0 is arranged becomes zero, and produces
It is raw to interrupt, record its zero crossing break period Th0；Hereafter, the output electricity of electricity pressure comparator ﹙ V1 ﹚ at point 1 is screened in microcontroller scanning
Pressure, when all wave voltages are reached to the threshold voltage of ﹙ V1 ﹚, output voltage saltus step from high to low, scanning records its bound-time Th1；
Same scanning record screens electricity at point 2 and presses comparator ﹙ V2 ﹚ output voltage bound-time Th2, and Th0 and voltage zero-cross are detected mould
The output voltage bound-time setting value Ts0 of Kuai ﹙ V0 ﹚ makes comparisons；The output voltage bound-time of Th1 and electricity pressure comparator ﹙ V1 ﹚
Setting value Ts1 and Th2 makes comparisons respectively with the output voltage bound-time setting value Ts2 of electricity pressure comparator ﹙ V2 ﹚, if
Within the scope of allowable error, then the discriminator signal detected is true, is otherwise false.When above-mentioned judgement discriminator signal is true, calculate
When clock timer timing between cycle signal zero passage when this cycle signal zero passage and an adjacent preceding discriminator signal are true
Between Tzu, it is made comparisons with the average value Tz of cycle time, the cycle signal if no more than setting cycle time error Tzv
It is true, at this moment preserves Tzu and 20ms is taken to be added with synchrotimer timing time, in the value deposit synchrotimer that will add up.
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens the break period between 18.5ms
Open interruption when setting value Tk, clock timer timing to 25ms is disconnected to Central Shanxi Plain when pass break period setting value Tn between 27ms.
After system boot, clock timer starts timing, and when detecting first cycle voltage zero-cross, setting is being screened
The voltage zero-cross Jian of point 0 surveys the output voltage saltus step of Mo Kuai ﹙ V0 ﹚, is interrupted to generate, and takes out the time of cycle voltage over zero
T0 is preserved, and clock timer is reset to and started timing, and at this moment cycle time voltage crosses zero Th0 is 0, while microcontroller is by above-mentioned
Method scans and judges discriminator signal.What it is due to detection is first cycle, and clock timer is opened in cycle voltage zero-cross
The value of beginning timing, Th0, Th1 and Th2 must add the difference that cycle time 20ms subtracts out break period setting value Tk, such as
Three discriminator signals of fruit are true, and i.e. opening the break period for the first time takes Tk next time.Otherwise it is fictitious time, at this time clock timer time
T0 must be added, continues to detect.
When detecting first and second adjacent cycle voltage zero-cross, due to not preserving the cycle time of detection,
Therefore the clock timer timing time twice between cycle signal zero passage is made comparisons with cycle time 20ms, judges cycle signal
When being true, then takes out clock timer cumulative time T1=T0+Tk when opening interruption and be stored in synchrotimer as initial time
In, open interruption after clock timer reset, otherwise judge cycle signal be fictitious time, at this time the clock timer time must add T1,
Continue to detect first cycle again as stated above.After it is very to detect first cycle signal, restore above-described week
Wave signal determining.
As shown in Figure 1, if detecting that cycle signal is false, the break period is opened next time and opens the break period at this
Afterwards, open interruptions when average value Tz through the cycle time that is delayed, and open interrupt after be delayed Tns when the Central Shanxi Plain it is disconnected, when the setting Central Shanxi Plain is broken
Between be when cycle signal screen point 0 when do not generate interruption, at this moment must be in the setting time point more than Ts0 allowable error ranges
Start to scan, and when scanning examination point 1 and examination point 2, voltage comparator output voltage does not generate saltus step, all breaks in the Central Shanxi Plain
The time Tns Central Shanxi Plain is disconnected and stops scanning, and Tns is:
Tns=Tn-Tk
If detecting that cycle signal is true, next cycle opens break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is that timing opens interruption to Tks, and weight after resetting
New to start timing, timing is disconnected to Central Shanxi Plain when Tns, to make the synchrotimer time be corrected by cycle time voltage crosses zero.
It repeats the above process.If the upper cycle signal detected is true, when this cycle judges, discriminator signal is
Vacation, or the cycle time detected is more than setting cycle time error Tzv or clock meter compared with the average value Tz of cycle time
When device timing to close break period setting value Tns when, voltage zero-cross inspection survey the non-saltus step of mould block ﹙ V0 ﹚ output voltages, in not generating
Disconnected, then when clock timer timing is to Tns, the Central Shanxi Plain is disconnected, at this moment remembers that not counting cycle N is 1 and stores, when opening interruption next time
Between be to open the break period in last time to open interruption after Tz, hereafter every time judgement the cycle signal true and false, if false or this detection
Though discriminator signal is true but last time is false, then N is taken, will be restored after N+1 in memory, clock timer is not reset after opening interruption
Continue timing, at this moment, next cycle of setting opens the break period and temporarily uses out break period interim setting value Tkz instead：
Tkz=(N+1) × Tz
Meanwhile next cycle closes break period temporary use instead and closes break period interim setting value Tnz：
Tnz=Tkz+Tns
When clock timer to after Tkz, the time that point is screened in scanning can be obtained by simple computation.If at this moment examined
It is true to measure cycle signal, then takes out N in memory and preserve, and by N zero setting in memory, make clock timer clocking value Ts
For：(Ts-Tkz) at this moment → Ts takes the value of (N+1) × 20ms to be added in synchrotimer, and restore using setting value Tks with
Tns, recovered clock timer are reset after opening interruption.
The system synchronization time is the time of synchrotimer, along with current just in the time of the clock timer of timing.
When the point signal true and false is screened in judgement, Th0, Th1, Th2 are by being set with voltage comparator output voltage bound-time
Definite value Ts0, Ts1, Ts2 make comparisons see it is whether overproof, come judge screen point a signal true and false, can select：Th0, Th1, Th2 are
The cycle discriminator signal is true when true or Th0 is true, while when one of Th1, Th2 are true or when Th1, Th2 are true, should
Cycle discriminator signal is true, depending on requiring judgement cycle signal true and false difference.
If system fault, when N is more than a setting value between 25 to 70, due to each billboard control in system
Device, the Tz values and N values of detection may be different, at this moment, power network frequency accumulated error, may cause the synchrotimer time without
It is corrected when method is by detecting true cycle signal, when it is true to detect cycle signal, using clock timer in Tkz
The clocking value at place is directly added in synchrotimer, and to reduce the asynchronous time of system, N is remote in the case of power network normal operation
Less than 25.
The cycle time error Tzv of permission and the flip-flop transition setting value of voltage comparator output voltage, by test assessment
Its average value is taken to obtain.
(4) it illustrates：
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structural schematic diagram；
Fig. 3 is the circuit structure block diagram of the column LED billboard by highway.
(5) specific implementation mode：
Fig. 3 is the circuit structure block diagram of the column LED billboard by highway, including:11 ﹚ of billboard Kong Qi ﹙,
Cycle screens 12 ﹚ of electricity Lu ﹙, 13 ﹚ of Guang Gao Pai ﹙, and wherein cycle is screened Dan Pian Ji ﹙ U0 ﹚ in 12 ﹚ and Fig. 2 of electricity Lu ﹙ and is respectively included in
In each 11 ﹚ of billboard Kong Qi ﹙.
Fig. 2 is the structural schematic diagram that cycle screens 12 ﹚ of electricity Lu ﹙, by：Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian surveys Mo Kuai ﹙
V0 ﹚, electricity pressure comparator ﹙ V1 ﹚ and electricity pressure comparator ﹙ V2 ﹚ are constituted.Dan Pian Ji ﹙ U0 ﹚ refer to the list in each 11 ﹚ of billboard Kong Qi ﹙
Piece machine.Shu enters electricity Lu ﹙ S0 ﹚ for the partial pressure by mains AC voltage by resistance and diode, is converted to voltage comparator
Suitably stable input voltage.Single piece machine ﹙ U0 ﹚ survey mould block ﹙ V0 ﹚, electricity pressure comparator ﹙ using the inspection of 89C55WD voltage zero-cross
It is the voltage stabilizing electricity using voltage-stabiliser tube that V1 ﹚, electricity pressure comparator ﹙ V2 ﹚, which use dedicated voltage comparator LM339, reference voltage,
The threshold voltage of burning voltage comparator is carried out on road.
When mains AC voltage cycle signal zero passage, voltage zero-cross Jian surveys the output voltage saltus step of Mo Kuai ﹙ V0 ﹚, single
Pian Ji ﹙ U0 ﹚ generate interruption, record the break period, while Dan Pian Ji ﹙ U0 ﹚ are additionally operable to scanning voltage Bi compare Qi ﹙ V1 ﹚ and voltage ratio
The output voltage of compare Qi ﹙ V2 ﹚, records bound-time, for judging power network cycle signal to produce when output voltage saltus step
Raw synchronization time.
Claims (2)
1. the column LED billboard by a kind of highway, characterized in that in the software of synchronization time and each billboard controller
Common to complete overall light decorative effect under Collaborative Control, display pattern selection is one section of specific time after rigid booting, respectively
When lamp controller sequentially shows different modes jointly, selects display pattern shutdown corresponding with display mode to preserve, compiling
Number period when can't detect power network cycle signal, microcontroller by its power capacitor energy storage will number data be stored in it is non-easy
It loses in memory；
Cycle discriminator circuit is the positive half cycle ascent stage using power network cycle, takes three to screen knowledge of the point realization to cycle signal
Do not judge, recycle the cycle time to establish synchronization time, clock timer and synchrotimer is arranged in system, if detecting phase
Two adjacent cycle signals are true, then take out the clock timer timing time between two adjacent cycle signal zero passages
That is the cycle time is sequentially stored in cycle time memory cell, when being filled with 100 cycle time, is often stored in a cycle time,
The cycle time being stored at first is first removed, and calculates the average value Tz of the cycle time of deposit, is waited for using the discriminating of Tz values
Identify cycle signal；
Two comparators are respectively used to screen point 1, screen point 2, at the cycle zero passage of cycle positive half cycle ascent stage, that is, screen a little
0 setting voltage zero-cross detection module, it using cycle positive half-wave signal through electric resistance partial pressure, diode be further isolated negative half period,
The clock end CLK of d type flip flop is sent into after signal condition, when cycle positive half-wave zero cross signal arrives, cycle letter immediately after
Number rising edge makes the ends d type flip flop Q be 0, and microcontroller external interrupt mouth low level is interrupted to generate, and two comparators are set respectively
It sets in cycle positive half cycle ascent stage, the examination point 2 of the examination point 1 and 50% to 70% place at 35% to 50% place of crest voltage；
Cycle signal determining process：For microcontroller after setting time opens interruption, clock timer resets and starts timing, works as cycle
When voltage zero-cross, the output voltage jump that the d type flip flop in the voltage zero-cross detection module for screening point 0 is arranged becomes zero, in generation
It is disconnected, record zero crossing break period Th0；Hereafter, the output electricity of first voltage Bi compare Qi ﹙ V1 ﹚ at point 1 is screened in microcontroller scanning
Pressure, when all wave voltages reach first voltage than threshold voltage compared with device ﹙ V1 ﹚, output voltage saltus step from high to low, scanning record
Bound-time Th1；Same scanning record screens second voltage Bi compare Qi ﹙ V2 ﹚ output voltage bound-time Th2 at point 2, if institute
Bound-time Th1 and Th2 are stated within the scope of allowable error, then the Th1 and Th2 discriminator signals detected are true, are otherwise vacation, on
Judgement discriminator signal is stated when being true, calculates cycle signal when this cycle signal zero passage and an adjacent preceding discriminator signal are true
Clock timer timing time Tzu between zero passage makes comparisons Tzu with the average value Tz of cycle time, if no more than setting
Then cycle signal is true to cycle time error Tzv, at this moment preserves Tzu and 20ms is taken to be added with synchrotimer timing time, will
In the value deposit synchrotimer of addition；
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens break period setting between 18.5ms
Open interruption when value Tk, clock timer timing to 25ms is disconnected to Central Shanxi Plain when pass break period setting value Tn between 27ms；
When detecting first cycle voltage zero-cross, the output voltage being arranged in the voltage zero-cross detection module for screening point 0 is jumped
Becoming, is interrupted to generate, time T0 for taking out cycle voltage over zero preserves, and clock timer is reset to and started timing, this
When week wave voltage zero crossing break period Th0 be 0, microcontroller scans and judges that discriminator signal, the value of Th0, Th1 and Th2 are equal
The difference that break period setting value Tk must be subtracted open plus cycle time 20ms is examined next time if three discriminator signals are true
The break period of opening for surveying cycle voltage over zero takes Tk, is otherwise fictitious time there are one discriminator signal, at this time the clock timer time
T0 must be added, continues to detect；
When it is true to detect first and second adjacent cycle voltage zero-cross, judgement cycle signal, then takes out and open interruption
When clock timer cumulative time T1=T0+Tk as initial time be stored in synchrotimer in, open interruption after clock timing
Device reset, otherwise judge cycle signal be fictitious time, at this time the clock timer time must add T1, again detect first cycle,
After it is very to detect first cycle signal, restore above-described cycle signal determining；
If detecting that cycle signal is false, the break period is opened next time after this opens the break period, when through delay cycle
Between average value Tz when open interruption, and open interrupt after be delayed Tns when the Central Shanxi Plain it is disconnected, it is when cycle signal is discriminated that the break period is closed in setting
Not Wei fictitious time, the break period Tns Central Shanxi Plain is disconnected and stop scanning, and Tns is closing:
Tns=Tn-Tk
If detecting that cycle signal is true, next cycle opens break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is that timing opens interruption to Tks, and is opened again after resetting
Beginning timing, timing are disconnected to Central Shanxi Plain when Tns；
Above-mentioned cycle signal determining process is repeated, if the upper cycle signal detected is true, when this cycle judges, is discriminated
Level signal is false, then when clock timer timing is to Tns, the Central Shanxi Plain is disconnected, at this moment remembers that cycle N is 1 and stores, open next time in
The disconnected time is to open the break period in last time to open interruption after Tz, hereafter every time judgement the cycle signal true and false, if false or this
Though detection discriminator signal is true but last time is false, then stored N is taken out, and will be restored in the memory of storage N after N+1,
Clock timer open interrupt after do not reset continuation timing, at this moment, next cycle of setting is opened during the break period temporarily uses instead open
The disconnected time interim setting value Tkz：
Tkz=(N+1) × Tz
Meanwhile next cycle closes break period temporary use instead and closes break period interim setting value Tnz：
Tnz=Tkz+Tns
When clock timer to after Tkz, if at this moment detecting that cycle signal is true, takes out N in memory and preserve, and
By N zero setting in memory, the clock timer clocking value Ts is set to be：First calculate Ts-Tkz again with results modification Ts values are calculated, at this moment
It takes the value of (N+1) × 20ms to be added in synchrotimer, and restores that setting value Tks and Tns, recovered clock timer is used to open
It is reset after interruption；
The system synchronization time is the time of synchrotimer, along with current just in the time of the clock timer of timing；
And it selects：Cycle discriminator signal is true when Th0, Th1, Th2 are true or Th0 is true, while one of Th1, Th2 are
When true or when Th1, Th2 are true, cycle discriminator signal is true, if N is more than a setting value between 25 to 70, is used
Clocking value of the clock timer at Tkz is directly added in synchrotimer.
2. the column LED billboard by highway according to claim 1, it is characterised in that including:
11 ﹚ of billboard Kong Qi ﹙, cycle screen 12 ﹚ of electricity Lu ﹙, 13 ﹚ of Guang Gao Pai ﹙, and wherein Dan Pian Ji ﹙ U0 ﹚ and cycle screen electricity
12 ﹚ of Lu ﹙ are respectively included in each 11 ﹚ of billboard Kong Qi ﹙；
Cycle screens 12 ﹚ of electricity Lu ﹙, by：Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian surveys Mo Kuai ﹙ V0 ﹚, screens first voltage ratio at point 1
Compare Qi ﹙ V1 ﹚ are constituted with second voltage Bi compare Qi ﹙ V2 ﹚ at point 2 are screened, and wherein Shu enters electricity Lu ﹙ S0 ﹚ for mains AC is electric
Pressure is converted to the suitably stable input voltage of voltage comparator by the partial pressure of resistance and diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610447930.0A CN105845049B (en) | 2016-06-20 | 2016-06-20 | Stand column L ED billboard beside expressway |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610447930.0A CN105845049B (en) | 2016-06-20 | 2016-06-20 | Stand column L ED billboard beside expressway |
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| Publication Number | Publication Date |
|---|---|
| CN105845049A CN105845049A (en) | 2016-08-10 |
| CN105845049B true CN105845049B (en) | 2018-10-23 |
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| Application Number | Title | Priority Date | Filing Date |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270419A (en) * | 2010-06-07 | 2011-12-07 | 张广涵 | LED (light-emitting diode) display system based on power network |
| CN102708808A (en) * | 2012-06-18 | 2012-10-03 | 深圳Tcl新技术有限公司 | Method and circuit for driving backlight light emitting diode (LED) lamp of television, and television |
| KR20140022234A (en) * | 2012-08-13 | 2014-02-24 | 주식회사 오로라 | Led electric lighting board having dual mode |
-
2016
- 2016-06-20 CN CN201610447930.0A patent/CN105845049B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102270419A (en) * | 2010-06-07 | 2011-12-07 | 张广涵 | LED (light-emitting diode) display system based on power network |
| CN102708808A (en) * | 2012-06-18 | 2012-10-03 | 深圳Tcl新技术有限公司 | Method and circuit for driving backlight light emitting diode (LED) lamp of television, and television |
| KR20140022234A (en) * | 2012-08-13 | 2014-02-24 | 주식회사 오로라 | Led electric lighting board having dual mode |
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| Publication number | Publication date |
|---|---|
| CN105845049A (en) | 2016-08-10 |
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