CN105911931B - A kind of rainwater discharge record system - Google Patents
A kind of rainwater discharge record system Download PDFInfo
- Publication number
- CN105911931B CN105911931B CN201610454885.1A CN201610454885A CN105911931B CN 105911931 B CN105911931 B CN 105911931B CN 201610454885 A CN201610454885 A CN 201610454885A CN 105911931 B CN105911931 B CN 105911931B
- Authority
- CN
- China
- Prior art keywords
- cycle
- time
- voltage
- signal
- true
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/23—Pc programming
- G05B2219/23009—Automatic documentation of program
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Measurement Of Unknown Time Intervals (AREA)
Abstract
The present invention relates to a kind of rainwater discharge record systems, the system is made of multiple flowmeters and a master controller, each flowmeter includes a plug-in type flow transducer, the heavy rain rainwater flow of one position of long term monitoring, the rainwater flow signal of cmf record synchronization time and its acquisition is converted into digital signal, convenient for determining the rainwater discharge capacity of certain time point each position floss hole, and send master controller processing in the synchronization time of setting.
Description
(1) technical field：
The present invention relates to a kind of rainwater discharge record system, which is made of multiple flowmeters and a master controller,
Each flowmeter includes a plug-in type flow transducer, the heavy rain rainwater flow of one position of long term monitoring, cmf record
The rainwater flow signal of synchronization time and its acquisition is converted into digital signal, convenient for determining the rain of certain time point each position floss hole
Water discharge capacity, and send master controller processing in the synchronization time of setting.
(2) background technology：
The control system of power supply is provided by power network, each electronic equipment or intermodule are communicated by special circuit,
The timing time of each electronic equipment or electronic module is corrected, reaches synchronous operation purpose.Due to being made using special circuit communication
Wiring complicates and increases cost, if timing time is not corrected by line traffic, due to traditional timing error, runs number
After hour, accumulation timing error can make system control action inconsistent, may cause system crash, and at some, often change is set
Meter, its products application of the big occasion of wiring installation amount are restricted.
(3) content of the invention：
The present invention relates to a kind of rainwater discharge record systems.Summer city often suddenly rains cats and dogs in a small range moment, drop
Rain process rainwater along the horizontal plane, is flowed into the municipal Storm Sewer Network of rainwater on road surface floss hole access by vacant lot or road, then passed through
Floss hole is discharged into river.It is attacked since rainwater on road surface floss hole and Storm Sewer Network layout can not accommodate heavy rain, causes city office
Portion's flood for reasonable placement rainwater on road surface floss hole, and passes through landscape construction and grass planting makes the measures such as depression it is necessary to reality
Shi Jilu rainwater is discharged into the rainwater discharge capacity of each floss hole in river, and statistics each position is to heavy rain rainwater discharge capacity.
The system is made of multiple flowmeters and a master controller, and each flowmeter includes a plug-in type flow and senses
The rainwater flow signal of device, the heavy rain rainwater flow of one position of long term monitoring, cmf record synchronization time and its acquisition turns
It changes digital signal into, sends master controller processing in the synchronization time of setting, using record synchronization time convenient for the definite some time
Between put each position floss hole rainwater discharge capacity.Each flowmeter and master controller are connected on same electric power cable and set total
Switch installs an electronic switch after master switch, and master controller AC power is connected between electronic switch and master switch, and
One communications electronics switch, the AC power of each flowmeter are respectively installed in the telecommunication circuit of master controller and each flowmeter
Input terminal sets insulating electron to switch.In the communication synchronization time of setting, master controller shut-off electronic switch simultaneously connects its communication
Electronic switch, each flowmeter are connected each logical also in the synchronization time of the communication of setting or when not receiving grid cyclic wave signal
Believe electronic switch, shut-off insulating electron switch is communicated by electric power cable, after sign off, turns off all communications electronics switches,
Electronic switch and insulating electron switch are connected again, and at this moment, synchrotimer restarts timing after resetting and corrected, to protect
System synchronization is held, and remembers the accumulated value of time synchronisation.Communication period relies on and is connected to the chargeable of microcontroller power supply filter capacitor
Battery powered, and isolate through diode with former rectification circuit, the charging circuit of rechargeable battery possesses charging protection function.
The panel of each flowmeter is equipped with 3 to 5 LED modules with different colors lamps, and each color represents different numerical value, sets of numbers
Conjunction is corresponding with the number numbered, and one section setting time of the flowmeter after individually just start sequentially shows different number difference face
Color LED light, shutdown obtains corresponding number and preserves, then labels knowledge, it is to work as to can't detect grid cyclic wave in the number period
During signal, number data are stored in nonvolatile storage by microcontroller by the energy storage of its power capacitor.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three to screen point and realize and the identification of cycle signal is sentenced
It is fixed, the cycle time is recycled to establish synchronization time, the long-time of master controller and each flowmeter is run simultaneously in realization system.
The cycle identification circuit of master controller and each flowmeter is as shown in Fig. 2, by three voltage using hysteresis loop comparator
Comparator forms, and comprising filter circuit in each voltage comparator, the reference voltage of voltage comparator is carried by regulator circuit
For.System sets clock timer and synchrotimer.If it is true to detect two adjacent cycle signals, taking out should
Clock timer timing time between two adjacent cycle signal zero passages is sequentially stored in cycle time memory cell, should
Cycle time memory cell can store 100 cycle times, and a cycle time is often stored in when being filled with, first removes and is stored at first
A cycle time, and calculate the average value Tz of the cycle time of deposit and preserve, Tz values is utilized to differentiate cycle letter to be identified
Number, reduce erroneous judgement possibility to reduce the influence of power network frequency fluctuation, while point is screened using three.
Three comparators are respectively used to three examination points, that is, screen point 0, screen point 1, screen point 2, as shown in Figure 1.In week
At the cycle zero passage of ripple positive half cycle ascent stage, that is, screen point 0 and voltage zero-crossing comparator is set, remaining two comparator is set respectively
In the cycle positive half cycle ascent stage, the examination point 1 at 35% to 50% place of crest voltage and the examination point 2 at 50% to 70% place.
Cycle signal determining：After setting time opens interruption, clock timer resets and starts timing microcontroller, works as cycle
During voltage zero-cross, the output voltage overturning for the voltage zero-crossing comparator V0 for screening point 0 is arranged on, in the generation of its voltage trailing edge
It is disconnected, it records its zero crossing break period Th0 and the Central Shanxi Plain is broken；Hereafter, the output of voltage comparator V1 at point 1 is screened in microcontroller scanning
Voltage, when all wave voltages reach the threshold voltage of V1, output voltage is overturn from high to low, and scanning records its flip-flop transition Th1；
Similary scanning record screens voltage comparator V2 output voltage flip-flop transition Th2 at point 2, by Th0 and voltage zero-crossing comparator V0
Output voltage flip-flop transition setting value Ts0 make comparisons；The output voltage flip-flop transition setting value of Th1 and voltage comparator V1
Ts1 and Th2 makes comparisons respectively with the output voltage flip-flop transition setting value Ts2 of voltage comparator V2, if in allowable error
In the range of, then the discriminator signal detected is true, is otherwise false.When above-mentioned judgement discriminator signal is true, this cycle is calculated
The clock timer timing time Tzu between cycle signal zero passage when signal zero passage and an adjacent preceding discriminator signal are true, will
It makes comparisons with the average value Tz of cycle time, and cycle signal is true if being no more than and setting cycle time error Tzv, at this moment
It preserves Tzu and 20ms is taken to be added with synchrotimer timing time, in the value deposit synchrotimer that will add up.
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens the break period between 18.5ms
Open interruption during setting value Tk, clock timer timing to 25ms to Central Shanxi Plain during pass break period setting value Tn between 27ms is broken.
After system boot, clock timer starts timing, when detecting first cycle voltage zero-cross, is arranged on examination
The output voltage overturning of the voltage zero-crossing comparator V0 of point 0, is interrupted so as to generate, and the time T0 for taking out cycle voltage over zero is protected
It deposits, clock timer is reset and starts timing, at this moment cycle time voltage crosses zero Th0 is 0, while microcontroller is as stated above
It scans and judges discriminator signal.What it is due to detection is first cycle, and clock timer is to start to count in cycle voltage zero-cross
When, the value of Th0, Th1 and Th2 must add the difference that cycle time 20ms subtracts out break period setting value Tk, if three
A discriminator signal is true, and the time T0 of the cycle voltage over zero of taking-up is stored in as initial time in synchrotimer, next
It is secondary that i.e. opening the break period for the first time takes Tk.Otherwise for fictitious time, at this time the clock timer time must add T0, continue to detect.
When detecting first and second adjacent cycle voltage zero-cross, due to not preserving the cycle time of detection,
Therefore the clock timer timing time twice between cycle signal zero passage is made comparisons with cycle time 20ms, judges cycle signal
Then it is that the difference that 20ms is taken to subtract Th0 is added with synchrotimer timing time when being true, i.e., preserves the standard cycle time for the first time
20ms need to deduct its Th0 value, this is because when hereafter to detect cycle signal every time be true, by clock meter when opening interruption
When device reset after restart timing, and be that the standard cycle time is included in synchrotimer when opening interruption, open interruption
Afterwards clock timer reset, otherwise judge cycle signal be fictitious time, at this time the clock timer time must add T1=T0+Tk, after
It is continuous to detect first cycle again as stated above.After it is very to detect first cycle signal, recover above-described cycle
Signal determining.
If as shown in Figure 1, detecting that cycle signal is false, the break period is opened next time and opens the break period at this
Afterwards, open interruptions during average value Tz through the cycle time that is delayed, and open interrupt after be delayed Tns when the Central Shanxi Plain break, when setting the Central Shanxi Plain to break
Between be when cycle signal screen point 0 when do not generating interruption, at this moment must be in the setting time point more than Ts0 allowable error scopes
When starting to scan and scanning examination point 1 and screen point 2, voltage comparator output voltage does not generate overturning, all breaks in the Central Shanxi Plain
Scanning is broken and is stopped in the time Tns Central Shanxi Plain, and Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is that timing opens interruption to Tks, and weight after resetting
New to start timing, timing is broken to Central Shanxi Plain during Tns, so that the synchrotimer time is corrected be subject to cycle time voltage crosses zero.
It repeats the above process.If the upper cycle signal detected is true, when this cycle judges, discriminator signal is
Vacation or the cycle time detected are more than setting cycle time error Tzv or clock meter compared with the average value Tz of cycle time
When device timing to close break period setting value Tns when, voltage zero-crossing comparator V0 output voltages are not overturn, do not generate interruption,
Then when clock timer timing is to Tns, the Central Shanxi Plain is broken, and is at this moment remembered and is not counted cycle N 1 and to store, and is opened the break period next time and is
The break period was opened in last time, interruption is opened after Tz, hereafter judge the cycle signal true and false every time, if false or this detection is screened
Though signal is true but last time is false, then N is taken, will be restored after N+1 in memory, clock timer does not reset continuation after interruption is opened
Timing, at this moment, next cycle of setting open the break period and temporarily use out break period interim setting value Tkz instead：
Tkz=(N+1) × Tz
Meanwhile next cycle closes break period temporary use instead and closes break period interim setting value Tnz：
Tnz=Tkz+Tns
When clock timer to after Tkz, the time that point is screened in scanning can be obtained by simple computation.If it at this moment examines
It is true to measure cycle signal, then takes out in memory N and preserve, and by N zero setting in memory, makes clock timer clocking value Ts
For：(Ts-Tkz) at this moment → Ts takes the value of (N+1) × 20ms to be added in synchrotimer, and recover using setting value Tks with
Tns, recovered clock timer are reset after interruption is opened.
The system synchronization time be synchrotimer time, along with currently just timing clock timer time.
When judging to screen the point signal true and false, Th0, Th1, Th2 are by being set with voltage comparator output voltage flip-flop transition
Definite value Ts0, Ts1, Ts2 make comparisons see it is whether overproof, come judge screen point a signal true and false, can select：Th0, Th1, Th2 are
The cycle discriminator signal is true when true or Th0 is true, while when one of Th1, Th2 are true or when Th1, Th2 are true, it should
Cycle discriminator signal is true, depending on to judging the different requirements of the cycle signal true and false.
If system fault, when N is more than a setting value between 25 to 70, due to master controller in system and each stream
Gauge, Tz values and the N values of detection may be different, and at this moment, power network frequency accumulated error may cause the synchrotimer time
It is corrected when can not be by detecting true cycle signal, when it is true to detect cycle signal, is existed using clock timer
Clocking value at Tkz is directly added in synchrotimer, to reduce the asynchronous time of system, in the case of power network normal operation
N is much smaller than 25.
The cycle time error Tz of permissionvWith the flip-flop transition setting value of voltage comparator output voltage, by test assessment
Its average value is taken to obtain.
(4) illustrate：
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structure diagram；
Fig. 3 is a kind of circuit structure block diagram of rainwater discharge record system.
(5) specific embodiment：
Fig. 3 is a kind of circuit structure block diagram of rainwater discharge record system, including:10 ﹚ of Zhu Kong Qi ﹙, communications electronics
11 ﹚ of Kai Guan ﹙, cycle screen 12 ﹚ of electricity Lu ﹙, 13 ﹚ of Liu Liang Ji ﹙, 14 ﹚ of plug-in type Liu amount Chuan Gan Qi ﹙, 15 ﹚ of electricity Kai Guan ﹙, wherein week
Ripple is screened Dan Pian Ji ﹙ U0 ﹚ in 12 ﹚ and Fig. 2 of electricity Lu ﹙ and is respectively included in 13 ﹚ of Liu Liang Ji ﹙ and 10 ﹚ of Zhu Kong Qi ﹙；
Fig. 2 is the structure diagram that cycle screens 12 ﹚ of electricity Lu ﹙, by：Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian and surveys Mo Kuai ﹙
V0 ﹚, electricity pressure comparator ﹙ V1 ﹚ and electricity pressure comparator ﹙ V2 ﹚ are formed.Dan Pian Ji ﹙ U0 ﹚ refer to 13 ﹚ of Liu Liang Ji ﹙ and 10 ﹚ of Zhu Kong Qi ﹙
In microcontroller.Shu enters electricity Lu ﹙ S0 ﹚ for the partial pressure by mains AC voltage by resistance and diode, is converted to voltage
The suitably stable input voltage of comparator.Dan Pian Ji ﹙ U0 ﹚ survey Mo Kuai ﹙ V0 ﹚ using 89C55WD voltage zero-cross Jian, voltage compares
Using dedicated voltage comparator LM339, reference voltage is the voltage stabilizing using voltage-stabiliser tube by device ﹙ V1 ﹚, electricity pressure comparator ﹙ V2 ﹚
Circuit carrys out the threshold voltage of burning voltage comparator；
When mains AC voltage cycle signal zero passage, voltage zero-cross Jian surveys the output voltage saltus step of Mo Kuai ﹙ V0 ﹚, single
Pian Ji ﹙ U0 ﹚ generate interruption, record the break period, while Dan Pian Ji ﹙ U0 ﹚ are additionally operable to scanning voltage Bi compare Qi ﹙ V1 ﹚ and voltage ratio
The output voltage of compare Qi ﹙ V2 ﹚, bound-time is recorded when output voltage saltus step, for judging power network cycle signal so as to producing
Raw synchronization time.
Claims (2)
1. a kind of rainwater discharge record system, it is characterized in that, an electronic switch, master controller exchange are installed after master switch
Power supply is connected between electronic switch and master switch, and is respectively installed one in the telecommunication circuit of master controller and each flowmeter and led to
Believe electronic switch, the ac power input end of each flowmeter sets insulating electron to switch；Each flowmeter is in the communication of setting
It synchronization time or when not receiving grid cyclic wave signal, is communicated by electric power cable, after sign off, after synchrotimer is reset
Restart timing and corrected, to keep system synchronization, and remember the accumulated value of time synchronisation, communication period is relied on and is connected to
The rechargeable battery power supply of microcontroller power supply filter capacitor；The heavy rain rainwater flow of each one position of flowmeter long term monitoring,
Cmf record synchronization time and its rainwater flow signal of acquisition, and sent in the synchronization time of setting at master controller
Reason, equipped with 3 to 5 LED modules with different colors lamps, each color represents different numerical value, sequentially shows difference the panel of each flowmeter
Quantity LED modules with different colors lamp, shutdown obtain corresponding number and preserve, and work as in the number period and can't detect grid cyclic wave signal
When, number data are stored in nonvolatile storage by microcontroller by the energy storage of its power capacitor；
Using the positive half cycle ascent stage of power network cycle, take three to screen identification decision of the point realization to cycle signal, recycle
The cycle time establishes synchronization time, and the cycle identification circuit of master controller and each flowmeter is by three electricity using hysteresis loop comparator
Comparator composition is pressed, system sets clock timer and synchrotimer, if detecting that two adjacent cycle signals are
Very, then the clock timer timing time i.e. cycle time between this two adjacent cycle signal zero passages is taken out, is sequentially stored in
A cycle time is often stored in cycle time memory cell, when being filled with 100 cycle time, first removes one be stored at first
A cycle time, and calculate the average value Tz of the cycle time of deposit and preserve differentiates cycle signal to be identified using Tz values, three
A comparator is respectively used to three examination points, that is, screens point 0, screen point 1, screen point 2, in the cycle of cycle positive half cycle ascent stage
At zero passage, that is, to screen point 0 and voltage zero-crossing comparator is set, remaining two comparator is separately positioned on the cycle positive half cycle ascent stage,
The examination point 1 at 35% to 50% place of crest voltage and the examination point 2 at 50% to 70% place；
Cycle signal determining process：After setting time opens interruption, clock timer resets and starts timing microcontroller, works as cycle
During voltage zero-cross, the output voltage overturning for the voltage Zero-cross comparator Qi ﹙ V0 ﹚ for screening point 0 is arranged on, is generated in its voltage trailing edge
It interrupts, records its zero crossing break period Th0 and the Central Shanxi Plain is broken；Hereafter, first voltage Bi compare Qi ﹙ at point 1 are screened in microcontroller scanning
The output voltage of V1 ﹚, when all wave voltages reach first voltage than threshold voltage compared with device ﹙ V1 ﹚, output voltage turns over from high to low
Turn, scanning records its flip-flop transition Th1；Similary scanning record screens second voltage Bi compare Qi ﹙ V2 ﹚ output voltages overturning at point 2
Time Th2, if above-mentioned flip-flop transition Th1 and Th2 in the range of allowable error, detects at examination point 1 and screen point 2
The discriminator signal at place is true, is otherwise vacation, when above-mentioned judgement discriminator signal is true, calculates this cycle signal zero passage and phase
The clock timer timing time Tzu between cycle signal zero passage when a discriminator signal is true before neighbour, by itself and cycle time
Average value Tz make comparisons, to be true, at this moment preservation Tzu and taken if no more than cycle signal if set cycle time error Tzv
20ms is added with synchrotimer timing time, in the value deposit synchrotimer that will add up；
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens break period setting between 18.5ms
Open interruption during value Tk, clock timer timing to 25ms to Central Shanxi Plain during pass break period setting value Tn between 27ms is broken；
After system boot, clock timer starts timing, when detecting first cycle voltage zero-cross, is arranged on examination point 0
Voltage Zero-cross comparator Qi ﹙ V0 ﹚ output voltage overturning, so as to generate interrupt, take out cycle voltage over zero time T0 protect
It deposits, clock timer is reset and starts timing, at this moment cycle time voltage crosses zero Th0 is 0, while microcontroller is scanned and judged
Discriminator signal, the value of Th0, Th1 and Th2 must add the difference that cycle time 20ms subtracts out break period setting value Tk,
If three discriminator signals are true, the time T0 of the cycle voltage over zero of taking-up is stored in synchrotimer as initial time
In, the break period of opening for detecting cycle voltage over zero next time takes Tk, is otherwise fictitious time there are one discriminator signal, at this time clock
Timer periods must add T0, continue to detect；
When detecting first and second adjacent cycle voltage zero-cross, due to not preserving the cycle time of detection,
The clock timer timing time between cycle signal zero passage is made comparisons with cycle time 20ms twice, judges that cycle signal is true
When, then it is that the difference that 20ms is taken to subtract Th0 is added with synchrotimer timing time, clock timer is reset after opening interruption, otherwise
Judge cycle signal be fictitious time, at this time the clock timer time must add T1, T1=T0+Tk, again detect first cycle, when
Detection first cycle signal be very after, recover above-described cycle signal determining；
If it is false to detect cycle signal, open the break period next time after this opens the break period, through be delayed cycle when
Between average value Tz when open interruption, and open interrupt after be delayed Tns when the Central Shanxi Plain break, it is when cycle signal exists to set and close the break period
It screens as fictitious time, breaks and stops to scan closing the break period Tns Central Shanxi Plain, Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is that timing opens interruption to Tks, and is opened again after resetting
Beginning timing, timing are broken to Central Shanxi Plain during Tns, repeat above-mentioned cycle signal determining process, if the upper cycle letter detected
Number it is true, when this cycle judges, discriminator signal is that the average value Tz of cycle time that is false or detecting and cycle time are relatively super
When crossing setting cycle time error Tzv or clock timer timing to pass break period setting value Tns, voltage Zero-cross comparator device ﹙
V0 ﹚ output voltages are not overturn, do not generate interruption, then when clock timer timing is to Tns, the Central Shanxi Plain is broken, and at this moment remember cycle N
1 and to store, it is to open the break period in last time to open interruption after Tz to open the break period next time, hereafter judges cycle letter every time
Number true and false, though if false or this detection discriminator signal be false true last time, then take out stored N, and will be restored after N+1
In the memory of storage N, clock timer open interrupt after do not reset continuation timing, at this moment, during next cycle of setting is opened
The disconnected time temporarily uses out break period interim setting value Tkz instead：
Tkz=(N+1) × Tz
Meanwhile next cycle closes break period temporary use instead and closes break period interim setting value Tnz：
Tnz=Tkz+Tns
When clock timer to after Tkz, if at this moment detecting that cycle signal is true, take out N in memory and preserve, and
By N zero setting in memory, the clock timer clocking value Ts is set to be：Ts-Tkz is first calculated again with results modification Ts values are calculated, at this moment
The value of (N+1) × 20ms is taken to be added in synchrotimer, and is recovered using setting value Tks and Tns, recovered clock timer is being opened
It is reset after interruption,
The system synchronization time be synchrotimer time, along with currently just timing clock timer time；
And it selects：Cycle discriminator signal is true when Th0, Th1, Th2 are true or Th0 is true, while one of Th1, Th2 are
When true or when Th1, Th2 are true, cycle discriminator signal is true；
When N is more than a setting value between 25 to 70, synchronometer is directly added on using clocking value of the clock timer at Tkz
When device in.
2. a kind of rainwater discharge record system according to claim 1, it is characterised in that including:
10 ﹚ of Zhu Kong Qi ﹙, 11 ﹚ of communications electronics Kai Guan ﹙, cycle screen 12 ﹚ of electricity Lu ﹙, 13 ﹚ of Liu Liang Ji ﹙, plug-in type flow sensing
14 ﹚ of Qi ﹙, 15 ﹚ of electricity Kai Guan ﹙, wherein cycle screen 12 ﹚ and Dan Pian Ji ﹙ U0 ﹚ of electricity Lu ﹙ be respectively included in 13 ﹚ of Liu Liang Ji ﹙ with
In 10 ﹚ of Zhu Kong Qi ﹙；
Wherein cycle screens 12 ﹚ of electricity Lu ﹙, by：Shu enters electricity Lu ﹙ S0 ﹚, voltage Zero-cross comparator Qi ﹙ V0 ﹚, screens first voltage at point 1
Bi compare Qi ﹙ V1 ﹚ are formed with second voltage Bi compare Qi ﹙ V2 ﹚ at point 2 are screened, and wherein Shu enters electricity Lu ﹙ S0 ﹚ and is used for mains AC
Voltage is converted to the suitably stable input voltage of voltage comparator by the partial pressure of resistance and diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610454885.1A CN105911931B (en) | 2016-06-20 | 2016-06-20 | A kind of rainwater discharge record system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610454885.1A CN105911931B (en) | 2016-06-20 | 2016-06-20 | A kind of rainwater discharge record system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105911931A CN105911931A (en) | 2016-08-31 |
| CN105911931B true CN105911931B (en) | 2018-05-22 |
Family
ID=56758218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610454885.1A Active CN105911931B (en) | 2016-06-20 | 2016-06-20 | A kind of rainwater discharge record system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105911931B (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1876977A (en) * | 2006-06-27 | 2006-12-13 | 林万泉 | Water flow quality-divided discharge method for urban river rain and sewage mixed flow pipe network |
| WO2008111492A1 (en) * | 2007-03-07 | 2008-09-18 | Japan Agency For Marine-Earth Science And Technology | Rain gauge and rain gauge data calculation storage device |
| JP2010196369A (en) * | 2009-02-25 | 2010-09-09 | Toshiba Corp | Rainwater drainage control device |
| CN102331282A (en) * | 2011-08-30 | 2012-01-25 | 中国林业科学研究院 | Leakage test recorder for soil deep water yield |
| CN103984320A (en) * | 2014-05-23 | 2014-08-13 | 杭州银江环保科技有限公司 | System and method for monitoring enterprise rainwater drainage outlets based on internet of things |
-
2016
- 2016-06-20 CN CN201610454885.1A patent/CN105911931B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1876977A (en) * | 2006-06-27 | 2006-12-13 | 林万泉 | Water flow quality-divided discharge method for urban river rain and sewage mixed flow pipe network |
| WO2008111492A1 (en) * | 2007-03-07 | 2008-09-18 | Japan Agency For Marine-Earth Science And Technology | Rain gauge and rain gauge data calculation storage device |
| JP2010196369A (en) * | 2009-02-25 | 2010-09-09 | Toshiba Corp | Rainwater drainage control device |
| CN102331282A (en) * | 2011-08-30 | 2012-01-25 | 中国林业科学研究院 | Leakage test recorder for soil deep water yield |
| CN103984320A (en) * | 2014-05-23 | 2014-08-13 | 杭州银江环保科技有限公司 | System and method for monitoring enterprise rainwater drainage outlets based on internet of things |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105911931A (en) | 2016-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106094620A (en) | Remote analog amount gathers warning system | |
| CN105931414B (en) | A kind of Warehouse Fire alarm control system | |
| CN105894789B (en) | The Automatic meter reading system of tap water supply pipe network | |
| CN105911931B (en) | A kind of rainwater discharge record system | |
| CN106092152B (en) | A kind of warehouse humiture information acquisition system | |
| CN106123985B (en) | A kind of flow signal synchronous | |
| CN106227078B (en) | Rainstorm flood discharge recording system | |
| CN106100782B (en) | A kind of signal synchronous collection system | |
| CN105960060B (en) | Park L ED landscape lamp post control system | |
| CN105869538B (en) | Road roadside LED Chinese character advertisement placards | |
| CN106023570B (en) | Automatic meter reading system for tap water supply pipe network | |
| CN106102227B (en) | Building roof control system of lamp decoration | |
| CN106089782B (en) | Parlor fan natural wind control system | |
| CN106061017B (en) | Building LED guardrail tube clearance light decoration system | |
| CN106102226B (en) | Restaurant LED point light source control system of lamp decoration | |
| CN105848371B (en) | Household exempts from the LED decorative lamp controller of wiring | |
| CN106028524B (en) | Exempt from the LED light decorations control system of wiring in a kind of interior | |
| CN106125594B (en) | Hotel intelligence control system | |
| CN106054710B (en) | eating house intelligent control system | |
| CN106154031A (en) | Factory Electric Power information acquisition system | |
| CN106023501A (en) | Warehouse environment information collection alarm system | |
| CN106102225B (en) | Bridge guardrail pipe control system of lamp decoration | |
| CN105869543B (en) | The column LED Chinese character placards of both sides of the road | |
| CN105845049B (en) | Stand column L ED billboard beside expressway | |
| CN106097683B (en) | Distribution electric quantity parameter acquisition system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20180403 Address after: 350208 Shop No. 4, building materials market, building materials market, Fuzhou, Changle District, Changle District, Changle District Applicant after: Fuzhou alignment Mdt InfoTech Ltd Address before: 350004 Taijiang, Fujian District, Riverside Road, No., No. 180 Applicant before: Fuzhou Taijiang Chaoren Electronic Co., Ltd. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201117 Address after: No.39, Weinan group, Gaolou village, Liangji Town, Suining County, Xuzhou City, Jiangsu Province, 221000 Patentee after: XUZHOU JUYUAN ENVIRONMENTAL PROTECTION TECHNOLOGY Co.,Ltd. Address before: 350208 Shop No. 4, building materials market, building materials market, Fuzhou, Changle District, Changle District, Changle District Patentee before: FUZHOU ZHUNDIAN INFORMATION TECHNOLOGY Co.,Ltd. |