CN106123985B - A kind of flow signal synchronous - Google Patents
A kind of flow signal synchronous Download PDFInfo
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- CN106123985B CN106123985B CN201610447964.XA CN201610447964A CN106123985B CN 106123985 B CN106123985 B CN 106123985B CN 201610447964 A CN201610447964 A CN 201610447964A CN 106123985 B CN106123985 B CN 106123985B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
- G01F15/00—Details of, or accessories for, apparatus of groups G01F1/00 - G01F13/00 insofar as such details or appliances are not adapted to particular types of such apparatus
Abstract
The present invention relates to a kind of flow signal synchronous, are made of multiple flowmeters and a main controller, and synchronization time and its fluid flow rate signal of measurement are converted into digital signal through A/D and send main controller processing to by each flowmeter.It is communicated between flowmeter by electric power cable, communication period flowmeter is by the rechargeable battery power supply for being connected to microcontroller power supply filter capacitor.
Description
(1) technical field:
The present invention relates to a kind of flow signal synchronous, are made of multiple flowmeters and a main controller,
Synchronization time and its fluid flow rate signal of measurement are converted into digital signal through A/D and send master control to by each flowmeter
Device processing.It is communicated between flowmeter by electric power cable, communication period flowmeter relies on and is connected to microcontroller power supply
The rechargeable battery of filter capacitor is powered.
(2) background technique:
The control system of power supply is provided by power network, each electronic equipment or intermodule are communicated by special circuit,
The timing time of each electronic equipment or electronic module is corrected, reaches synchronous operation purpose.Due to being made using special circuit communication
Wiring complicates and increases cost, if timing time is not corrected by line traffic, due to traditional timing error, runs number
After hour, accumulation timing error can make system control action inconsistent, may cause system crash, set in some frequent changes
Meter, its products application of the big occasion of wiring installation amount are restricted.
(3) summary of the invention:
The present invention relates to a kind of flow signal synchronous, are made of multiple flowmeters and a main controller,
Each flowmeter includes one or several flowmeters, measures the fluid flow of a position, and by synchronization time and its survey
The fluid flow rate signal of amount is converted into digital signal through A/D, main controller processing is sent in the synchronization time of setting, using synchronization
Time is convenient for relatively more measured fluid flow rate signal.Each flowmeter and main controller are connected on same electric power cable and set
Master switch is set, an electronic switch is installed after master switch, it controls its opening and closing by main controller.Main controller AC power source is connected to
Between electronic switch and master switch.One communications electronics is respectively installed to open in the telecommunication circuit of main controller and each flowmeter
It closes, the ac power input end setting insulating electron of each flowmeter switchs.When communication, main controller turns off electronic switch simultaneously
Its communications electronics switch is connected, each flowmeter also when can't detect power network cycle signal the synchronization time of setting, connects
Lead to respective communications electronics switch, shutdown insulating electron switch is communicated by electric power cable, after sign off, turns off all communications
Electronic switch, then electronic switch and insulating electron switch are connected, at this moment, synchrotimer restarts timing after resetting and obtains
It corrects, it is synchronous to keep system, and remember the accumulated value of time synchronisation.Communication period flowmeter is electromechanical by monolithic is connected to
The rechargeable battery of source filter capacitor is powered, and is isolated through diode with former rectification circuit, the charging circuit of rechargeable battery, tool
Standby charging protection function.The panel of each flowmeter is equipped with 3 to 5 LED modules with different colors, and flowmeter is after rigid booting
For a period of time, it sequentially shows LED modules with different colors combination (such as: red, green, blue, red green, bluish-green, red blue, RGB), it is each to combine
Corresponding with the number of number, when selection display LED modules with different colors combines, shutdown obtains corresponding number and saves, it is
In the number period when can't detect grid cyclic wave signal, number data are stored in non-by single-chip microcontroller by the energy storage of its power capacitor
In volatile memory.
The present invention utilizes the positive half cycle ascent stage of power network cycle, and three examination point realizations is taken to sentence the identification of cycle signal
It is fixed, recycle the cycle time to establish synchronization time, the synchronous operation of main controller and each flowmeter in realization system.
The cycle discriminator circuit structural schematic diagram of master controller and each flowmeter is as shown in Fig. 2, by two using stagnant
The voltage comparator composition of comparator is returned, includes filter circuit, the benchmark electricity of voltage comparator in each voltage comparator
Pressure is provided by voltage regulator circuit.Clock timer and synchrotimer is arranged in system.If detecting two adjacent cycle signals
It is very, then to take out the clock timer timing time between two adjacent cycle signal zero passages, when being sequentially stored in cycle
Between in storage unit, which can store 100 cycle times, the one cycle time of every deposit when being filled with,
The cycle time being stored at first is first removed, and calculates the average value Tz of the cycle time of deposit and saves, utilizes Tz value
Identify cycle signal to be identified, to reduce the influence of power network frequency fluctuation, while reducing erroneous judgement using three examination points may
Property.
Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.In the cycle of cycle positive half cycle ascent stage
At zero passage, that is, screen point 0 setting a voltage zero-cross detection module, it using cycle positive half-wave signal through electric resistance partial pressure, diode into
The clock end CLK of feeding d type flip flop after negative half period, signal condition is isolated in one step, and the Q of d type flip flop terminates single-chip microcontroller external interrupt
Mouthful, which is arranged to level triggers, the end the D ground connection of d type flip flop, and S terminates single-chip processor i/o mouth, usually sets for the I/O mouthfuls
1.When cycle positive half-wave zero cross signal arrives, cycle signal rising edge immediately after makes the end d type flip flop Q 0, outside single-chip microcontroller
Fracture low level in portion executes instruction in the interrupt service program to generate interruption: setting the 0, Central Shanxi Plain for described I/O mouthfuls and breaks, counts
When, described I/O mouthfuls set 1, open interruption.Remaining two comparator is separately positioned on the cycle positive half cycle ascent stage, crest voltage
The examination point 2 of the examination point 1 and 50% to 70% place at 35% to 50% place.
Cycle signal determining: for single-chip microcontroller after setting time opens interruption, clock timer resets and starts timing, works as cycle
When voltage zero-cross, the output voltage jump that d type flip flop in the voltage zero-cross inspection survey mould block ﹙ V0 ﹚ for screen point 0 is arranged in is become zero, and is produced
It is raw to interrupt, record its zero crossing break period Th0；Hereafter, the output electricity of electricity pressure comparator ﹙ V1 ﹚ at point 1 is screened in single-chip microcontroller scanning
Pressure, when all wave voltages reach to ﹙ V1 ﹚ threshold voltage when, output voltage jumps from high to low, scanning record its bound-time Th1；
Same scanning record screens electricity at point 2 and presses comparator ﹙ V2 ﹚ output voltage bound-time Th2, and Th0 and voltage zero-cross are detected mould
The output voltage bound-time setting value Ts0 of Kuai ﹙ V0 ﹚ makes comparisons；The output voltage bound-time of Th1 and electricity pressure comparator ﹙ V1 ﹚
Setting value Ts1 and Th2 makes comparisons respectively with the output voltage bound-time setting value Ts2 of electricity pressure comparator ﹙ V2 ﹚, if
Within the scope of allowable error, then otherwise it is false that the discriminator signal detected, which is true,.When above-mentioned judgement discriminator signal is true, calculate
When clock timer timing between cycle signal zero passage when this cycle signal zero passage and an adjacent preceding discriminator signal are true
Between Tzu, it is made comparisons with the average value Tz of cycle time, if be no more than setting cycle time error Tzv if cycle signal
It is very, at this moment to save Tzu and 20ms is taken to be added with synchrotimer timing time, in the value deposit synchrotimer that will add up.
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens the break period between 18.5ms
Open interruption when setting value Tk, the Central Shanxi Plain is disconnected when clock timer timing to 25ms is to pass break period setting value Tn between 27ms.
After system boot, clock timer starts timing, and when detecting first cycle voltage zero-cross, setting is being screened
The output voltage jump that the voltage zero-cross Jian of point 0 surveys Mo Kuai ﹙ V0 ﹚ takes out the time of cycle voltage over zero to generate interruption
T0 is saved, and clock timer is reset to and started timing, and at this moment cycle time voltage crosses zero Th0 is 0, while single-chip microcontroller is by above-mentioned
Method scans and determines discriminator signal.What it is due to detection is first cycle, and clock timer is opened in cycle voltage zero-cross
Beginning timing, the value of Th0, Th1 and Th2 must subtract open the difference of break period setting value Tk plus cycle time 20ms, such as
Three discriminator signals of fruit are that very, the time T0 of the cycle voltage over zero of taking-up is stored in synchrotimer as initial time,
I.e. opening the break period for the first time takes Tk next time.It otherwise is fictitious time, the clock timer time must add T0 at this time, continue to test.
When detecting first and adjacent second cycle voltage zero-cross, due to not saving the cycle time of detection,
Therefore the clock timer timing time twice between cycle signal zero passage is made comparisons with cycle time 20ms, determines cycle signal
Then it is that the difference for taking 20ms to subtract Th0 is added with synchrotimer timing time when being true, i.e., saves the standard cycle time for the first time
20ms need to deduct its Th0 value, this is because when hereafter detecting that cycle signal is true every time, when opening interruption by clock meter
When device reset after restart timing, and be that the standard cycle time is included in synchrotimer when opening interruption, open interruption
Clock timer is reset afterwards, otherwise determines that cycle signal is fictitious time, and the clock timer time must add T1=T0+Tk at this time, after
It is continuous to detect first cycle again according to the above method.After detecting first cycle signal is very, restore above-described cycle
Signal determining.
As shown in Figure 1, if detect cycle signal be it is false, open the break period next time and open the break period at this
Afterwards, open interruptions when average value Tz through the cycle time that is delayed, and open interrupt after be delayed Tns when the Central Shanxi Plain it is disconnected, when the setting Central Shanxi Plain is broken
Between be when cycle signal screen point 0 when do not generate interruption, at this moment must be in the setting time point more than Ts0 allowable error range
Start to scan, and when scanning examination point 1 and examination point 2, voltage comparator output voltage does not generate jump, all breaks in the Central Shanxi Plain
The time Tns Central Shanxi Plain is disconnected and stops scanning, Tns are as follows:
Tns=Tn-Tk
If detecting that cycle signal is very, next cycle opens break period Tks are as follows:
Tks=Tk+Th0
I.e. from being opened after the break period takes Tk for the first time, clock timer is that timing to Tks opens interruption, and weight after resetting
New to start timing, the Central Shanxi Plain is broken when Tns is arrived in timing, to make the synchrotimer time by the correction of cycle time voltage crosses zero.
It repeats the above process.If the upper cycle signal detected is that very, when this cycle determines, discriminator signal is
Vacation, or the cycle time detected is more than setting cycle time error Tzv or clock meter compared with the average value Tz of cycle time
When device timing to when closing break period setting value Tns, voltage zero-cross inspection is surveyed mould block ﹙ V0 ﹚ output voltage and is not jumped, does not generate
Disconnected, then when Tns is arrived in clock timer timing, the Central Shanxi Plain is disconnected, at this moment remembers and does not count cycle N 1 and to store, when opening interruption next time
Between be to open the break period in last time to open interruption after Tz, clock timer open interrupt after reset and timing, when timing is to Tns
The Central Shanxi Plain is disconnected, hereafter determines the cycle signal true and false every time, though if false or this detection discriminator signal be true last time be it is false, then take
N will be restored in memory after N+1.
When it is true for detecting cycle signal, then takes out N in memory and save, and by N zero setting in memory, and restore to make
With setting value Tks, the value of (N+1) × 20ms is at this moment taken to be added in synchrotimer.
System synchronization time is the time of synchrotimer, along with currently just in the time of the clock timer of timing.
When determining to screen the point signal true and false, Th0, Th1, Th2 are by setting with voltage comparator output voltage bound-time
Definite value Ts0, Ts1, Ts2 make comparisons see it is whether overproof, come determine screen point a signal true and false, can choose: Th0, Th1, Th2 are
It is true that the cycle discriminator signal, which is true or Th0, when true, while when one of Th1, Th2 are true or when Th1, Th2 are true, should
Cycle discriminator signal is very, depending on to determining that cycle signal true and false difference requires.
If system fault, when N be greater than 25 to 70 between a setting value when, due to master controller in system and each stream
Flowmeter, the Tz value and N value of detection may be different, and at this moment, power network frequency accumulated error may cause synchrotimer
Time is corrected when can not be by detecting true cycle signal, when it is true for detecting cycle signal, at this moment uses clock
The accumulative clocking value of timer is directly added in synchrotimer, to reduce the asynchronous time of system, add up clocking value be N ×
Tz+20ms.N is much smaller than 25 in the case of power network normal operation.
The cycle time error Tzv of permission and the flip-flop transition setting value of voltage comparator output voltage, by test assessment
Its average value is taken to obtain.
(4) Detailed description of the invention:
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structural schematic diagram；
Fig. 3 is a kind of circuit structure block diagram of flow signal synchronous.
(5) specific embodiment:
Fig. 3 is a kind of circuit structure block diagram of flow signal synchronous, comprising: 10 ﹚ of Zhu Kong Qi ﹙, communication electricity
11 ﹚ of sub- Kai Guan ﹙, cycle screen 12 ﹚, Liu measurement Yi ﹙ of electricity Lu ﹙, 13 ﹚, 14 ﹚ of Liu Liang Ji ﹙, 15 ﹚ of electricity Kai Guan ﹙, wherein communication electricity
Son, which is opened to close list piece machine ﹙ U0 ﹚ in 11 ﹚ of ﹙, cycle examination electricity road ﹙ 12 ﹚ and Fig. 2 and be separately contained in, flows 13 ﹚ of measurement instrument ﹙ and master control
In 10 ﹚ of Qi ﹙.11 ﹚ and electricity Kai Guan ﹙ of communications electronics Kai Guan ﹙, 15 ﹚ uses bidirectional triode thyristor as switch.
Fig. 2 is the structural schematic diagram that cycle screens 12 ﹚ of electricity Lu ﹙, by: Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian and surveys Mo Kuai ﹙
V0 ﹚, electricity pressure comparator ﹙ V1 ﹚ and electricity pressure comparator ﹙ V2 ﹚ are constituted.Dan Pian Ji ﹙ U0 ﹚ refers to 13 ﹚ of Liu measurement Yi ﹙ and Zhu Kong Qi ﹙
Single-chip microcontroller in 10 ﹚.Shu enters electricity Lu ﹙ S0 ﹚ for mains AC voltage to be passed through to the partial pressure of resistance and diode, is converted to electricity
The input voltage for pressing comparator suitably stable.Single piece machine ﹙ U0 ﹚ uses 89C55WD, electricity pressure comparator ﹙ V1 ﹚, electricity pressure comparator ﹙
V2 ﹚ uses dedicated voltage comparator LM393, and reference voltage is to be compared using the voltage regulator circuit of voltage-stabiliser tube come burning voltage
The threshold voltage of device.When mains AC voltage cycle signal zero passage, the output voltage that voltage zero-cross Jian surveys Mo Kuai ﹙ V0 ﹚ is jumped
Become, Dan Pian Ji ﹙ U0 ﹚ generates interruption, records the break period, while Dan Pian Ji ﹙ U0 ﹚ is also used to scanning voltage Bi compare Qi ﹙ V1 ﹚ and electricity
Press comparator ﹙ V2 ﹚ output voltage, when output voltage jump when record bound-time, for determine power network cycle signal from
And generate synchronization time.
Claims (2)
1. a kind of flow signal synchronous, characterized in that each flowmeter is by synchronization time and the liquid of measurement
Flow signal is converted into digital signal through A/D, sends main controller in the synchronization time of setting and is handled, after master switch
One electronic switch to be installed, its opening and closing is controlled by main controller, main controller AC power source is connected between electronic switch and master switch,
One communications electronics switch, the exchange of each flowmeter are respectively installed in the telecommunication circuit of main controller and each flowmeter
Power input is arranged insulating electron and switchs；Each flowmeter can't detect power network cycle signal in the synchronization time of setting
When, it is communicated by electric power cable, sign off is followed by energization sub switch, and at this moment, synchrotimer restarts timing after resetting
And corrected, communication period flowmeter is by the rechargeable battery power supply for being connected to microcontroller power supply filter capacitor；Respectively
The panel of flowmeter is equipped with 3 to 5 LED modules with different colors, a period of time of flowmeter after rigid booting, selection display
When LED modules with different colors combines, shutdown obtains corresponding number and saves, and working as in the number period can't detect grid cyclic wave signal
When, number data are stored in nonvolatile storage by single-chip microcontroller by the energy storage of its power capacitor；
Cycle discriminator circuit is the positive half cycle ascent stage using power network cycle, takes three to screen knowledge of the point realization to cycle signal
Do not determine, recycle the cycle time to establish synchronization time, clock timer and synchrotimer is arranged in system, if detecting phase
Two adjacent cycle signals are very, then to take out the clock timer timing time between two adjacent cycle signal zero passages
That is the cycle time is sequentially stored in cycle time memory cell, is filled with the one cycle time of every deposit when 100 cycle time,
First remove the cycle time being stored at first, and calculate the average value Tz of the cycle time of deposit, using Tz value identify to
Identify cycle signal；
Two voltage comparators are respectively used to screen point 1, screen point 2, at the cycle zero passage of cycle positive half cycle ascent stage, that is, discriminate
Voltage zero-cross detection module is arranged in other point 0, and negative half is further isolated using cycle positive half-wave signal through electric resistance partial pressure, diode for it
Week, the clock end CLK that d type flip flop is sent into after signal condition, when cycle positive half-wave zero cross signal arrives, cycle immediately after
Signal rising edge makes the end d type flip flop Q 0, single-chip microcontroller external interrupt mouth low level, so that interruption is generated, two voltage comparators
It is separately positioned on cycle positive half cycle ascent stage, the Zhen of the examination point 1 and 50% to 70% place at 35% to 50% place of crest voltage
Other point 2；
Cycle signal determining process: for single-chip microcontroller after setting time opens interruption, clock timer resets and starts timing, works as cycle
When voltage zero-cross, the output voltage jump that d type flip flop in the voltage zero-cross detection module for screening point 0 is arranged in is become zero, in generation
It is disconnected, record its zero crossing break period Th0；Hereafter, the output electricity of first voltage Bi compare Qi ﹙ V1 ﹚ at point 1 is screened in single-chip microcontroller scanning
Pressure, when all wave voltages reach first voltage than threshold voltage compared with device ﹙ V1 ﹚, output voltage jumps from high to low, scanning record
Its bound-time Th1；Same scanning record screens second voltage Bi compare Qi ﹙ V2 ﹚ output voltage bound-time Th2 at point 2, if
For the bound-time Th1 and Th2 within the scope of allowable error, then otherwise it is false, above-mentioned judgement that the discriminator signal detected, which is true,
When discriminator signal is true, calculate between cycle signal zero passage when this cycle signal zero passage and an adjacent preceding discriminator signal are true
Clock timer timing time Tzu, it is made comparisons with the average value Tz of cycle time, if be no more than setting the cycle time
Then cycle signal is very, at this moment to save Tzu and 20ms is taken to be added with synchrotimer timing time to error Tzv, the value that will add up
It is stored in synchrotimer；
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens break period setting between 18.5ms
Open interruption when value Tk, the Central Shanxi Plain is disconnected when clock timer timing to 25ms is to pass break period setting value Tn between 27ms；
When detecting first cycle voltage zero-cross, the output voltage jump for screening the voltage zero-cross detection module of point 0 is set
Become, to generate interruption, time T0 for taking out cycle voltage over zero is saved, clock timer is reset to and is started timing, this
Shi Zhoubo time voltage crosses zero Th0 is 0, and single-chip microcontroller scans and determine discriminator signal, and the value of Th0, Th1 and Th2 must add
The cycle time, 20ms subtracted out the difference of break period setting value Tk, if three discriminator signals are true, all wave voltages of taking-up
The time T0 of zero crossing detects when opening interruption of cycle voltage over zero as in initial time deposit synchrotimer next time
Between take Tk, be otherwise fictitious time, at this time the clock timer time must add T0, continue to test；
It is then that 20ms is taken to subtract when determining that cycle signal is true when detecting first and second adjacent cycle voltage zero-cross
The difference of Th0 is added with synchrotimer timing time, and clock timer is reset after opening interruption, otherwise determines that cycle signal is false
When, the clock timer time must add T1, T1=T0+Tk at this time, first cycle be detected again, when first cycle letter of detection
Number be very after, restore above-described cycle signal determining；
If detecting that cycle signal is vacation, the break period is opened next time after this opens the break period, when through delay cycle
Between average value Tz when open interruption, and open interrupt after be delayed Tns when the Central Shanxi Plain it is disconnected, it is when cycle signal is discriminated that the break period is closed in setting
Not Wei fictitious time, closing, the Central Shanxi Plain break period Tns is disconnected and stop scanning, Tns are as follows:
Tns=Tn-Tk
If detecting that cycle signal is very, next cycle opens break period Tks are as follows:
Tks=Tk+Th0
I.e. from being opened after the break period takes Tk for the first time, clock timer is that timing to Tks opens interruption, and opens again after resetting
Beginning timing, the Central Shanxi Plain is disconnected when timing is to Tns；
Above-mentioned cycle signal determining process is repeated, if the upper cycle signal detected is very, when this cycle determines, to discriminate
Level signal be it is false, then when Tns is arrived in clock timer timing, the Central Shanxi Plain is disconnected, remember cycle N at this moment 1 and to store, and opens next time
The disconnected time is to open the break period in last time to open interruption after Tz, and clock timer is reset after opening interruption and timing, timing are arrived
The Central Shanxi Plain is disconnected when Tns, hereafter determines the cycle signal true and false every time, though if false or this detection discriminator signal is true last time to be
Vacation is then taken out stored N, and will be restored in the memory of storage N after N+1；
It when it is true for detecting cycle signal, then takes out in memory N and saves, and by N zero setting in memory, and restore using setting
At this moment definite value Tks takes the value of (N+1) × 20ms to be added in synchrotimer；
System synchronization time is the time of synchrotimer, along with currently just in the time of the clock timer of timing；
And select: cycle discriminator signal is true when Th0, Th1, Th2 are true or Th0 is true, while one of Th1, Th2 are
When true or when Th1, Th2 are true, cycle discriminator signal be it is true, if N be greater than 25 to 70 between a setting value when, use
The accumulative clocking value of clock timer is directly added in synchrotimer, and adding up clocking value is N × Tz+20ms.
2. a kind of flow signal synchronous according to claim 1, it is characterised in that include:
10 ﹚ of Zhu Kong Qi ﹙, 11 ﹚ of communications electronics Kai Guan ﹙, cycle screen 12 ﹚, Liu measurement Yi ﹙ of electricity Lu ﹙, 13 ﹚, 14 ﹚ of Liu Liang Ji ﹙, electricity
Son, which is opened, closes 15 ﹚ of ﹙, wherein list piece machine ﹙ U0 ﹚, communications electronics run pass 11 ﹚ of ﹙ and cycle screens 12 ﹚ of electricity distance ﹙ and is separately contained in flow
In 13 ﹚ of Ce Liang Yi ﹙ and 10 ﹚ of Zhu Kong Qi ﹙；Wherein cycle screens that 12 ﹚ of electricity Lu ﹙ by: Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross detects mould
Kuai ﹙ V0 ﹚, it screens first voltage Bi compare Qi ﹙ V1 ﹚ at point 1 and screens second voltage Bi compare Qi ﹙ V2 ﹚ composition at point 2, wherein inputting
Electricity Lu ﹙ S0 ﹚ is used to pass through mains AC voltage the partial pressure of resistance and diode, and it is suitably stable to be converted to voltage comparator
Input voltage.
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| US20060232387A1 (en) * | 1995-03-20 | 2006-10-19 | Wheelock Inc. | Apparatus and method for synchronizing visual/audible alarm units in an alarm system |
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