CN106097683B - Distribution electric quantity parameter acquisition system - Google Patents
Distribution electric quantity parameter acquisition system Download PDFInfo
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- CN106097683B CN106097683B CN201610447962.0A CN201610447962A CN106097683B CN 106097683 B CN106097683 B CN 106097683B CN 201610447962 A CN201610447962 A CN 201610447962A CN 106097683 B CN106097683 B CN 106097683B
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C17/00—Arrangements for transmitting signals characterised by the use of a wireless electrical link
- G08C17/02—Arrangements for transmitting signals characterised by the use of a wireless electrical link using a radio link
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- G—PHYSICS
- G08—SIGNALLING
- G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
- G08C19/00—Electric signal transmission systems
Abstract
The invention relates to a power distribution electric quantity parameter acquisition system which comprises a plurality of electric quantity monitoring meters and a main controller, wherein each power distribution line and main electric equipment are respectively provided with one electric quantity monitoring meter, the electric quantity monitoring meters monitor the operation real-time parameters of the power distribution lines, the electric quantity data acquired by the electric quantity monitoring meters are transmitted to the main controller for processing through power line communication, and the main controller is connected with a dispatching room through a GSM network.
Description
(1) technical field:
It include more electric quantity monitoring instrument and a main controller the present invention relates to a kind of distribution electrical parameter acquisition system,
Every distribution line and main electrical equipment configure an electric quantity monitoring instrument, the fortune of electric quantity monitoring instrument monitoring distribution line
Row real-time parameter, the electricity data acquired by power line communication send to main controller handle, main controller by GSM net with
Control room connection.
(2) background technique:
The control system of power supply is provided by power network, each electronic equipment or intermodule are communicated by special circuit,
The timing time of each electronic equipment or electronic module is corrected, reaches synchronous operation purpose.Due to being made using special circuit communication
Wiring complicates and increases cost, if timing time is not corrected by line traffic, due to traditional timing error, runs number
After hour, accumulation timing error can make system control action inconsistent, may cause system crash, set in some frequent changes
Meter, its products application of the big occasion of wiring installation amount are restricted.
(3) summary of the invention:
When needing to measure the electrical parameter of each distribution line it is necessary to acquire distribution electrical parameter, for optimizing distribution
System, reasonable arrangement equipment operation time.The present invention relates to a kind of distribution electrical parameter acquisition systems, include more electric quantity monitorings
Instrument and a main controller, every distribution line and main electrical equipment configure an electric quantity monitoring instrument, every electricity prison
Surveying instrument includes one or several voltage transformer and current transformer, and the operation of electric quantity monitoring instrument monitoring distribution line is real-time
Parameter mainly has: route three-phase voltage, three-phase current, active power, reactive power, power factor, by electric quantity monitoring instrument
ADC synchronizes sampling, it can be achieved that sampling with the voltage of phase, current synchronization, and carries out conditioning transformation to sampled signal, then by its
The electricity data of acquisition sends main controller processing to by half wave communication of power line, and main controller is contacted by GSM net with control room,
Electricity data reasonable arrangement each Workshop Production of the control room according to acquisition.Each electric quantity monitoring instrument and main controller are connected to same electricity
On power cable and master switch is set, an isolating diode is installed after master switch, system is powered using half wave communication half-wave.
It is respectively mounted cycle discriminator circuit in each electric quantity monitoring instrument and main controller, the synchronization time for generation system keeps system acting
Unanimously, while in its telecommunication circuit one communications electronics switch, switch drive module are respectively installed.When communication, communication electricity is connected
Sub switch instructs conversely, main controller is first sent to each electric quantity monitoring instrument, shutdown communications electronics switch.
Communication is by being controlled synchronization time to keep acting permanent consistent, main controller and each electric quantity monitoring instrument, communication
The switch drive module of electronic switch is to be followed by the end CLK of d type flip flop through resistance decompression, partial pressure from electric power cable, d type flip flop
Q terminates the external interrupt mouth (INT0 or INT1) of single-chip microcontroller, which is set as level triggers.The D of d type flip flop is terminated
Ground, the end S connect with the I/O of single-chip microcontroller mouth, and original state S sets 1 in end.When the positive square-wave signal at the end CLK arrives, rising edge
D type flip flop is set to set 0, external interrupt mouth low level generates interruption, and so that the end S is set 0 in the interrupt service program makes d type flip flop set 1
I.e. the end Q is 1 and the Central Shanxi Plain is disconnected, is then communicated, and communications electronics switch is connected to single-chip microcontroller corresponding port according to used communication mode,
And signal condition is carried out, S, which sets at end 1, before sign off makes out the communication of the lower cycle of interrupt latency, so realizes half in cycles
Wave communication.
SMS R-T unit is installed in system, using GSM network, is communicated with receiving and dispatching short message mode, at present
The SMS messaging service of GSM is still that a kind of highest SMS of short message service GSM of domestic popularity rate itself has data transmission function
Can, the transmission of a message just constitutes primary communication, and the transmission of message is by the SMS service center outside GSM
(SMSC) it is relayed, it does not have to dialing and can establish connection by the SMS service SMS of GSM, and user adds the information to be sent out
Stay of two nights data are sent to short message service center, are then forwarded to the final stay of two nights after short message service center completes storage.So
When GSM terminal is not switched on, information will not lose.
The present invention utilizes the positive half cycle ascent stage of power network cycle, and three examination point realizations is taken to sentence the identification of cycle signal
It is fixed, recycle the cycle time to establish synchronization time, the synchronous operation of main controller and each electric quantity monitoring instrument in realization system.
Main controller and the cycle discriminator circuit structural schematic diagram of each electric quantity monitoring instrument are as shown in Fig. 2, by two using stagnant
The voltage comparator composition of comparator is returned, includes filter circuit, the benchmark electricity of voltage comparator in each voltage comparator
Pressure is provided by voltage regulator circuit.Clock timer and synchrotimer is arranged in system.If detecting two adjacent cycle signals
It is very, then to take out the clock timer timing time between two adjacent cycle signal zero passages, when being sequentially stored in cycle
Between in storage unit, which can store 100 cycle times, the one cycle time of every deposit when being filled with,
The cycle time being stored at first is first removed, and calculates the average value Tz of the cycle time of deposit and saves, utilizes Tz value
Identify cycle signal to be identified, to reduce the influence of power network frequency fluctuation, while reducing erroneous judgement using three examination points may
Property.
Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.In the cycle of cycle positive half cycle ascent stage
At zero passage, that is, screen point 0 setting a voltage zero-cross detection module, it using cycle positive half-wave signal through electric resistance partial pressure, diode into
The clock end CLK of feeding d type flip flop after negative half period, signal condition is isolated in one step, and the Q of d type flip flop terminates single-chip microcontroller external interrupt
Mouthful, which is arranged to level triggers, the end the D ground connection of d type flip flop, and S terminates single-chip processor i/o mouth, usually sets for the I/O mouthfuls
1.When cycle positive half-wave zero cross signal arrives, cycle signal rising edge immediately after makes the end d type flip flop Q 0, outside single-chip microcontroller
Fracture low level in portion executes instruction in the interrupt service program to generate interruption: setting the 0, Central Shanxi Plain for described I/O mouthfuls and breaks, counts
When, described I/O mouthfuls set 1, open interruption.Remaining two comparator is separately positioned on the cycle positive half cycle ascent stage, crest voltage
The examination point 2 of the examination point 1 and 50% to 70% place at 35% to 50% place.
Cycle signal determining: for single-chip microcontroller after setting time opens interruption, clock timer resets and starts timing, works as cycle
When voltage zero-cross, the output voltage jump that d type flip flop in the voltage zero-cross inspection survey mould block ﹙ V0 ﹚ for screen point 0 is arranged in is become zero, and is produced
It is raw to interrupt, record its zero crossing break period Th0；Hereafter, the output electricity of electricity pressure comparator ﹙ V1 ﹚ at point 1 is screened in single-chip microcontroller scanning
Pressure, when all wave voltages reach to ﹙ V1 ﹚ threshold voltage when, output voltage jumps from high to low, scanning record its bound-time Th1；
Same scanning record screens electricity at point 2 and presses comparator ﹙ V2 ﹚ output voltage bound-time Th2, and Th0 and voltage zero-cross are detected mould
The output voltage bound-time setting value Ts0 of Kuai ﹙ V0 ﹚ makes comparisons；The output voltage bound-time of Th1 and electricity pressure comparator ﹙ V1 ﹚
Setting value Ts1 and Th2 makes comparisons respectively with the output voltage bound-time setting value Ts2 of electricity pressure comparator ﹙ V2 ﹚, if
Within the scope of allowable error, then otherwise it is false that the discriminator signal detected, which is true,.When above-mentioned judgement discriminator signal is true, calculate
When clock timer timing between cycle signal zero passage when this cycle signal zero passage and an adjacent preceding discriminator signal are true
Between Tzu, it is made comparisons with the average value Tz of cycle time, if be no more than setting cycle time error Tzv if cycle signal
It is very, at this moment to save Tzu and 20ms is taken to be added with synchrotimer timing time, in the value deposit synchrotimer that will add up.
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens the break period between 18.5ms
Open interruption when setting value Tk, the Central Shanxi Plain is disconnected when clock timer timing to 25ms is to pass break period setting value Tn between 27ms.
After system boot, clock timer starts timing, and when detecting first cycle voltage zero-cross, setting is being screened
The output voltage jump that the voltage zero-cross Jian of point 0 surveys Mo Kuai ﹙ V0 ﹚ takes out the time of cycle voltage over zero to generate interruption
T0 is saved, and clock timer is reset to and started timing, and at this moment cycle time voltage crosses zero Th0 is 0, while single-chip microcontroller is by above-mentioned
Method scans and determines discriminator signal.What it is due to detection is first cycle, and clock timer is opened in cycle voltage zero-cross
Beginning timing, the value of Th0, Th1 and Th2 must subtract open the difference of break period setting value Tk plus cycle time 20ms, such as
Three discriminator signals of fruit are that very, the time T0 of the cycle voltage over zero of taking-up is stored in synchrotimer as initial time,
I.e. opening the break period for the first time takes Tk next time.It otherwise is fictitious time, the clock timer time must add T0 at this time, continue to test.
When detecting first and adjacent second cycle voltage zero-cross, due to not saving the cycle time of detection,
Therefore the clock timer timing time twice between cycle signal zero passage is made comparisons with cycle time 20ms, determines cycle signal
Then it is that the difference for taking 20ms to subtract Th0 is added with synchrotimer timing time when being true, i.e., saves the standard cycle time for the first time
20ms need to deduct its Th0 value, this is because when hereafter detecting that cycle signal is true every time, when opening interruption by clock meter
When device reset after restart timing, and be that the standard cycle time is included in synchrotimer when opening interruption, open interruption
Clock timer is reset afterwards, otherwise determines that cycle signal is fictitious time, and the clock timer time must add T1=T0+Tk at this time, after
It is continuous to detect first cycle again according to the above method.After detecting first cycle signal is very, restore above-described cycle
Signal determining.
As shown in Figure 1, if detect cycle signal be it is false, open the break period next time and open the break period at this
Afterwards, open interruptions when average value Tz through the cycle time that is delayed, and open interrupt after be delayed Tns when the Central Shanxi Plain it is disconnected, when the setting Central Shanxi Plain is broken
Between be when cycle signal screen point 0 when do not generate interruption, at this moment must be in the setting time point more than Ts0 allowable error range
Start to scan, and when scanning examination point 1 and examination point 2, voltage comparator output voltage does not generate jump, all breaks in the Central Shanxi Plain
The time Tns Central Shanxi Plain is disconnected and stops scanning, Tns are as follows:
Tns=Tn-Tk
If detecting that cycle signal is very, next cycle opens break period Tks are as follows:
Tks=Tk+Th0
I.e. from being opened after the break period takes Tk for the first time, clock timer is that timing to Tks opens interruption, and weight after resetting
New to start timing, the Central Shanxi Plain is broken when Tns is arrived in timing, to make the synchrotimer time by the correction of cycle time voltage crosses zero.
It repeats the above process.If the upper cycle signal detected is that very, when this cycle determines, discriminator signal is
Vacation, or the cycle time detected is more than setting cycle time error Tzv or clock meter compared with the average value Tz of cycle time
When device timing to when closing break period setting value Tns, voltage zero-cross inspection is surveyed mould block ﹙ V0 ﹚ output voltage and is not jumped, does not generate
Disconnected, then when Tns is arrived in clock timer timing, the Central Shanxi Plain is disconnected, at this moment remembers and does not count cycle N 1 and to store, when opening interruption next time
Between be to open the break period in last time to open interruption after Tz, hereafter every time determine the cycle signal true and false, if false or this detection
Though discriminator signal is true but last time is vacation, then N is taken, will be restored after N+1 in memory, clock timer not reset after opening interruption
Continue timing, at this moment, next cycle of setting opens the break period and temporarily uses out break period interim setting value Tkz instead:
Tkz=(N+1) × Tz
Meanwhile next cycle pass break period temporarily uses instead and closes break period interim setting value Tnz:
Tnz=Tkz+Tns
When clock timer to after Tkz, the time that point is screened in scanning can be obtained by simple computation.If at this moment examined
Measuring cycle signal is very, then to take out N in memory and save, and by N zero setting in memory, make clock timer clocking value Ts
Are as follows: at this moment (Ts-Tkz) → Ts takes the value of (N+1) × 20ms to be added in synchrotimer, and restore using setting value Tks with
Tns, recovered clock timer are reset after opening interruption.
System synchronization time is the time of synchrotimer, along with currently just in the time of the clock timer of timing.
When determining to screen the point signal true and false, Th0, Th1, Th2 are by setting with voltage comparator output voltage bound-time
Definite value Ts0, Ts1, Ts2 make comparisons see it is whether overproof, come determine screen point a signal true and false, can choose: Th0, Th1, Th2 are
It is true that the cycle discriminator signal, which is true or Th0, when true, while when one of Th1, Th2 are true or when Th1, Th2 are true, should
Cycle discriminator signal is very, depending on to determining that cycle signal true and false difference requires.
If system fault, when N be greater than 25 to 70 between a setting value when, due to main controller in system and each electricity
Measuring instrument, the Tz value and N value of detection may be different, and at this moment, power network frequency accumulated error may cause synchrotimer
Time is corrected when can not be by detecting true cycle signal, when it is true for detecting cycle signal, using clock timing
Clocking value of the device at Tkz is directly added in synchrotimer, to reduce the asynchronous time of system, power network normal operation feelings
N is much smaller than 25 under condition.
The cycle time error Tzv of permission and the flip-flop transition setting value of voltage comparator output voltage, by test assessment
Its average value is taken to obtain.
(4) Detailed description of the invention:
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structural schematic diagram；
Fig. 3 is the circuit structure block diagram of distribution electrical parameter acquisition system.
(5) specific embodiment:
Fig. 3 is the circuit structure block diagram of distribution electrical parameter acquisition system, comprising: 10 ﹚ of Zhu Kong Qi ﹙, communications electronics are opened
Close 11 ﹚ of ﹙, switch drives 12 ﹚ of dynamic model block ﹙, SMS receives 13 ﹚, SIM card ﹙ of transmitting apparatus ﹙, 14 ﹚, mutually sense 15 ﹚ of device ﹙, cycle screen electricity
16 ﹚ of Lu ﹙, 17 ﹚ of electric quantity monitoring Yi Biao ﹙.Wherein 11 ﹚ of communications electronics Kai Guan ﹙, 12 ﹚ of switch Qu dynamic model Kuai ﹙, cycle screen electricity Lu ﹙
List piece machine ﹙ U0 ﹚ is separately contained in 17 ﹚ of electric quantity monitoring instrument table ﹙ and main 10 ﹚ of control device ﹙ in 16 ﹚ and Fig. 2.It is wrapped in 15 ﹚ of Hu Gan Qi ﹙
Include voltage transformer and current transformer.Wherein 11 ﹚ of communications electronics Kai Guan ﹙ uses bidirectional triode thyristor as switch.
Fig. 2 is the structural schematic diagram that cycle screens 16 ﹚ of electricity Lu ﹙, by: Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian and surveys Mo Kuai ﹙
V0 ﹚, electricity pressure comparator ﹙ V1 ﹚ and electricity pressure comparator ﹙ V2 ﹚ are constituted.Dan Pian Ji ﹙ U0 ﹚ refers to 17 ﹚ of electric quantity monitoring Yi Biao ﹙ and master control
Single-chip microcontroller in 10 ﹚ of Qi ﹙.Shu enters electricity Lu ﹙ S0 ﹚ for mains AC voltage to be passed through to the partial pressure of resistance and diode, conversion
For the input voltage that voltage comparator is suitably stable.Single piece machine ﹙ U0 ﹚ uses 89C55WD, electricity pressure comparator ﹙ V1 ﹚, voltage ratio
Compare Qi ﹙ V2 ﹚ uses dedicated voltage comparator LM393, and reference voltage is the voltage regulator circuit using voltage-stabiliser tube come burning voltage
The threshold voltage of comparator.
When mains AC voltage cycle signal zero passage, voltage zero-cross Jian surveys the output voltage jump of Mo Kuai ﹙ V0 ﹚, single
Pian Ji ﹙ U0 ﹚ generates interruption, records the break period, while Dan Pian Ji ﹙ U0 ﹚ is also used to scanning voltage Bi compare Qi ﹙ V1 ﹚ and voltage ratio
The output voltage of compare Qi ﹙ V2 ﹚ records bound-time when output voltage jump, produces for determining power network cycle signal
Raw synchronization time.
Single chip computer89C51 realizes serial communication, the single-chip microcontroller by I2C bus and main controller in SMS R-T unit
89C51 also passes through serial line interface integrated circuit MAX232 and connect progress data exchange, gsm module chip with gsm module TC35i
TC35i is RS232 data port, supports AT Command Set, wherein contain the control to SMS, single chip computer89C51 is by GSM mould
Block sends a series of AT instructions, completes the initialization and receiving short message to gsm module.The transmitting-receiving of SMS uses TEXT mode,
TEXT mode is a kind of tactic pattern based on ASCII character.
Claims (2)
1. distribution electrical parameter acquisition system, characterized in that its electricity data acquired is sent to by half wave communication of power line
Main controller processing, main controller are contacted by GSM net with control room, electricity data reasonable arrangement each workshop of the control room according to acquisition
Production, each electric quantity monitoring instrument and main controller are connected on same electric power cable and master switch are arranged, install after master switch
One isolating diode is respectively mounted cycle discriminator circuit in each electric quantity monitoring instrument and main controller, the synchronization for generation system
Time, while communications electronics switch, switch drive module, main controller and each electric quantity monitoring being respectively installed in its telecommunication circuit
It is by being controlled synchronization time to keep movement permanent consistent that instrument communicates therebetween, and the switch drive module of communications electronics switch is
The end CLK of d type flip flop is followed by through resistance decompression, partial pressure from electric power cable, the Q of d type flip flop terminates the external interrupt mouth of single-chip microcontroller,
When the positive square-wave signal at the end CLK arrives, rising edge makes d type flip flop set 0, and external interrupt mouth low level generates interruption, carries out
It communicates, SMS R-T unit is installed in system, using GSM network, is communicated with receiving and dispatching short message mode；
Cycle discriminator circuit is the positive half cycle ascent stage using power network cycle, takes three to screen knowledge of the point realization to cycle signal
Do not determine, recycle the cycle time to establish synchronization time, clock timer and synchrotimer is arranged in system, if detecting phase
Two adjacent cycle signals are very, then to take out the clock timer timing time between two adjacent cycle signal zero passages
That is the cycle time is sequentially stored in cycle time memory cell, is filled with the one cycle time of every deposit when 100 cycle time,
First remove the cycle time being stored at first, and calculate the average value Tz of the cycle time of deposit, using Tz value identify to
Identify cycle signal；
Two comparators are respectively used to screen point 1, screen point 2, at the cycle zero passage of cycle positive half cycle ascent stage, that is, screen point
0 setting voltage zero-cross detection module, it using cycle positive half-wave signal through electric resistance partial pressure, diode be further isolated negative half period,
The clock end CLK of d type flip flop is sent into after signal condition, when cycle positive half-wave zero cross signal arrives, cycle immediately after is believed
Number rising edge makes the end d type flip flop Q 0, and single-chip microcontroller external interrupt mouth low level, to generate interruption, two comparators are set respectively
It sets in cycle positive half cycle ascent stage, the examination point 2 of the examination point 1 and 50% to 70% place at 35% to 50% place of crest voltage；
Cycle signal determining process: for single-chip microcontroller after setting time opens interruption, clock timer resets and starts timing, works as cycle
When voltage zero-cross, the output voltage jump that d type flip flop in the voltage zero-cross detection module for screening point 0 is arranged in is become zero, in generation
It is disconnected, record its cycle time voltage crosses zero Th0；Hereafter, the output of first voltage Bi compare Qi ﹙ V1 ﹚ at point 1 is screened in single-chip microcontroller scanning
Voltage, when all wave voltages reach first voltage than threshold voltage compared with device ﹙ V1 ﹚, output voltage jumps from high to low, scanning note
Record its bound-time Th1；Same scanning record screens second voltage Bi compare Qi ﹙ V2 ﹚ output voltage bound-time Th2 at point 2, institute
If stating bound-time Th1 and Th2 within the scope of allowable error, otherwise it is vacation that the discriminator signal detected, which is true, above-mentioned to sentence
When to determine discriminator signal be true, cycle signal zero passage when this cycle signal zero passage and an adjacent preceding discriminator signal are true is calculated
Between clock timer timing time Tzu, it is made comparisons with the average value Tz of cycle time, if be no more than setting cycle
Between error Tzv then cycle signal be it is true, at this moment save Tzu and 20ms taken to be added with synchrotimer timing time, will add up
In value deposit synchrotimer；
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens break period setting between 18.5ms
Open interruption when value Tk, the Central Shanxi Plain is disconnected when clock timer timing to 25ms is to pass break period setting value Tn between 27ms；
When detecting first cycle voltage zero-cross, the output voltage jump for screening the voltage zero-cross detection module of point 0 is set
Become, to generate interruption, time T0 for taking out cycle voltage over zero is saved, clock timer is reset to and is started timing, this
Shi Zhoubo time voltage crosses zero Th0 is 0, and single-chip microcontroller scans and determine discriminator signal, and the value of Th0, Th1 and Th2 must add
The cycle time, 20ms subtracted out the difference of break period setting value Tk, if three discriminator signals are true, all wave voltages of taking-up
The time T0 of zero crossing detects when opening interruption of cycle voltage over zero as in initial time deposit synchrotimer next time
Between take Tk, otherwise have a discriminator signal be fictitious time, at this time the clock timer time must add T0, continue to test；
It is then that 20ms is taken to subtract when determining that cycle signal is true when detecting first and second adjacent cycle voltage zero-cross
The difference of Th0 is added with synchrotimer timing time, and clock timer is reset after opening interruption, otherwise determines that cycle signal is false
When, the clock timer time must add T1, T1=T0+Tk at this time, first cycle be detected again, when first cycle letter of detection
Number be very after, restore above-described cycle signal determining；
If detecting that cycle signal is vacation, the break period is opened next time after this opens the break period, when through delay cycle
Between average value Tz when open interruption, and open interrupt after be delayed Tns when the Central Shanxi Plain it is disconnected, it is when cycle signal is discriminated that the break period is closed in setting
Not Wei fictitious time, closing, the Central Shanxi Plain break period Tns is disconnected and stop scanning, Tns are as follows:
Tns=Tn-Tk
If detecting that cycle signal is very, next cycle opens break period Tks are as follows:
Tks=Tk+Th0
I.e. from being opened after the break period takes Tk for the first time, clock timer is that timing to Tks opens interruption, and opens again after resetting
Beginning timing, the Central Shanxi Plain is disconnected when timing is to Tns；
Above-mentioned cycle signal determining process is repeated, if the upper cycle signal detected is very, when this cycle determines, to discriminate
Level signal be it is false, then when Tns is arrived in clock timer timing, the Central Shanxi Plain is disconnected, remember cycle N at this moment 1 and to store, and opens next time
The disconnected time is to open the break period in last time to open interruption after Tz, hereafter every time determine the cycle signal true and false, if false or this
Though detection discriminator signal is true but last time is vacation, then stored N is taken out, and will restore in the memory of storage N after N+1,
Clock timer open interrupt after do not reset continuation timing, at this moment, next cycle of setting is opened during the break period temporarily uses instead open
Disconnected time interim setting value Tkz:
Tkz=(N+1) × Tz
Meanwhile next cycle pass break period temporarily uses instead and closes break period interim setting value Tnz:
Tnz=Tkz+Tns
When clock timer to after Tkz, if at this moment detect cycle signal be it is true, take out N in memory and save, and
By N zero setting in memory, make clock timer clocking value Ts are as follows: first calculate Ts-Tkz again with results modification Ts value is calculated, at this moment
It takes the value of (N+1) × 20ms to be added in synchrotimer, and restores using setting value Tks and Tns, recovered clock timer is being opened
It is reset after interruption；
System synchronization time is the time of synchrotimer, along with currently just in the time of the clock timer of timing；
And select: cycle signal is true when Th0, Th1, Th2 are true or Th0 is true and when one of Th1, Th2 are true, or
When person Th1, Th2 are true, cycle signal be it is true, if N be greater than 25 to 70 between a setting value when, existed using clock timer
Clocking value at Tkz is directly added in synchrotimer.
2. distribution electrical parameter acquisition system according to claim 1, it is characterised in that include:
Main 10 ﹚ of control device ﹙, communications electronics, which are opened, closes 11 ﹚ of ﹙, switch drive 12 ﹚ of dynamic model block ﹙, SMS receipts 13 ﹚, SIM card ﹙ of transmitting apparatus ﹙
14 ﹚, 15 ﹚ of Hu Gan Qi ﹙, cycle screen 16 ﹚ of electricity Lu ﹙, 17 ﹚ of electric quantity monitoring Yi Biao ﹙, and wherein Dan Pian Ji ﹙ U0 ﹚ and communications electronics are opened
Close 11 ﹚ of ﹙, switch drives 12 ﹚ of dynamic model block ﹙ and cycle screens 16 ﹚ of electricity road ﹙ and is separately contained in 17 ﹚ of electric quantity monitoring instrument table ﹙ and master control
It include voltage transformer and current transformer in 15 ﹚ of Hu Gan Qi ﹙ in 10 ﹚ of Qi ﹙；
Cycle screens 16 ﹚ of electricity Lu ﹙, by: Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian and surveys Mo Kuai ﹙ V0 ﹚, an examination 1 first voltage ratio of point
Compare Qi ﹙ V1 ﹚ is constituted with second voltage Bi compare Qi ﹙ V2 ﹚ at point 2 is screened, and Shu enters electricity Lu ﹙ S0 ﹚ for leading to mains AC voltage
The partial pressure for crossing resistance and diode is converted to the suitably stable input voltage of voltage comparator；
Single chip computer89C51 realizes serial communication, the single-chip microcontroller by I2C bus and main controller in SMS R-T unit
89C51 also passes through serial port MAX232 and connect progress data exchange with gsm module TC35i.
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| CN2230929Y (en) * | 1994-10-06 | 1996-07-10 | 吴子方 | Electric meter |
| JP2001256583A (en) * | 2000-03-08 | 2001-09-21 | Toyo Keiki Co Ltd | Automatic meter reading system |
| CN101256210A (en) * | 2008-03-26 | 2008-09-03 | 首都师范大学 | Three-phase electric energy meter based on NIOS II microprocessor |
| JP2011250300A (en) * | 2010-05-28 | 2011-12-08 | Panasonic Electric Works Co Ltd | Remote meter reading system |
| JP2015186388A (en) * | 2014-03-25 | 2015-10-22 | 株式会社東芝 | Watt-hour meter for automatic meter reading system and power failure monitoring system |
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