CN106089782B - Parlor fan natural wind control system - Google Patents
Parlor fan natural wind control system Download PDFInfo
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- CN106089782B CN106089782B CN201610448468.6A CN201610448468A CN106089782B CN 106089782 B CN106089782 B CN 106089782B CN 201610448468 A CN201610448468 A CN 201610448468A CN 106089782 B CN106089782 B CN 106089782B
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Classifications
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04D—NON-POSITIVE-DISPLACEMENT PUMPS
- F04D27/00—Control, e.g. regulation, of pumps, pumping installations or pumping systems specially adapted for elastic fluids
-
- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F04—POSITIVE - DISPLACEMENT MACHINES FOR LIQUIDS; PUMPS FOR LIQUIDS OR ELASTIC FLUIDS
- F04D—NON-POSITIVE-DISPLACEMENT PUMPS
- F04D27/00—Control, e.g. regulation, of pumps, pumping installations or pumping systems specially adapted for elastic fluids
- F04D27/001—Testing thereof; Determination or simulation of flow characteristics; Stall or surge detection, e.g. condition monitoring
Abstract
The present invention relates to a kind of parlor fan natural wind control system, comprising multiple fan governors and a main controller.Each wall fan or the fixed sensing of stand fan blowing direction unification are outdoor, produce the natural wind effect that each fan is uniformly coordinated, more effectively heat is sent out outdoor, main controller is provided with infrared receiving circuit, when needing to change fan operational mode, infra-red remote control transmitter sends operational mode command signal, and implementation pattern changes and various operations.
Description
(1) technical field：
The present invention relates to a kind of parlor fan natural wind control system, comprising multiple fan governors and a main controller.
Each wall fan or the fixed natural wind effect pointed to open air, produce each fan to be uniformly coordinated of stand fan blowing direction unification, more effectively
Heat is sent out outdoor in ground.Main controller is provided with infrared receiving circuit, it is necessary to when changing fan operational mode, infra-red remote control is sent out
Emitter sends operational mode command signal, and implementation pattern changes and various operations.
(2) background technology：
The control system of power supply is provided by power network, its each electronic equipment or intermodule are communicated by special circuit,
To correct the timing time of each electronic equipment or electronic module, synchronous operation purpose is reached.Due to being made using special circuit communication
Wiring is complicated and increases cost, if timing time is not corrected by line traffic, due to traditional timing error, runs number
After hour, its accumulation timing error can make system control action inconsistent, be likely to result in system crash, often changed at some and set
Meter, the big occasion of wiring installation amount its products application is restricted.
(3) content of the invention：
Many parlors do not fill air-conditioning but are desultorily dried with electric fan, and radiating effect is poor.The present invention relates to parlor
Fan natural wind control system, comprising multiple fan governors and a main controller.Each fan governor controls a ceiling fan
Or the electric fan such as wall fan or stand fan, each wall fan or unification of stand fan blowing direction is fixed points to outdoor, blowing is unified orderly, more
Effectively heat is sent out outdoor.There is an air switch on the main switchboard of parlor, an electronics is installed after air switch
Switch, electronic switch parallel connection isolating diode, and each installation one in the telecommunication circuit of main controller and each fan governor
Individual communications electronics switch, switch drive module.Cycle discriminator circuit is respectively mounted in main controller and each fan governor, for producing
The lock in time of system keeps system to keep strokes.During communication, main controller shut-off electronic switch simultaneously connects its communications electronics switch,
Civil power is sent into system through isolating diode, system is in through half wave communication half-wave power supply state of power line, each fan control
Device also can't detect power network be rectified diode blocking half-wave voltage signal when, system be in half-wave communications status, that is, turn off
Fan power supply, connects communications electronics switch；Conversely, before all-wave is switched to from half-wave, main controller is first sent out to each fan governor
Switching command is sent, communications electronics switch connection fan power supply is turned off.Main controller is provided with infrared receiving circuit, and it is generally by producer
Be integrated in an element, being integrally formed infrared receiving terminal, it is necessary to when changing fan operational mode, infra-red remote control transmitter
Operational mode command signal is sent, infrared receiver device receives the infrared command signal of infra-red remote control transmitter in main controller
When, infrared signal is become electric signal and is sent to pre-amplification circuit to be amplified by it, then after demodulated device, is examined by signal
Go out circuit to detect command signal, implementation pattern changes and various operations.Gentle breeze or temporary of the main controller selection in operation natural wind
Half-wave traffic operation is carried out during blow off wind, call duration time is very short, natural wind effect is not influenceed.The output warp of each fan governor
Phototube Coupling and bidirectional triode thyristor are serially connected with former socket or switch, and electric fan is inserted on socket or is connected in on-off circuit, real
Existing its load energized power and control of time, the natural wind effect for producing each fan to be uniformly coordinated change parlor design very square
Just, without broken wall paper line.
The switch drive module of communications electronics switch is to divide two-way after being depressured through resistance from electric power netting twine, all the way for each wind
Fan controller, it is connected to the single-chip processor i/o mouthful of each fan governor through reversal connection diode, negative to cycle in clock timer timing
During half-wave, the I/O mouthfuls is scanned, if being that system is in half-wave communications status without signal.Another road is used for each fan governor
And main controller, communication therebetween is that the road is followed by d type flip flop through electric resistance partial pressure to keep keeping strokes by lock in time control
CLK ends, the external interrupt mouthful (INT0 or INT1) of the Q termination single-chip microcomputers of d type flip flop, fracture is set to level triggers in this.D is touched
The D ends ground connection of device is sent out, its S end connects with I/O mouthfuls of single-chip microcomputer, and original state S puts 1 in end.When the positive square-wave signal at CLK ends arrives
When, its rising edge sets to 0 d type flip flop, and external interrupt mouthful low level produces interruption, and first setting to 0 S ends in interrupt service routine makes
D type flip flop put 1 i.e. Q ends for 1 the Central Shanxi Plain break, then communicated, communications electronics switch according to monolithic is connected to using communication mode
Machine corresponding port, and carry out signal condition, S puts at end 1 before sign off makes out the communication of the next cycle of interrupt latency, so week and
Renew and realize half wave communication.
The present invention is taken three examination points and is realized sentencing the identification of cycle signal using the positive half cycle ascent stage of power network cycle
It is fixed, recycle the cycle time to set up lock in time, realize the synchronous operation of main controller and each fan governor in system.
The cycle discriminator circuit structural representation of main controller and each fan governor by two as shown in Fig. 2 use hysteresis
The voltage comparator composition of comparator, includes filter circuit, the reference voltage of its voltage comparator in each voltage comparator
There is provided by mu balanced circuit.System sets clock timer and synchrotimer.If it is equal to detect two adjacent cycle signals
It is true, then takes out the clock timer timing time between this two adjacent cycle signal zero passages, is sequentially stored in the cycle time
In memory cell, the cycle time memory cell can deposit 100 cycle times, a cycle time is often stored in when being filled with,
The cycle time being stored at first is first removed, and is calculated the average value Tz of the cycle time being stored in and is preserved, reflected using Tz values
Cycle signal not to be identified, to reduce the influence of power network frequency fluctuation, while screening point using three reduces erroneous judgement possibility.
Two comparators are respectively used to screen point 1, screen point 2, as shown in Figure 1.In the cycle of cycle positive half cycle ascent stage
At zero passage, that is, screen point 0 and voltage zero-cross detection module is set, it is entered using cycle positive half-wave signal through electric resistance partial pressure, diode
The clock end CLK of d type flip flop, the Q termination single-chip microcomputer external interrupts of d type flip flop are sent into after one step isolation negative half period, signal condition
Mouthful, external interrupt mouth is arranged to level triggers, and the D ends ground connection of d type flip flop, S termination single-chip processor i/os mouthful are usually put for the I/O mouthfuls
1.When cycle positive half-wave zero cross signal arrives, cycle signal rising edge immediately after makes d type flip flop Q ends be 0, outside single-chip microcomputer
Fracture low level in portion, so that interruption is produced, the execute instruction in interrupt service routine：Described I/O mouthfuls set to 0, the Central Shanxi Plain is disconnected, meter
When, described I/O mouthfuls put 1, open interruption.Remaining two comparator is separately positioned on the cycle positive half cycle ascent stage, crest voltage
The examination point 1 and the examination point 2 at 50% to 70% place at 35% to 50% place.
Cycle signal determining：After setting time opens interruption, clock timer resets and starts timing single-chip microcomputer, works as cycle
During voltage zero-cross, the output voltage for being arranged on d type flip flop in the voltage zero-cross inspection survey mould block ﹙ V0 ﹚ for screen point 0 jumps vanishing, produces
It is raw to interrupt, record its zero crossing break period Th0；Hereafter, the output electricity of electricity pressure comparator ﹙ V1 ﹚ at point 1 is screened in single-chip microcomputer scanning
Pressure, during when all wave voltages up to the threshold voltage to ﹙ V1 ﹚, output voltage saltus step from high to low, scanning records its bound-time Th1；
Same scanning record screens electricity pressure comparator ﹙ V2 ﹚ output voltage bound-time Th2 at point 2, and Th0 and voltage zero-cross are detected into mould
The output voltage bound-time setting value Ts0 of Kuai ﹙ V0 ﹚ makes comparisons；The output voltage bound-time of Th1 and electricity pressure comparator ﹙ V1 ﹚
Setting value Ts1 and Th2 makes comparisons respectively with the output voltage bound-time setting value Ts2 of electricity pressure comparator ﹙ V2 ﹚, if
In the range of allowable error, then the discriminator signal for detecting is true, is otherwise false.It is above-mentioned when judging discriminator signal as true, calculate
During clock timer timing between cycle signal zero passage when this cycle signal zero passage is true with an adjacent preceding discriminator signal
Between Tzu, it is made comparisons with the average value Tz of cycle time, the cycle signal if no more than setting cycle time error Tzv
It is true, at this moment preserves Tzu and take 20ms and be added with synchrotimer timing time, the value that will add up is stored in synchrotimer.
When clock timer starts timing with cycle voltage zero-cross, then timing opens the break period between 16ms to 18.5ms
Open interruption during setting value Tk, clock timer timing is broken to Central Shanxi Plain during pass break period setting value Tn between 25ms to 27ms.
After system boot, clock timer starts timing, when first cycle voltage zero-cross is detected, is arranged on examination
The voltage zero-cross Jian of point 0 surveys the output voltage saltus step of Mo Kuai ﹙ V0 ﹚, so as to produce interruption, takes out the time of cycle voltage over zero
T0 is preserved, and clock timer is reset and starts timing, and at this moment cycle time voltage crosses zero Th0 is 0, while single-chip microcomputer is by above-mentioned
Method is scanned and judges discriminator signal.Due to detection is first cycle, and clock timer is opened in cycle voltage zero-cross
Beginning timing, the value of its Th0, Th1 and Th2 must add the difference that cycle time 20ms subtracts out break period setting value Tk, such as
Really three discriminator signals are true, and the time T0 of the cycle voltage over zero of taking-up is stored in synchrotimer as initial time,
I.e. opening the break period for the first time takes Tk next time.Otherwise it is fictitious time, now the clock timer time must be plus T0, and continuation is detected.
When first and second adjacent cycle voltage zero-cross is detected, due to not preserving the cycle time of detection,
Therefore the clock timer timing time twice between cycle signal zero passage is made comparisons with cycle time 20ms, judges cycle signal
Then it is to take 20ms and subtract the difference of Th0 to be added with synchrotimer timing time when being true, i.e., preserves the standard cycle time for the first time
20ms, need to deduct its Th0 value, because when hereafter to detect cycle signal every time be true, by clock meter when interruption is opened
When device reset after restart timing, and be in when interruption is opened being counted into synchrotimer the standard cycle time, to open interruption
Clock timer resets afterwards, otherwise judges that cycle signal is fictitious time, now the clock timer time must plus T1=T0+Tk, after
It is continuous to detect first cycle again as stated above.When first cycle signal of detection is after very, to recover above-described cycle
Signal determining.
If as shown in figure 1, it is false to detect cycle signal, the break period being opened next time and opening the break period at this
Interruption is opened when afterwards, through the average value Tz of time delay cycle time, and the Central Shanxi Plain is broken in time delay Tns after opening interruption, when the setting Central Shanxi Plain is disconnected
Between be when cycle signal screen point 0 when do not produce interruption, at this moment must be in the setting time point more than Ts0 allowable error scopes
When starting scanning, and scanning examination point 1 with point 2 is screened, voltage comparator output voltage does not produce saltus step, all breaks in the Central Shanxi Plain
The Central Shanxi Plain was broken and stopped scanning time Tns, and Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
Opened after the break period takes Tk from first time, clock timer is timing opens interruptions to Tks, and weighed after resetting
New to start timing, timing is disconnected to Central Shanxi Plain during Tns, so that the synchrotimer time is corrected by cycle time voltage crosses zero.
Repeat said process.If the upper cycle signal for detecting is true, when this cycle judges, discriminator signal is
Vacation, or the cycle time for detecting compares more than setting cycle time error Tzv with the average value Tz of cycle time, or clock meter
When device timing to close break period setting value Tns when, voltage zero-cross inspection survey the mould block ﹙ V0 non-saltus steps of ﹚ output voltages, without produce in
Disconnected, then when clock timer timing is to Tns, the Central Shanxi Plain is broken, and at this moment remembers that not counting cycle N is 1 and stores, when opening interruption next time
Between be to open the break period by opening interruption after Tz in last time, clock timer open interrupt after reset and timing, when timing is to Tns
The Central Shanxi Plain is broken, and the cycle signal true and false is hereafter judged every time, though if false or this detection discriminator signal be false true last time, then take
N, will restore in memory after N+1.
When it is true to detect cycle signal, then N is preserved in taking out memory, and N zero setting in memory, and recovery are made
Setting value Tks is used, the value at this moment taking (N+1) × 20ms is added in synchrotimer.
The system synchronization time for synchrotimer time, along with currently just timing clock timer time.
When judging to screen the point signal true and false, Th0, Th1, Th2 are set by with voltage comparator output voltage bound-time
Definite value Ts0, Ts1, Ts2 make comparisons see whether it is overproof come judge screen point a signal true and false, can select：Th0, Th1, Th2 are
The cycle discriminator signal is true when true, or Th0 is true, while when one of Th1, Th2 are true, or Th1, Th2 are when being true, should
Cycle discriminator signal is true, depending on to judging the different requirements of the cycle signal true and false.
If system fault, when N be more than 25 to 70 between a setting value when, due to main controller in system and each fan
Controller, Tz values and the N values of its detection may be different, at this moment, power network frequency accumulated error, when being likely to result in synchrotimer
Between cannot by detecting true cycle signal when corrected, when it is true to detect cycle signal, at this moment using clock meter
When device accumulative clocking value be directly added in synchrotimer, to reduce the asynchronous time of system, add up clocking value be N × Tz
+20ms.N is much smaller than 25 in the case of power network normal operation.
The cycle time error Tzv of permission and the flip-flop transition setting value of voltage comparator output voltage, by test assessment
Take the acquisition of its average value.
(4) illustrate：
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structural representation；
Fig. 3 is the circuit structure block diagram of parlor fan natural wind control system.
(5) specific embodiment：
Fig. 3 is that parlor fan natural wind control system circuit block diagram includes:The ﹚ of Zhu Kong Qi ﹙ 10, communications electronics are opened
The ﹚ of Guan ﹙ 11, the ﹚ of switch Qu dynamic model Kuai ﹙ 12, infra-red remote control are generated the ﹚ of She Qi ﹙ 13, the ﹚ of 14 ﹚, electricity Feng Shan ﹙ of electricity Kai Guan ﹙ 15, cycle and are screened
The ﹚ of electricity Lu ﹙ 16 ﹚, Feng fan Kong Qi ﹙ 17.The wherein ﹚ of communications electronics Kai Guan ﹙ 11, the ﹚ of switch Qu dynamic model Kuai ﹙ 12, cycle screen electricity Lu ﹙
Dan Pian Ji ﹙ U0 ﹚ are respectively included in the ﹚ of 17 ﹚ and Zhu Kong Qi ﹙ of Feng fan Kong Qi ﹙ 10 in 16 ﹚ and Fig. 2.It is the ﹚ of electricity Kai Guan ﹙ 14, logical
The ﹚ of letter electricity Kai Guan ﹙ 11 use bidirectional triode thyristor as switch.
Fig. 2 is the structural representation that cycle screens the ﹚ of electricity Lu ﹙ 16, by：Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian and surveys Mo Kuai ﹙
V0 ﹚, electricity pressure comparator ﹙ V1 ﹚ and electricity pressure comparator ﹙ V2 ﹚ are constituted.Dan Pian Ji ﹙ U0 ﹚ refer to ﹚ the and Zhu Kong Qi ﹙ of Feng fan Kong Qi ﹙ 17
Single-chip microcomputer in 10 ﹚.Shu enters electricity Lu ﹙ S0 ﹚ and, by resistance and the partial pressure of diode, is converted to electricity for by mains AC voltage
The input voltage of pressure comparator suitably stabilization.Dan Pian Ji ﹙ U0 ﹚ use 89C55WD.Electricity pressure comparator ﹙ V1 ﹚, electricity pressure comparator ﹙
V2 ﹚ use special voltage comparator LM393, and its reference voltage is compared come burning voltage using the mu balanced circuit of voltage-stabiliser tube
The threshold voltage of device.
When mains AC voltage cycle signal zero passage, voltage zero-cross Jian surveys the output voltage saltus step of Mo Kuai ﹙ V0 ﹚, single
Pian Ji ﹙ U0 ﹚ produce interruption, the break period are recorded, while Dan Pian Ji ﹙ U0 ﹚ are additionally operable to scanning voltage Bi compare Qi ﹙ V1 ﹚ and voltage ratio
The output voltage of compare Qi ﹙ V2 ﹚, records bound-time, for judging power network cycle signal so as to produce when output voltage saltus step
Raw lock in time.
The ﹚ of Zhu Kong Qi ﹙ 10 are provided with integrated infrared receiving terminal, and the ﹚ emission instruction signals of infra-red remote control Fa She Qi ﹙ 13 are main
When integrated infrared receiving terminal receives infrared command signal in the ﹚ of control device ﹙ 10, the infrared signal is become into electric signal and send preceding storing
Big circuit is amplified, then after demodulated device, is detected command signal by signal detection circuit, realizes various operations.
Claims (2)
1. a kind of parlor fan natural wind control system, it is characterized in that, an electronic switch, the electricity are installed after air switch
Sub switch parallel connection isolating diode, is respectively mounted cycle discriminator circuit, for generation system in main controller and each fan governor
Lock in time, while each in its telecommunication circuit install communications electronics switch, a switch drive module, each fan governor
Output through Phototube Coupling and bidirectional triode thyristor be serially connected with former socket or switch on, electric fan insert on socket or be connected to switch electricity
Lu Zhong；During communication, civil power sends into system through isolating diode, and system is in through half wave communication half-wave power supply state of power line,
Each fan governor also can't detect power network be rectified diode blocking half-wave voltage signal when, connect communications electronics switch；
Infra-red remote control transmitter sends operational mode command signal, and infrared receiver device receives infra-red remote control transmitter in main controller
Infrared command signal when, it by infrared signal become electric signal implementation pattern change and various operations；Communications electronics are switched
Switch drive module be from electric power netting twine be depressured through resistance after point two-way, all the way for each fan governor, it is through reversal connection two
Pole pipe is connected to the single-chip processor i/o mouthful of each fan governor, when half-wave is born in clock timer timing to cycle, scans the I/O mouthfuls,
If being that system is in half-wave communications status without signal, another road is used for each fan governor and main controller, and the road is through resistance
Partial pressure is followed by the CLK ends of d type flip flop, the external interrupt mouthful of the Q termination single-chip microcomputers of d type flip flop, when the positive square-wave signal at CLK ends is arrived
When coming, its rising edge sets to 0 d type flip flop, and external interrupt mouthful low level produces interruption, is communicated；
Cycle discriminator circuit is, using the positive half cycle ascent stage of power network cycle, to take three and screen knowledge of the point realization to cycle signal
Do not judge, recycle the cycle time to set up lock in time, system sets clock timer and synchrotimer, if detecting phase
The two cycle signals for facing are very, then when taking out the clock timer timing between this two adjacent cycle signal zero passages
Between, sequentially it is stored in cycle time memory cell, a cycle time is often stored in when being filled with 100 cycle time, first remove
The cycle time being stored at first, and the average value Tz of the cycle time being stored in is calculated, differentiate cycle to be identified using Tz values
Signal；
Two comparators are respectively used to screen point 1, screen point 2, at the cycle zero passage of cycle positive half cycle ascent stage, that is, screen a little
0 set voltage zero-cross detection module, it using cycle positive half-wave signal through electric resistance partial pressure, diode further isolate negative half period,
The clock end CLK of d type flip flop is sent into after signal condition, when cycle positive half-wave zero cross signal arrives, cycle letter immediately after
Number rising edge makes d type flip flop Q ends be 0, single-chip microcomputer external interrupt mouthful low level, so as to produce interruptions, remaining two comparator divides
Cycle positive half cycle ascent stage, the examination point 1 at 35% to 50% place of crest voltage and the examination at 50% to 70% place are not arranged on
Point 2；
Cycle signal determining：After setting time opens interruption, clock timer resets and starts timing single-chip microcomputer, when all wave voltages
During zero passage, the output voltage for being arranged on d type flip flop in the voltage zero-cross detection module for screening point 0 jumps vanishing, produces interruption, note
Record its zero crossing break period Th0；Hereafter, the output voltage of electricity pressure comparator ﹙ V1 ﹚ at point 1 is screened in single-chip microcomputer scanning, works as cycle
When voltage reaches the threshold voltage of electricity pressure comparator ﹙ V1 ﹚, output voltage saltus step from high to low, scanning records its bound-time
Th1；Same scanning record screens electricity pressure comparator ﹙ V2 ﹚ output voltage bound-time Th2 at point 2, if the bound-time
In the range of allowable error, then the discriminator signal for detecting is true for Th1 and Th2, be otherwise it is false, it is above-mentioned judge discriminator signal as
When true, the clock timing between cycle signal zero passage when this cycle signal zero passage is true with an adjacent preceding discriminator signal is calculated
Device timing time Tzu, it is made comparisons with the average value Tz of cycle time, if no more than setting cycle time error Tzv
Cycle signal is true, at this moment preserves Tzu and takes 20ms and be added with synchrotimer timing time, and the value that will add up is stored in synchronometer
When device in；
When clock timer starts timing with cycle voltage zero-cross, then timing opens break period setting between 16ms to 18.5ms
Open interruption during value Tk, clock timer timing is broken to Central Shanxi Plain during pass break period setting value Tn between 25ms to 27ms；
When first cycle voltage zero-cross is detected, the output voltage for being arranged on the voltage zero-cross detection module for screening point 0 is jumped
Become, so as to produce interruption, the time T0 for taking out cycle voltage over zero is preserved, and clock timer is reset and starts timing, this
Shi Zhoubo time voltage crosses zeros Th0 is 0, and single-chip microcomputer is scanned and judges discriminator signal as stated above, its Th0, Th1 and Th2's
Value must add the difference that cycle time 20ms subtracts out break period setting value Tk, if three discriminator signals are true, take out
The time T0 of cycle voltage over zero be stored in synchrotimer as initial time, open the break period for the first time next time
Tk is taken, is otherwise fictitious time, now the clock timer time must be plus T0, and continuation is detected；
Then it is to take 20ms to subtract when judging cycle signal as true when first and second adjacent cycle voltage zero-cross is detected
The difference of Th0 is added with synchrotimer timing time, and clock timer resets after opening interruption, otherwise judges cycle signal as false
When, now the clock timer time must be plus T1=T0+Tk, and continuation detects first cycle again as stated above, works as detection
First cycle signal be very after, recover above-described cycle signal determining；
If it is false to detect cycle signal, the break period is opened next time after this opens the break period, during through time delay cycle
Between average value Tz when open interruption, and open interrupt after time delay Tns when the Central Shanxi Plain break, it is when cycle signal Zhen to set and close the break period
Not Wei fictitious time, the break period Tns Central Shanxi Plain is disconnected and stop scanning closing, and Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
Opened after the break period takes Tk from first time, clock timer is opened again after timing opens interruptions, and clearing to Tks
Beginning timing, timing is disconnected to Central Shanxi Plain during Tns；
Said process is repeated, if the upper cycle signal for detecting is true, when this cycle judges, discriminator signal is vacation,
Then when clock timer timing is to Tns, the Central Shanxi Plain is broken, and is at this moment remembered and is not counted cycle N 1 and to store, and is opened the break period next time and is
The break period was opened by opening interruption, clock timer clearing and timing, timing to Central Shanxi Plain during Tns after interruption is opened after Tz in last time
It is disconnected, the cycle signal true and false is hereafter judged every time, though if false or this detection discriminator signal be false true last time, then take N, will
Restored in memory after N+1；
When it is true to detect cycle signal, then N is preserved in taking out memory, and by N zero setting in memory, and is recovered using setting
Definite value Tks, the value at this moment taking (N+1) × 20ms is added in synchrotimer；
The system synchronization time for synchrotimer time, along with currently just timing clock timer time；
When judging to screen the point signal true and false, selection：The cycle discriminator signal is true when Th0, Th1, Th2 are true, or Th0 is
When one of true and Th1, Th2 are true, or Th1, Th2, when being true, the cycle discriminator signal is true, depending on true to judging cycle signal
Depending on pseudo- different requirements, if N is more than a setting value between 25 to 70, the accumulative clocking value using clock timer is direct
It is added in synchrotimer, it is N × Tz+20ms to add up clocking value.
2. a kind of parlor fan natural wind control system according to claim 1, it is characterised in that including:
The ﹚ of Zhu Kong Qi ﹙ 10, the ﹚ of communications electronics Kai Guan ﹙ 11, the ﹚ of switch Qu dynamic model Kuai ﹙ 12, the ﹚ of infra-red remote control Fa She Qi ﹙ 13, electronic cutting
The ﹚ of 14 ﹚, electricity Feng Shan ﹙ of Guan ﹙ 15, cycle screen the ﹚ of 16 ﹚, Feng fan Kong Qi ﹙ of electricity Lu ﹙ 17, and wherein Dan Pian Ji ﹙ U0 ﹚ and communications electronics are opened
The ﹚ of Guan ﹙ 11, the ﹚ of switch Qu dynamic model Kuai ﹙ 12, cycle screen the ﹚ of electricity Lu ﹙ 16 and are respectively included in ﹚ the and Zhu Kong Qi ﹙ of Feng fan Kong Qi ﹙ 17
In 10 ﹚；
Cycle screen the ﹚ of electricity Lu ﹙ 16 by：Shu Ru electricity roads ﹙ S0 ﹚, voltage zero-cross inspection survey mould block ﹙ V0 ﹚, electricity pressure comparator ﹙ V1 ﹚ and voltage
Bi compare Qi ﹙ V2 ﹚ are constituted, and Shu enters electricity Lu ﹙ S0 ﹚ and, by resistance and the partial pressure of diode, is converted to for by mains AC voltage
The input voltage of voltage comparator suitably stabilization；
The ﹚ of Zhu Kong Qi ﹙ 10 are provided with integrated infrared receiving terminal, the ﹚ emission instruction signals of infra-red remote control Fa She Qi ﹙ 13, Zhu Kong Qi ﹙
10 ﹚ are by after reception and signal transacting, realizing various operations.
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| CN201610448468.6A CN106089782B (en) | 2016-06-20 | 2016-06-20 | Parlor fan natural wind control system |
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| CN201610448468.6A CN106089782B (en) | 2016-06-20 | 2016-06-20 | Parlor fan natural wind control system |
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|---|---|---|---|---|
| JP2004120930A (en) * | 2002-09-27 | 2004-04-15 | Nishishiba Electric Co Ltd | Fault detection device of power conversion element |
| US7190124B2 (en) * | 2005-05-16 | 2007-03-13 | Lutron Electronics Co., Inc. | Two-wire dimmer with power supply and load protection circuit in the event of switch failure |
| JP4524219B2 (en) * | 2005-06-08 | 2010-08-11 | 矢崎総業株式会社 | Flying capacitor voltage measuring device |
| CN100485734C (en) * | 2007-07-17 | 2009-05-06 | 东北大学 | Electric energy quality and electrical power system malfunction detection wave recording device and method |
| CN101788615B (en) * | 2010-01-11 | 2011-12-14 | 中色科技股份有限公司 | Simple method for detecting phase sequence of three-phase industrial-frequency alternating current and detection device |
| CN103558476B (en) * | 2013-11-09 | 2015-11-11 | 张金木 | A kind of high-voltage fence condition monitoring system |
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2016
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| CN106089782A (en) | 2016-11-09 |
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Effective date of registration: 20191204 Address after: 528300 1st floor, No.8, Xiangan North Road, Jun'an community residents committee, Jun'an Town, Shunde District, Foshan City, Guangdong Province Patentee after: Foshan Shunde nengqu Electronic Technology Co., Ltd Address before: The riverside road in Taijiang District of Fuzhou City, Fujian Province, No. 180 350004 Patentee before: Fuzhou Taijiang Chaoren Electronic Co., Ltd. |
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