CN105960060B - Park L ED landscape lamp post control system - Google Patents
Park L ED landscape lamp post control system Download PDFInfo
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- CN105960060B CN105960060B CN201610447841.6A CN201610447841A CN105960060B CN 105960060 B CN105960060 B CN 105960060B CN 201610447841 A CN201610447841 A CN 201610447841A CN 105960060 B CN105960060 B CN 105960060B
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
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- Measurement Of Unknown Time Intervals (AREA)
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Abstract
The invention relates to a park L ED landscape lamp post control system, which communicates through a power network cable, wherein each L ED landscape lamp post completes the overall lighting effect under the control of synchronization time and each L ED landscape lamp post software, and the display mode selection is to select the number of L ED lamps to be turned on for power-off storage when each lighting controller sequentially and jointly displays different numbers of L ED lamps in a period of time just after the power-on, so as to obtain the display modes corresponding to the number.
Description
(1) technical field：
The present invention relates to a kind of park LED landscape lamp column control systems, are communicated therebetween by electric power cable.Each LED landscapes
Lamppost completes overall light decorative effect under synchronization time and the control of each LED landscape lamp column software.Its display pattern selection be
Just a period of time after start, when each lamp controller sequentially show different number LED light jointly, the number lighted of selection LED light
Amount shutdown preserves, and obtains and the corresponding display pattern of the quantity.
(2) background technology：
The control system of power supply is provided by power network, each electronic equipment or intermodule are communicated by special circuit,
The timing time of each electronic equipment or electronic module is corrected, reaches synchronous operation purpose.Due to being made using special circuit communication
Wiring complicates and increases cost, if timing time is not corrected by line traffic, due to traditional timing error, runs number
After hour, accumulation timing error can make system control action inconsistent, may cause system crash, and at some, often change is set
Meter, its products application of the big occasion of wiring installation amount are restricted.
(3) content of the invention：
Using the LED light decoration system of preset collaboration Synchronization Control, such as the LED light of internal control mode between existing each LED light
Decorations, it is to realize Synchronization Control, since the timing accumulated error of conventional timing mode is big, each LED light using conventional timing mode
A kind of lamp decoration pattern of completing can only be limited in finite time, and light decorative effect cannot be made very complicated.The present invention relates to parks
LED landscape lamp column control system establishes the synchronization time corrected by grid cyclic wave, enables the system to keep permanent synchronization, anti-interference
Ability is strong.The LED landscape lamp column by park road is stood on, is made of LED point light source, each LED landscape lamp column has controller
Control wherein LED point light source is lighted and changed colour.Each LED landscape lamp column is connected to same power network, with a master switch, total
One electronic switch after switch is installed, its break-make is controlled by main controller, main controller AC power is connected to electronic switch with always opening
Between pass, and a communications electronics switch is respectively installed in the telecommunication circuit of main controller and each controller, each controller
Ac power input end sets insulating electron to switch.In the communication synchronization time, main controller shut-off electronic switch simultaneously connects its communication
Electronic switch, each controller are connected each logical also in the synchronization time of the communication of setting or when not receiving grid cyclic wave signal
Believe electronic switch, shut-off insulating electron switch is communicated by electric power cable, transmitted from main controller to each controller and show mould
The data of formula, parameter and display content after sign off, turn off all communications electronics switches, then connect electronic switch and isolation
Electronic switch, at this moment, synchrotimer restart timing after resetting and are corrected, and to keep system synchronization, and remember synchronization
The accumulated value of timing.Communication period is powered by the rechargeable battery for being connected to microcontroller power supply filter capacitor, and through diode
Isolate with former rectification circuit, the charging circuit of rechargeable battery possesses charging protection function.It is each to control in the case where synchronization time controls
Gradually bright, gradually dark, the various Display patterns such as beat, pile up, and keeping of LED landscape lamp column are completed in the preset software collaboration cooperation of device processed
Permanent synchronization rule is shown.
Its display pattern selects, and is a period of time after firm start, and each lamp controller sequentially lights different numbers jointly
When measuring LED light, the quantity of LED light is selected to shut down and is preserved, obtains lighting the corresponding display pattern of quantity with this, it is to number
Period, number data were stored in non-volatile deposit by microcontroller by the energy storage of its power capacitor when can't detect grid cyclic wave signal
In reservoir.
The present invention utilizes the positive half cycle ascent stage of power network cycle, takes three to screen point and realize and the identification of cycle signal is sentenced
It is fixed, the cycle time is recycled to establish synchronization time, the synchronous operation of main controller and each controller in realization system.
The cycle identification circuit of main controller and each controller is as shown in Fig. 2, by three voltage ratios using hysteresis loop comparator
It is formed compared with device, comprising filter circuit in each voltage comparator, the reference voltage of voltage comparator is provided by regulator circuit.
System sets clock timer and synchrotimer.If detecting that two adjacent cycle signals are true, take out this two
Clock timer timing time between a adjacent cycle signal zero passage is sequentially stored in cycle time memory cell, this week
Ripple time memory cell can store 100 cycle times, and a cycle time is often stored in when being filled with, first removes what is be stored at first
One cycle time, and calculate the average value Tz of the cycle time of deposit and preserve, differentiate cycle signal to be identified using Tz values,
Erroneous judgement possibility is reduced to reduce the influence of power network frequency fluctuation, while point is screened using three.
Three comparators are respectively used to three examination points, that is, screen point 0, screen point 1, screen point 2, as shown in Figure 1.In week
At the cycle zero passage of ripple positive half cycle ascent stage, that is, screen point 0 and voltage zero-crossing comparator is set, remaining two comparator is set respectively
In the cycle positive half cycle ascent stage, the examination point 1 at 35% to 50% place of crest voltage and the examination point 2 at 50% to 70% place.
Cycle signal determining：After setting time opens interruption, clock timer resets and starts timing microcontroller, works as cycle
During voltage zero-cross, the output voltage overturning for the voltage zero-crossing comparator V0 for screening point 0 is arranged on, in the generation of its voltage trailing edge
It is disconnected, it records its zero crossing break period Th0 and the Central Shanxi Plain is broken；Hereafter, the output of voltage comparator V1 at point 1 is screened in microcontroller scanning
Voltage, when all wave voltages reach the threshold voltage of V1, output voltage is overturn from high to low, and scanning records its flip-flop transition Th1；
Similary scanning record screens voltage comparator V2 output voltage flip-flop transition Th2 at point 2, by Th0 and voltage zero-crossing comparator V0
Output voltage flip-flop transition setting value Ts0 make comparisons；The output voltage flip-flop transition setting value of Th1 and voltage comparator V1
Ts1 and Th2 makes comparisons respectively with the output voltage flip-flop transition setting value Ts2 of voltage comparator V2, if in allowable error
In the range of, then the discriminator signal detected is true, is otherwise false.When above-mentioned judgement discriminator signal is true, this cycle is calculated
The clock timer timing time Tzu between cycle signal zero passage when signal zero passage and an adjacent preceding discriminator signal are true, will
It makes comparisons with the average value Tz of cycle time, and cycle signal is true if being no more than and setting cycle time error Tzv, at this moment
It preserves Tzu and 20ms is taken to be added with synchrotimer timing time, in the value deposit synchrotimer that will add up.
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens the break period between 18.5ms
Open interruption during setting value Tk, clock timer timing to 25ms to Central Shanxi Plain during pass break period setting value Tn between 27ms is broken.
After system boot, clock timer starts timing, when detecting first cycle voltage zero-cross, is arranged on examination
The output voltage overturning of the voltage zero-crossing comparator V0 of point 0, is interrupted so as to generate, and the time T0 for taking out cycle voltage over zero is protected
It deposits, clock timer is reset and starts timing, at this moment cycle time voltage crosses zero Th0 is 0, while microcontroller is as stated above
It scans and judges discriminator signal.What it is due to detection is first cycle, and clock timer is to start to count in cycle voltage zero-cross
When, the value of Th0, Th1 and Th2 must add the difference that cycle time 20ms subtracts out break period setting value Tk, if three
A discriminator signal is true, and i.e. opening the break period for the first time takes Tk next time.Otherwise for fictitious time, at this time the clock timer time must add
Upper T0 continues to detect.
When detecting first and second adjacent cycle voltage zero-cross, due to not preserving the cycle time of detection,
Therefore the clock timer timing time twice between cycle signal zero passage is made comparisons with cycle time 20ms, judges cycle signal
When being true, then take out clock timer cumulative time T1=T0+Tk when opening interruption and be stored in synchrotimer as initial time
In, open interruption after clock timer reset, otherwise judge cycle signal be fictitious time, at this time the clock timer time must add T1,
Continue to detect first cycle again as stated above.After it is very to detect first cycle signal, recover above-described week
Ripple signal determining.
If as shown in Figure 1, detecting that cycle signal is false, the break period is opened next time and opens the break period at this
Afterwards, open interruptions during average value Tz through the cycle time that is delayed, and open interrupt after be delayed Tns when the Central Shanxi Plain break, when setting the Central Shanxi Plain to break
Between be when cycle signal screen point 0 when do not generating interruption, at this moment must be in the setting time point more than Ts0 allowable error scopes
When starting to scan and scanning examination point 1 and screen point 2, voltage comparator output voltage does not generate overturning, all breaks in the Central Shanxi Plain
Scanning is broken and is stopped in the time Tns Central Shanxi Plain, and Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is that timing opens interruption to Tks, and weight after resetting
New to start timing, timing is broken to Central Shanxi Plain during Tns, so that the synchrotimer time is corrected be subject to cycle time voltage crosses zero.
It repeats the above process.If the upper cycle signal detected is true, when this cycle judges, discriminator signal is
Vacation or the cycle time detected are more than setting cycle time error Tzv or clock meter compared with the average value Tz of cycle time
When device timing to close break period setting value Tns when, voltage zero-crossing comparator V0 output voltages are not overturn, do not generate interruption,
Then when clock timer timing is to Tns, the Central Shanxi Plain is broken, and is at this moment remembered and is not counted cycle N 1 and to store, and is opened the break period next time and is
The break period was opened in last time, interruption is opened after Tz, hereafter judge the cycle signal true and false every time, if false or this detection is screened
Though signal is true but last time is false, then N is taken, will be restored after N+1 in memory, clock timer does not reset continuation after interruption is opened
Timing, at this moment, next cycle of setting open the break period and temporarily use out break period interim setting value Tkz instead：
Tkz=(N+1) × Tz
Meanwhile next cycle closes break period temporary use instead and closes break period interim setting value Tnz：
Tnz=Tkz+Tns
When clock timer to after Tkz, the time that point is screened in scanning can be obtained by simple computation.If it at this moment examines
It is true to measure cycle signal, then takes out in memory N and preserve, and by N zero setting in memory, makes clock timer clocking value Ts
For：(Ts-Tkz) at this moment → Ts takes the value of (N+1) × 20ms to be added in synchrotimer, and recover using setting value Tks with
Tns, recovered clock timer are reset after interruption is opened.
The system synchronization time be synchrotimer time, along with currently just timing clock timer time.
When judging to screen the point signal true and false, Th0, Th1, Th2 are by being set with voltage comparator output voltage flip-flop transition
Definite value Ts0, Ts1, Ts2 make comparisons see it is whether overproof, come judge screen point a signal true and false, can select：Th0, Th1, Th2 are
The cycle discriminator signal is true when true or Th0 is true, while when one of Th1, Th2 are true or when Th1, Th2 are true, it should
Cycle discriminator signal is true, depending on to judging the different requirements of the cycle signal true and false.
If system fault, when N is more than a setting value between 25 to 70, due to main controller in system and each control
Device, detection Tz values and N values possibility it is different, at this moment, power network frequency accumulated error, may cause the synchrotimer time without
It is corrected when method is by detecting true cycle signal, when it is true to detect cycle signal, using clock timer in Tkz
The clocking value at place is directly added in synchrotimer, and to reduce the asynchronous time of system, N is remote in the case of power network normal operation
Less than 25.
The cycle time error Tzv of permission and the flip-flop transition setting value of voltage comparator output voltage, by test assessment
Its average value is taken to obtain.
(4) illustrate：
Fig. 1 is that cycle screens data relationship schematic diagram；
Fig. 2 is cycle discriminator circuit structure diagram；
Fig. 3 is the circuit structure block diagram of park LED landscape lamp column control system.
(5) specific embodiment：
Fig. 3 is the circuit structure block diagram of park LED landscape lamp column control system, including:10 ﹚ of Zhu Kong Qi ﹙, communications electronics
11 ﹚ of Kai Guan ﹙, cycle screen 12 ﹚ of electricity Lu ﹙, 13 ﹚ of Kong Qi ﹙, 14 ﹚ of LED Deng ﹙, electricity Kai Guan ﹙ 15 ﹚, wherein communications electronics Kai Guan ﹙
11 ﹚ and cycle are screened Dan Pian Ji ﹙ U0 ﹚ in 12 ﹚ and Fig. 2 of electricity Lu ﹙ and are respectively included in 13 ﹚ of Kong Qi ﹙ and 10 ﹚ of Zhu Kong Qi ﹙.It is logical
11 ﹚ and electricity Kai Guan ﹙ of letter electricity Kai Guan ﹙, 15 ﹚ use bidirectional triode thyristor as switch.
Fig. 2 is the structure diagram that cycle screens 12 ﹚ of electricity Lu ﹙, by：Shu enters electricity Lu ﹙ S0 ﹚, voltage zero-cross Jian and surveys Mo Kuai ﹙
V0 ﹚, electricity pressure comparator ﹙ V1 ﹚ and electricity pressure comparator ﹙ V2 ﹚ are formed.Single piece machine ﹙ U0 ﹚ are that 13 ﹚ of control device ﹙ are controlled with main in 10 ﹚ of device ﹙
Microcontroller.Shu enters electricity Lu ﹙ S0 ﹚ for the partial pressure by mains AC voltage by resistance and diode, is converted to voltage ratio
The suitably stable input voltage compared with device.Dan Pian Ji ﹙ U0 ﹚ survey Mo Kuai ﹙ V0 ﹚ using 89C55WD voltage zero-cross Jian, voltage compares
Using dedicated voltage comparator LM339, reference voltage is the voltage stabilizing using voltage-stabiliser tube by device ﹙ V1 ﹚, electricity pressure comparator ﹙ V2 ﹚
Circuit carrys out the threshold voltage of burning voltage comparator.
When mains AC voltage cycle signal zero passage, voltage zero-cross Jian surveys the output voltage saltus step of Mo Kuai ﹙ V0 ﹚, single
Pian Ji ﹙ U0 ﹚ generate interruption, record the break period, while Dan Pian Ji ﹙ U0 ﹚ are additionally operable to scanning voltage Bi compare Qi ﹙ V1 ﹚ and voltage ratio
The output voltage of compare Qi ﹙ V2 ﹚, bound-time is recorded when output voltage saltus step, for judging power network cycle signal so as to producing
Raw synchronization time.
Claims (2)
1. one kind is related to park LED landscape lamp column control system, it is characterized in that, the synchronization time corrected by grid cyclic wave is established,
One electronic switch after master switch is installed, break-make is controlled by main controller, main controller AC power be connected to electronic switch with it is total
Between switch, in the communication synchronization time, each controller the communication of setting synchronization time or do not receive grid cyclic wave signal
When, respective communications electronics switch is connected, shut-off insulating electron switch is communicated by grid line, after sign off, synchrotimer
Restart timing after clearing and corrected, to keep system synchronization, and remember the accumulated value of time synchronisation；Communication period relies on
It is connected to the rechargeable battery power supply of the power filtering capacitor of microcontroller；Display pattern selects, when being one section after firm start
Between, the quantity shutdown of lighting of LED light is selected to preserve, obtains lighting the corresponding display pattern of quantity with this, work as in the number period
When can't detect grid cyclic wave signal, number data are stored in non-volatile memory by microcontroller by the energy storage of its power filtering capacitor
In device；
Using the positive half cycle ascent stage of grid cyclic wave, take three to screen identification decision of the point realization to cycle signal, recycle week
The ripple time establishes synchronization time, and the cycle identification circuit of each controller is by three voltage comparator groups using hysteresis loop comparator
Into comprising filter circuit in each voltage comparator, the reference voltage of voltage comparator is provided by regulator circuit, and system is set
Clock timer and synchrotimer, if detecting that two adjacent cycle signals are true, take out this two it is adjacent
Clock timer timing time, that is, cycle time between cycle signal zero passage is sequentially stored in cycle time memory cell, deposits
A cycle time is often stored in during the full 100 cycle time, the cycle time being stored at first is first removed, and calculates deposit
The cycle time average value Tz and preserve, Tz values is utilized to differentiate cycle signal to be identified；
Three comparators are respectively used to three examination points, that is, screen point 0, screen point 1, screen point 2, in the cycle positive half cycle ascent stage
Cycle zero passage at, that is, screen point 0 and a voltage zero-crossing comparator be set, remaining two comparator is separately positioned in cycle positive half cycle
Rise section, the examination point 1 at 35% to 50% place of crest voltage and the examination point 2 at 50% to 70% place；
Cycle signal determining process：After setting time opens interruption, clock timer resets and starts timing microcontroller, works as cycle
During voltage zero-cross, the output voltage overturning for the voltage zero-crossing comparator (V0) for screening point 0 is arranged on, is generated in its voltage trailing edge
It interrupts, record cycle time voltage crosses zero Th0 simultaneously breaks in the Central Shanxi Plain；Hereafter, voltage comparator (V1) at point 1 is screened in microcontroller scanning
Output voltage, when all wave voltages reach the threshold voltage of voltage comparator (V1), output voltage is overturn from high to low, scanning note
Record its flip-flop transition Th1；Similary scanning record screens voltage comparator (V2) output voltage flip-flop transition Th2 at point 2, if on
Flip-flop transition Th1 and flip-flop transition Th2 are stated in the range of allowable error, then the discriminator signal detected be it is true, otherwise for
Vacation when above-mentioned judgement discriminator signal is true, calculates week when this cycle signal zero passage and an adjacent preceding discriminator signal are true
Clock timer timing time Tzu between ripple signal zero passage makes comparisons with the average value Tz of cycle time, if no more than setting
Then cycle signal is true to cycle time error Tzv, at this moment preserves Tzu and 20ms is taken to be added with synchrotimer timing time, will
In the value deposit synchrotimer of addition；
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens break period setting between 18.5ms
Open interruption during value Tk, clock timer timing to 25ms to Central Shanxi Plain during pass break period setting value Tn between 27ms is broken；
After system boot, clock timer starts timing, when detecting first cycle voltage zero-cross, is arranged on examination point 0
Voltage zero-crossing comparator (V0) output voltage overturning, so as to generate interrupt, take out cycle voltage over zero time T0 protect
It deposits, clock timer is reset and starts timing, at this moment cycle time voltage crosses zero Th0 is 0, while microcontroller is as stated above
It scans and judges discriminator signal, the value of Th0, Th1 and Th2 must subtract open break period setting value plus cycle time 20ms
The difference of Tk, if three discriminator signals are true, next time detect cycle voltage over zero break period of opening take Tk, otherwise for
Fictitious time, at this time the clock timer time must add T0, continue to detect；
When detecting first and second adjacent cycle voltage zero-cross, when judgement cycle signal is true, then take out in opening
Clock timer cumulative time T1=T0+Tk when disconnected is stored in as initial time in synchrotimer, opens clock meter after interruption
When device reset, otherwise judge cycle signal be fictitious time, at this time the clock timer time must add T1, again detect the first week
Ripple after it is very to detect first cycle signal, recovers above-described cycle signal determining；
If it is false to detect cycle signal, open the break period next time after this opens the break period, through be delayed cycle when
Between average value Tz when open interruption, and open interrupt after be delayed Tns when the Central Shanxi Plain break, it is when cycle signal exists to set and close the break period
It screens as fictitious time, breaks and stops to scan closing the break period Tns Central Shanxi Plain, Tns is:
Tns=Tn-Tk
If it is true to detect cycle signal, next cycle opens break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is that timing opens interruption to Tks, and is opened again after resetting
Beginning timing, timing are broken to Central Shanxi Plain during Tns, so that the synchrotimer time is corrected be subject to cycle time voltage crosses zero；
Above-mentioned cycle signal determining process is repeated, if the upper cycle signal detected is true, when this cycle judges, is discriminated
It vacation or the cycle time detected is more than setting cycle time error Tzv compared with the average value Tz of cycle time that level signal, which is,
Or clock timer timing, to when closing break period setting value Tns, voltage zero-crossing comparator (V0) output voltage is not overturn, is not had
Interruption is generated, then the Central Shanxi Plain is broken when clock timer timing is to Tns, at this moment remembers that not counting cycle N is 1 and stores, and opens next time
Break period is to open the break period in last time to open interruption after Tz, hereafter judges the cycle signal true and false every time, if false or originally
Though secondary detection discriminator signal is true but last time is false, then stored N is taken out, and will be restored after N+1 in the memory of storage N
In, clock timer does not reset continuation timing after interruption is opened, and at this moment, next cycle of setting is opened the break period and temporarily used instead open
Break period interim setting value Tkz：
Tkz=(N+1) × Tz
Meanwhile next cycle closes break period temporary use instead and closes break period interim setting value Tnz：
Tnz=Tkz+Tns
When clock timer to after Tkz, the time that point is screened in scanning is obtained by simple computation, if at this moment detecting week
Ripple signal is true, then takes out in memory N and preserve, and by N zero setting in memory, makes the clock timer clocking value Ts be：(Ts-
Tkz at this moment) → Ts takes the value of (N+1) × 20ms to be added in synchrotimer, and recover, using setting value Tks and Tns, to recover
Clock timer is reset after interruption is opened；
The system synchronization time be synchrotimer time, along with currently just timing clock timer time；
When judging to screen the point signal true and false, selection：Cycle discriminator signal is true when Th0, Th1, Th2 are true or Th0 is
Very, when while one of Th1, Th2 are true or when Th1, Th2 are true, cycle discriminator signal is true；
When N is more than a setting value between 25 to 70, synchronometer is directly added on using clocking value of the clock timer at Tkz
When device in.
2. LED landscape lamp column control system in park according to claim 1, it is characterised in that including:
10 ﹚ of Zhu Kong Qi ﹙, 11 ﹚ of communications electronics Kai Guan ﹙, cycle screen 12 ﹚ of electricity Lu ﹙, 13 ﹚ of Kong Qi ﹙, 14 ﹚ of LED Deng ﹙, electronic cutting
All set in 15 ﹚ of Guan ﹙, wherein 13 ﹚ and Zhu Kong Qi ﹙ of Kong Qi ﹙, 10 ﹚ 11 ﹚ of communications electronics Kai Guan ﹙ and cycle screen 12 ﹚ of electricity Lu ﹙ and
Dan Pian Ji ﹙ U0 ﹚；
Cycle screens 12 ﹚ of electricity Lu ﹙, by：Shu Ru electricity roads ﹙ S0 ﹚, voltage Zero-cross comparator device ﹙ V0 ﹚, electricity pressure comparator ﹙ at point 1 is screened
V1 ﹚ press comparator ﹙ V2 ﹚ compositions with electricity at point 2 is screened；Shu enters electricity Lu ﹙ S0 ﹚ for grid ac voltage to be passed through resistance and two poles
The partial pressure of pipe is converted to the suitably stable input voltage of voltage comparator.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610447841.6A CN105960060B (en) | 2016-06-20 | 2016-06-20 | Park L ED landscape lamp post control system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610447841.6A CN105960060B (en) | 2016-06-20 | 2016-06-20 | Park L ED landscape lamp post control system |
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| CN105960060B true CN105960060B (en) | 2018-05-22 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6348766B1 (en) * | 1999-11-05 | 2002-02-19 | Avix Inc. | Led Lamp |
| CN102841247A (en) * | 2012-08-30 | 2012-12-26 | 惠州三华工业有限公司 | Detection method for grid frequency |
| CN104360144A (en) * | 2014-12-08 | 2015-02-18 | 广东美的环境电器制造有限公司 | Method for determining zero crossing point of alternating current signal and system for determining zero crossing point of alternating current signal |
| DE102013220397A1 (en) * | 2013-10-10 | 2015-04-16 | Ruling Technologies Sdn. Bhd. | Method and control device for operating at least one light source |
-
2016
- 2016-06-20 CN CN201610447841.6A patent/CN105960060B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6348766B1 (en) * | 1999-11-05 | 2002-02-19 | Avix Inc. | Led Lamp |
| CN102841247A (en) * | 2012-08-30 | 2012-12-26 | 惠州三华工业有限公司 | Detection method for grid frequency |
| DE102013220397A1 (en) * | 2013-10-10 | 2015-04-16 | Ruling Technologies Sdn. Bhd. | Method and control device for operating at least one light source |
| CN104360144A (en) * | 2014-12-08 | 2015-02-18 | 广东美的环境电器制造有限公司 | Method for determining zero crossing point of alternating current signal and system for determining zero crossing point of alternating current signal |
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| CN105960060A (en) | 2016-09-21 |
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