(3) invention content:
Electrical device intelligent control system in community service of the present invention, using common electric caldron and electric caldron controller, each electricity boils
The panel of pot controller is equipped with 3 to 5 LED modules with different colors, is first numbered before access system.Appliance controller after rigid booting one
Section the time, sequentially show different colours different number LED combination (such as:It is red, green, blue, red green, bluish-green, red blue, red green
It is blue), each combination is corresponding with the number of number, and when selection shows LED modules with different colors combination, shutdown obtains corresponding number simultaneously
It preserves, it is in the number period when can't detect grid cyclic wave signal, and microcontroller will be numbered by the energy storage of its power capacitor
Data are stored in nonvolatile storage.Many common electric caldrons are arranged on Community Service Center's desktop, are put food and water into, are sticked
After name mark, it can be inserted at any time on the socket of electric caldron controller and choose culinary art pattern and start to endure by preset infusion program
Cook product, then main controller input socket number, start the infusion time, need after informant person's telephone number i.e. beginning oneself
Dynamic infusion.Main controller also passes through RS232 interface and host computer compunlcation.General infusion food begins with 10 minutes or more temperature
Water soak period then has very hot oven, slow fire phase etc., and main controller notifies to service by babyphone programme-controlled exchange at the end of infusion
Member, host computer computer show personnel's name by LED screen.Its power supply of the socket of electric caldron controller passes through bidirectional triode thyristor list
It is solely connected on power network, and after being isolated by photoelectronic coupler by electric caldron controller, the load for controlling bidirectional triode thyristor is powered
Power and time, each electric caldron controller is preset, and there are many operational modes of utility program may be selected, and can use common
Electric caldron makes the processes intelligence such as stew, boil, boil in a covered pot over a slow fire, simmer, endure and boil medicine.Cycle Zhen is respectively mounted in main controller and each electric caldron controller
Other circuit, communications electronics switch and its switch drive module, the synchronization time for generation system keeps system to keep strokes, real
Now power through half wave communication half-wave of power line.Main controller and each electric caldron controller are connected on same electric power cable and are arranged total
Switch, isolating diode is followed by master switch.
Communication is to be controlled by synchronization time to keep each electric caldron controller consistent with main controller communication operation.Each electric caldron
The switch drive module of the communications electronics of controller and main controller switch is depressured again after electric resistance partial pressure from power line through resistance
The ends CLK of d type flip flop, the external interrupt mouth (INT0 or INT1) of the Q termination microcontrollers of d type flip flop are connect, which sets
It is set to level triggers.The ends D of d type flip flop are grounded, and the ends S connect with the I/O of microcontroller mouths, and original state S sets 1 in end.When the ends CLK
Positive square-wave signal arrive when, rising edge makes d type flip flop set to 0, external interrupt mouth low level generate interruption, interrupt service journey
Setting to 0 first the ends S in sequence makes that d type flip flop sets the 1 i.e. ends Q as 1 and the Central Shanxi Plain is disconnected, is then communicated, and communications electronics switch is according to being used
Communication mode is connected to microcontroller corresponding port, and carries out signal condition, and S sets at end 1 and makes out under interrupt latency one week before sign off
Half wave communication is so realized in the communication of wave in cycles.
Infusion is very time-consuming, and waiter can control a part by telephone network has the infusion process of particular/special requirement.Community
A babyphone programme-controlled exchange is installed by service centre, and one of extension number is remotely controlled for infusion.The extension number and refer to
It enables the table of comparisons of code and instruction be stored in mobile phone, the methods of screen-lock password is used in combination to prevent the leakage of data of instruction code.It is logical
When letter, the number of instruction code is sent from base or mobile phone, interchanger is somebody's turn to do after caller dialing by dual-tone multifrequency decoder
After extension set calling telephone number, off-hook is simulated, and keep dual-tone multifrequency reception state, to receive instruction code signal, such as use hand
Machine can be sent out:" exchanging telephone number " P " number of instruction code ", wherein the * keys that " P " can pin mobile phone simulating keyboard obtain,
Type be to press * keys to obtain for 2-3 times, or instruction code is keyed in again after waiting for the voice prompt of interchanger solidification in the chips,
After sign off, interchanger sends the digital signal for receiving instruction code to main controller through interface circuit, is decoded by main controller
After execute corresponding operating.
Cycle discriminator circuit of the present invention as shown in Fig. 2, using power network cycle the positive half cycle ascent stage, take three examination points
It realizes the identification decision to cycle signal, recycles the cycle time to establish synchronization time, main controller and each electricity boil in realization system
The synchronous operation of pot controller.
The cycle identification circuit of main controller and each electric caldron controller is as shown in Fig. 2, by three using hysteresis loop comparator
Voltage comparator forms, and includes filter circuit in each voltage comparator, the reference voltage of voltage comparator is by voltage stabilizing electricity
Road provides.The input circuit of voltage comparator is the both ends for being connected to mains AC power supply respectively by two dropping resistors, decompression
The other end of resistance, parallel connection are connected to diode string, and the number of diode is by maximum in two comparators being arranged in diode string
Input voltage is set to determine, each diode drop is 0.7V, and the input terminal of two comparators is connected to diode string both ends,
Wherein one end is grounded.
Clock timer and synchrotimer is arranged in system.If detect two adjacent cycle signals be it is true,
The clock timer timing time between two adjacent cycle signal zero passages is taken out, cycle time memory cell is sequentially stored in
In, which can store 100 cycle times, and a cycle time is often stored in when being filled with, and first remove most
The cycle time being first stored in, and calculate the average value Tz of the cycle time of deposit and preserve, differentiated using Tz values to be identified
Cycle signal reduces erroneous judgement possibility to reduce the influence of power network frequency fluctuation, while screen point using three.
Three comparators are respectively used to three examination points, that is, screen point 0, screen point 1, screen point 2, as shown in Figure 1.Cycle
The positive half cycle ascent stage accounts for 1/4 period of cycle, the total 5ms times screen at the cycle zero passage of cycle positive half cycle ascent stage
0 setting voltage zero-crossing comparator of point, since power network cycle negative half period is rectified diode-isolated, in order to improve accuracy of detection,
Voltage zero-crossing comparator signal input part again series diode be isolated negative half period, reference voltage from zero be increased to 10mv to
100mv, depending on the offset voltage of comparator, which can be obtained using diode drop through electric resistance partial pressure.Remaining two
A comparator is separately positioned on the cycle positive half cycle ascent stage, the examination point 1 and 50% at 35% to 50% place of crest voltage to
Examination point 2 at 70%.
Cycle signal determining:For microcontroller after setting time opens interruption, clock timer resets and starts timing, works as cycle
When voltage zero-cross, it is arranged in the output voltage overturning for screening the voltage Zero-cross comparator Qi ﹙ V0 ﹚ of point 0, is generated in its voltage failing edge
It interrupts, records its zero crossing break period Th0 and the Central Shanxi Plain is disconnected;Hereafter, electricity pressure comparator ﹙ V1 ﹚ at point 1 are screened in microcontroller scanning
Output voltage, when all wave voltages are reached to the threshold voltage of ﹙ V1 ﹚, output voltage is overturn from high to low, when scanning records its overturning
Between Th1;Same scanning record screens electricity at point 2 and presses comparator ﹙ V2 ﹚ output voltage flip-flop transition Th2, by Th0 and voltage zero-cross
The output voltage flip-flop transition setting value Ts0 of Bi compare Qi ﹙ V0 ﹚ makes comparisons;The output voltage of Th1 and electricity pressure comparator ﹙ V1 ﹚ are overturn
Time setting value Ts1 and Th2 makes comparisons respectively with the output voltage flip-flop transition setting value Ts2 of electricity pressure comparator ﹙ V2 ﹚, such as
For fruit within the scope of allowable error, then the discriminator signal detected is true, is otherwise false.When above-mentioned judgement discriminator signal is true,
Calculate the clock timer meter between cycle signal zero passage when this cycle signal zero passage and an adjacent preceding discriminator signal are true
When time Tzu, it is made comparisons with the average value Tz of cycle time, the cycle if no more than setting cycle time error Tzv
Signal is true, at this moment preserves Tzu and 20ms is taken to be added with synchrotimer timing time, the value deposit synchrotimer that will add up
In.
When clock timer starts timing with cycle voltage zero-cross, then timing to 16ms opens the break period between 18.5ms
Open interruption when setting value Tk, clock timer timing to 25ms is disconnected to Central Shanxi Plain when pass break period setting value Tn between 27ms.
After system boot, clock timer starts timing, and when detecting first cycle voltage zero-cross, setting is being screened
The output voltage overturning of the voltage Zero-cross comparator Qi ﹙ V0 ﹚ of point 0, interrupts to generate, takes out the time T0 of cycle voltage over zero
It preserves, clock timer is reset to and started timing, at this moment cycle time voltage crosses zero Th0 is 0, while microcontroller presses above-mentioned side
Method scans and judges discriminator signal.What it is due to detection is first cycle, and clock timer is started in cycle voltage zero-cross
The value of timing, Th0, Th1 and Th2 must add the difference that cycle time 20ms subtracts out break period setting value Tk, if
Three discriminator signals are true, and i.e. opening the break period for the first time takes Tk next time.Otherwise it is fictitious time, at this time clock timer time palpus
In addition T0, continues to detect.
When detecting first and second adjacent cycle voltage zero-cross, due to not preserving the cycle time of detection,
Therefore the clock timer timing time twice between cycle signal zero passage is made comparisons with cycle time 20ms, judges cycle signal
When being true, then takes out clock timer cumulative time T1=T0+Tk when opening interruption and be stored in synchrotimer as initial time
In, open interruption after clock timer reset, otherwise judge cycle signal be fictitious time, at this time the clock timer time must add T1,
Continue to detect first cycle again as stated above.After it is very to detect first cycle signal, restore above-described week
Wave signal determining.
As shown in Figure 1, if detecting that cycle signal is false, the break period is opened next time and opens the break period at this
Afterwards, open interruptions when average value Tz through the cycle time that is delayed, and open interrupt after be delayed Tns when the Central Shanxi Plain it is disconnected, when the setting Central Shanxi Plain is broken
Between be when cycle signal screen point 0 when do not generate interruption, at this moment must be in the setting time point more than Ts0 allowable error ranges
Start to scan, and when scanning examination point 1 and examination point 2, voltage comparator output voltage does not generate overturning, all breaks in the Central Shanxi Plain
The time Tns Central Shanxi Plain is disconnected and stops scanning, and Tns is:
Tns=Tn-Tk
If detecting that cycle signal is true, next cycle opens break period Tks and is:
Tks=Tk+Th0
I.e. from opening for the first time after the break period takes Tk, clock timer is that timing opens interruption to Tks, and weight after resetting
New to start timing, timing is disconnected to Central Shanxi Plain when Tns, to make the synchrotimer time be corrected by cycle time voltage crosses zero.
It repeats the above process.If the upper cycle signal detected is true, when this cycle judges, discriminator signal is
Vacation, or the cycle time detected is more than setting cycle time error Tzv or clock meter compared with the average value Tz of cycle time
When device timing to close break period setting value Tns when, voltage Zero-cross comparator device ﹙ V0 ﹚ output voltages are not overturn, in not generating
Disconnected, then when clock timer timing is to Tns, the Central Shanxi Plain is disconnected, at this moment remembers that not counting cycle N is 1 and stores, when opening interruption next time
Between be to open the break period in last time to open interruption after Tz, hereafter every time judgement the cycle signal true and false, if false or this detection
Though discriminator signal is true but last time is false, then N is taken, will be restored after N+1 in memory, clock timer is not reset after opening interruption
Continue timing, at this moment, next cycle of setting opens the break period and temporarily uses out break period interim setting value Tkz instead:
Tkz=(N+1) × Tz
Meanwhile next cycle closes break period temporary use instead and closes break period interim setting value Tnz:
Tnz=Tkz+Tns
When clock timer to after Tkz, the time that point is screened in scanning can be obtained by simple computation.If at this moment examined
It is true to measure cycle signal, then takes out N in memory and preserve, and by N zero setting in memory, make clock timer clocking value Ts
For:(Ts-Tkz) at this moment → Ts takes the value of (N+1) × 20ms to be added in synchrotimer, and restore using setting value Tks with
Tns, recovered clock timer are reset after opening interruption.
The system synchronization time is the time of synchrotimer, along with current just in the time of the clock timer of timing.
When the point signal true and false is screened in judgement, Th0, Th1, Th2 are by being set with voltage comparator output voltage flip-flop transition
Definite value Ts0, Ts1, Ts2 make comparisons see it is whether overproof, come judge screen point a signal true and false, can select:Th0, Th1, Th2 are
The cycle discriminator signal is true when true or Th0 is true, while when one of Th1, Th2 are true or when Th1, Th2 are true, should
Cycle discriminator signal is true, depending on requiring judgement cycle signal true and false difference.
If system fault, when N is more than a setting value between 25 to 70, since main controller in system and each electricity boil
Pot controller, the Tz values and N values of detection may be different, and at this moment, power network frequency accumulated error may cause synchrotimer
Time is corrected when can not be by detecting true cycle signal, when it is true to detect cycle signal, using clock timing
Clocking value of the device at Tkz is directly added in synchrotimer, to reduce the asynchronous time of system, power network normal operation feelings
N is much smaller than 25 under condition.
It generates electricity and is carried out at the same time for electric process, the power that generator is sent out, the work(that is consumed with electrical equipment always
Rate keeps balance, when power network frequency drops to certain degree, i.e., carries out frequency modulation by opening the means such as stand-by generator,
Frequency is set to restore rapidly, therefore power network frequency fluctuation is very little under normal circumstances.Installed capacity is 3000MW's or more
System, frequency tolerance are (50 ± 0.2) Hz, installed capacity in 3000MW systems below, frequency tolerance be (50 ±
0.5)Hz.The above method can greatly improve system rejection to disturbance ability.
The cycle time error Tzv of permission and the flip-flop transition setting value of voltage comparator output voltage are using experiment
The week of test data sheet and permission of the software through 100 to 500 voltage comparator output voltages flip-flop transition Th0, Th1 and Th2
Wave time error Tzv test data sheets are assessed respectively takes its average value to obtain.