CN106030786B - 锚固的互连件 - Google Patents
锚固的互连件 Download PDFInfo
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- CN106030786B CN106030786B CN201480076362.7A CN201480076362A CN106030786B CN 106030786 B CN106030786 B CN 106030786B CN 201480076362 A CN201480076362 A CN 201480076362A CN 106030786 B CN106030786 B CN 106030786B
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- layer
- via hole
- metal layer
- nitride
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
实施例包括一种半导体结构,包括:后端部分,该后端部分包括位于底部金属层与顶部金属层之间的多个金属层;顶部金属层包括具有第一侧壁表面和第二侧壁表面以及使侧壁表面彼此耦合的顶部表面的顶部金属层部分,其中,第一侧壁表面与第二侧壁表面相对;绝缘体层,该绝缘体层直接接触顶部表面;以及过孔,该过孔将接触凸块耦合至顶部金属层部分;其中,与耦合至后端部分的衬底正交的第一垂直轴与接触凸块、氮化物层、过孔、和顶部金属层部分相交。本文中描述了其它实施例。
Description
技术领域
本发明的实施例属于半导体器件的领域,并且具体而言,属于互连件的领域。
背景技术
传统上,半导体芯片已经经由引线互连件电耦合至衬底上的电迹线,该引线互连件在一端被焊接至芯片的顶部有源区并且在另一端被焊接至衬底上的围绕芯片的迹线焊盘。这些类型的互连件并非特别有效,对于芯片的表面区域和用于迹线焊盘的周边区域两者都需要空间,导致较大的芯片封装体。为了更有效地利用衬底表面并有助于较小的芯片封装体,开发了倒装芯片互联工艺。实质上,半导体芯片的有源表面被倒装过来以面对衬底,并且芯片被直接焊接至位于有源表面邻近处的迹线焊盘。结果是更紧凑的和空间有效的封装体。
电连接倒装芯片的最成功和有效的方法中的一种方法利用可控塌陷芯片连接技术(C4)。首先,焊料凸块被施加到芯片、衬底或两者的有源侧上的焊盘。接下来,焊料凸块被融化并被允许流动,确保凸块对于芯片或衬底上的对应焊盘是完全湿的。粘性焊剂通常被施加到待连接的表面中的一个表面或两者。芯片和衬底的焊剂承载表面随后被放置为在总体对齐的情况下彼此接触。通过将芯片和衬底封装体加热至或高于焊料的熔点来执行回流。芯片和衬底上的焊料进行组合并且融化的焊料的表面张力使得对应的焊盘彼此自对准。经连接的封装体随后被冷却以使焊料固化。基于融化的焊料柱的表面张力与芯片的重量之间的平衡来确定焊料互连件的得到的高度。在去焊剂操作中从芯片和衬底组合中去除任何焊剂和焊剂残余物。最后,在芯片的底部表面与衬底的顶部表面之间、围绕并支撑焊料柱来施加环氧树脂底部填充剂。芯片衬底焊料连接的可靠性和抗疲劳性显著增加。底部填充剂用于承载由芯片与衬底之间的热膨胀系数(CTE)差异所引起的大部分热负载,而不是使所有的热负载通过焊料柱被转移。
附图说明
根据所附权利要求、一个或多个示例性实施例的以下具体实施方式、和对应的附图,本发明的实施例的特征和优点将变得显而易见,在附图中:
图1a描绘了传统的顶部金属层的分层(delamination),并且图1b描绘了在本发明的实施例中的顶部金属层的分层的显著降低。
图2a包括本发明的实施例中的锚固的(anchored)互连件。图2b包括图2a中的实施例的放大视图。
图3a-图3e包括形成本发明的实施例中的锚固的实施例的方法。
图4包括形成本发明的实施例中的锚固的实施例的方法。
具体实施方式
现在将参照附图,其中,类似的结构可以被提供有类似的附图标记。为了更清楚地示出各实施例的结构,本文中包括的附图是对半导体/电路结构的图形表示。因此,例如在显微照片中所制造的集成电路结构的实际外观可能有所不同,而依然包含所例示的实施例的请求保护的结构。此外,附图可能仅示出了对于理解所例示的实施例有用的结构。可能并未包括本领域公知的另外的结构,以保持附图的清楚性。例如,并非必须示出半导体器件的每一层。“实施例”、“各实施例”等等指示如此描述的一个或多个实施例可以包括特定的特征、结构、或特性,但并非每个实施例都必须包括该特定的特征、结构、或特性。某些实施例可具有针对其它实施例所描述的某些特征、全部特征、或不具有这些特征。“第一”、“第二”、“第三”等等描述共同的对象,并且指示正指代类似对象的不同实例。这些形容词并非暗示如此描述的对象必须以给定的顺序,不管是时间上的顺序、空间上的顺序、排序上的顺序、还是以任何其它方式的顺序。“连接”可以指示元件彼此直接物理接触或电接触,并且“耦合”可以指示元件彼此协作或交互,但是它们可以直接物理接触或电接触,或者可以不直接物理接触或电接触。
在以上“背景技术”部分中,总体上讨论了将焊料凸块添加至焊盘。现在更详细地讨论将焊料凸块添加至焊盘,并努力设置围绕这些部件的耦合的背景。
具体而言,将焊料凸块添加至焊盘发生在“后段工艺”接近结束时。更具体而言,一旦已经构建了半导体器件(例如,包括晶体管或其它开关器件的器件的部分),则其必须进行互连以形成期望的电路。该“后段工艺”涉及以期望的模式来沉积各金属层和绝缘材料。通常,金属层由铝、铜、等等组成。绝缘材料可以包括SiO2、低K材料、等等。各金属层通过互连件进行互连,互连件可以包括线部分和过孔部分。过孔可以通过在绝缘材料中形成蚀刻孔并在孔中沉积金属(例如,钨)来形成。线部分可以通过在绝缘材料中蚀刻沟槽并在沟槽中沉积金属来形成。该工艺的最后部分可以包括前面提及的将焊料凸块耦合至焊盘。焊盘可以包括在金属层中的一个金属层中或者耦合至金属层中的一个金属层。
一旦已经完成后段工艺,则半导体器件经受各种后段工艺(End-of-Line)电测试以判断其是否正常运行。随着工艺和对应的测试技术发展,后段工艺可靠性要求(例如,热应力b-HAST测试)变得越来越严格。首字母缩略词“HAST”表示“Highly acceleratedtemperature/Humidity Stress Test(高加速温度/湿度应力测试)”。该测试发展成为对温度湿度偏置(THB)测试的较短时的替代。如果THB测试花费1000小时来完成,则HAST结果在96-100小时内可用。因此,HAST的普及程度在近些年来已经持续增加。
申请人已经认识到关于在后段工艺测试期间发现的分层的担心。例如,发生厚过孔9的分层,这导致b-HAST测试失败。“过孔9”指代在第九个金属层(例如,金属9层)中形成的过孔。
本发明的实施例解决了在半导体器件的最上部的金属层中(或在多个最上部的金属层之中)发生的这种分层。实施例包括金属锚固件,其位于最高的金属层中的过孔下方,以便在过量应力被置于过孔(或构件,例如连接至过孔的焊球)上、污染物削弱过孔、等等的情况下保持过孔稳定。实施例包括金属9锚固件(位于金属9(M9)层中的锚固件),其位于过孔9(耦合至M9层的过孔,举例来说,例如,位于M9层的顶部上)下方,以便在过量应力被置于过孔(或构件,例如连接至过孔的焊球)上、污染削弱过孔、等等的情况下支撑过孔9。实施例可以包括用于将逻辑单元互连至存储器(LMI)管芯的金属再分布层中的穿硅过孔(TSV)(例如,蚀刻穿过晶圆以允许与3D晶圆级封装兼容的晶圆至晶圆互连方案的过孔)的锚固件。
现在讨论一系列附图以例示先前提及的概念和实施例中的某些概念和实施例。
图1a描绘了传统的顶部金属层的分层。存在比它们的周围更为明亮(lighter)的许多位置。这些更为明亮的区域存在于由于应力被置于分层的区域附近的一个或多个接触凸块上而已经发生顶部金属层的分层的地方。图1b描绘了在本发明的实施例中的顶部金属层的分层的显著下降。接下来阐述与引起下降的顶部层的分层的实施例有关的细节。
图2a包括本发明的实施例中的经锚固的互连件。图2b包括图2a中的实施例的放大视图。
半导体结构200可以包括出于清楚的目的而未示出的若干元件。例如,结构200可以包括具有位于衬底上的器件层的前端部分。器件层可以包括晶体管、开关器件、等等。结构200还可以包括具有底部金属层和位于底部金属层的顶部上的多个金属层的后端部分。如本领域技术人员将意识到的,后端部分在底部金属层与前端部分的顶部之间不包括金属层。此外,后端部分在顶部金属层与后端部分的顶部之间不包括金属层。
图2a和图2b示出了顶部金属层(其位于上面提及的多个金属层上),其包括具有第一和第二相对的侧壁表面206、207以及使侧壁表面彼此耦合的顶部表面(包括部分208、209)的顶部金属层部分205。
结构200还包括氮化物层210,其在第一位置(例如,位置211)处直接接触与第一侧壁表面直接相邻的顶部表面、并在第二位置(例如,位置212)处直接接触与第二侧壁表面直接相邻的顶部表面。
结构200还包括接触凸块220和将接触凸块220耦合至顶部金属层部分205的过孔215。要指出的是,由于放大图2b并未示出凸块220,取而代之示出了过孔215的在该过孔接触凸块之前的部分(如在图2a中所示出的)。
在实施例中,过孔215在第一位置211和第二位置212两者处直接接触位于氮化物层210正下方的顶部金属层部分205。如本领域技术人员将意识到的,过孔包括在层间电介质(例如,电介质225(例如,SiO2和/或Si3N4))中蚀刻的孔,其随后被填充有金属(例如,钨),以便在诸如顶部金属层205与接触凸块220之类的金属部分之间提供连接。在实施例中,顶部金属层部分205包括互连线、接触焊盘、等等中的任何一个。
在实施例中,过孔215沿着从第一位置211延伸到第二位置212的曲线230与部分205的顶部表面直接接合。因此,传统的过孔可以被认为被限于线235、236之间的空间,其中,线互连件从线236向下延伸。然而,在实施例中,过孔215延伸到线236下方并延伸到区域231(通常与互连线相关联的区域)中。这是因为在形成过孔215之前去除(例如,使用在图3中更充分描述的蚀刻步骤)金属层205的部分。在实施例中,曲线230“大体上呈抛物线状”,也就是说,线并非必须是完美地平滑的。大体上的抛物线230具有位于过孔215和接触凸块220正下方并位于第一位置211和第二位置212与衬底(未示出)之间的抛物线顶点(即,其中抛物线跨过其对称轴的点)。在图2a中,顶点大约位于线230的最底部部分处。显著地,线230不仅是用于例示的线(例如,线235,236)。线230描绘了存在于过孔215与顶部金属层部分205之间的实际物理界面。
线230例示了过孔215实际上是如何在氮化物210的部分下方延伸从而形成具有底切区域219、211的“互连锚固件”的。在实施例中,用距离250、251例示出过孔215底切氮化物210的量。距离250、251可以相等或可以不相等。在实施例中,距离250为1.0微米,但是在其它实施例中,其可以是0.3、0.4、0.5、0.6、0.7、0.8、0.9、1.1、1.2、1.3、1.4、1.5、1.6微米或更大。在实施例中,距离251为0.6微米,但是在其它实施例中,其可以是0.3、0.4、0.5、0.7、0.8、0.9、1.0、1.1、1.2、1.3、1.4、1.5、1.6微米或更大。
各个轴有助于例示某些实施例的特性。例如,第一垂直轴240(与在其上形成金属层205和其它下层金属层的衬底(未示出)正交)与接触凸块220、氮化物层210、过孔215、和顶部金属层部分205相交。这个轴可以不必接触电介质225。这对于轴241也一样。在实施例中,与衬底正交的第二垂直轴242与接触凸块220、氮化物层210、电介质225、和顶部表面208相交。尽管未示出,与衬底正交的另一个垂直轴将与接触凸块220、氮化物层210、电介质225、和顶部表面209相交。在实施例中,与第一垂直轴240正交的水平轴243与氮化物层210、第一侧壁表面206和第二侧壁表面207、以及过孔215相交。例如,轴243在区域231中与过孔215相交。因此,在实施例中,轴243与过孔215和顶部金属层部分205两者相交。
图3a-图3e包括用于形成本发明的实施例中的锚固的实施例的方法。在框365中,在电介质325内并在顶部金属层(例如,M9层)部分305的顶部上形成间隔体313。氮化物层310位于电介质325与金属部分305之间。金属部分305位于另一个层311的顶部上。层311可以是各种类型的层中的任何层,例如电介质层等等。层311可以形成在许多其它层(未示出,例如后端的多个金属和电介质层,其可以形成在前端的器件层和衬底上)的顶部上。
在框370中,光致抗蚀剂(PR)312被施加在电介质325上方并被施加至间隔体313中以及在框370中示出的左边或右边的器件的其它部分上。在框375中,去除了间隔体313中的该PR,但在器件的不需要经受随后的步骤中的蚀刻工艺的其它部分上保留该PR。在框380中,发生先前提及的蚀刻步骤,以便在氮化物310和电介质325下方构建底切区域319、321。在框385中,金属填充经蚀刻的空间以形成包括过孔315的锚固互连件。在实施例中,该工艺可用于通过将晶圆浸入湿法蚀刻工具组中来形成“金属9”(第9层金属层)锚固件或足部(例如,框380)。该锚固件或足部随后用来在过孔9已经被图案化并且电介质325已经被固化之后支承“过孔9”(耦合至第9金属层的过孔)。
电介质325可以包括光可限定的低收缩聚合物,其通常在固化(例如,在250摄氏度下热固化一个小时)期间具有大约百分之十五或更少的收缩。适于低收缩光可限定的聚合物的描述的聚合物为:以商标名称WPR(包括WPR-1020、WPR-1050、和WPR-1201)的可商购的聚(羟基苯乙烯)和酚醛清漆树脂。(WPR是日本东京的JSR公司的注册商标)。
图4包括用于形成本发明的实施例中的锚固的实施例的方法400。框405包括在衬底上形成前端部分,包括器件层。框410包括在前端部分上形成多个金属层。框415包括在多个金属层上形成顶部金属层;顶部金属层包括顶部金属层部分,其具有第一侧壁表面和第二侧壁表面以及使侧壁表面彼此耦合的顶部表面,其中,第一侧壁表面与第二侧壁表面相对。框420包括在顶部表面上形成氮化物层。框425包括在顶部金属层部分的顶部上形成过孔。框430包括在过孔上形成接触凸块。工艺产生了其中与衬底正交的第一垂直轴与接触凸块、氮化物层、过孔、和顶部金属层部分相交的器件。
各个实施例包括半导体衬底。这种衬底可以是体半导体材料,其是晶圆的部分。在实施例中,半导体衬底是作为已经从晶圆单颗化的芯片的部分的体半导体材料。在实施例中,半导体衬底是形成在诸如绝缘体上半导体(SOI)衬底之类的绝缘体上方的半导体材料。在实施例中,半导体衬底是诸如在体半导体材料上方延伸的鳍部之类的突出结构。
以下示例涉及其它实施例。
示例1包括A半导体结构,包括:前端部分,该前端部分包括位于衬底上的器件层;后端部分,该后端部分包括底部金属层、顶部金属层、和位于底部金属层与顶部金属层之间的多个金属层;该顶部金属层包括具有第一侧壁表面和第二侧壁表面以及使侧壁表面彼此耦合的顶部表面的顶部金属层部分,其中,第一侧壁表面与第二侧壁表面相对;氮化物层,该氮化物层在第一位置处直接接触与第一侧壁表面直接相邻的顶部表面,并在第二位置处直接接触与第二侧壁表面直接相邻的顶部表面;以及接触凸块和将接触凸块耦合至顶部金属层部分的过孔;其中,(a)后端部分在底部金属层与前端部分的顶部之间不包括金属层;(b)后端部分在顶部金属层与后端部分的顶部之间不包括金属层;并且(c)过孔在第一位置和第二位置两者处直接接触位于氮化物层正下方的顶部金属层部分。
在实施例中,顶部金属层部分包括铜,但是在其它实施例中,可以包括钨和/或铝或其它导体。在实施例中,过孔可以包括铜和/或铝,但是在其它实施例中,可以包括钨或其它导体。在实施例中,接触凸块包括铜,但在其它实施例中,可以包括钨、铝、铅、和/或锡或其它导体。
在示例2中,示例1的主题可以可选地包括:其中,过孔沿着从第一位置延伸到第二位置的曲线与顶部表面直接接合。
在示例3中,示例1-2的主题可以可选地包括:其中,顶部金属层部分包括互连线。
在示例4中,示例1-3的主题可以可选地包括:其中,该曲线大体上呈抛物线状,该曲线具有位于过孔和接触凸块正下方并位于第一位置和第二位置与衬底之间的抛物线顶点。
在示例5中,示例1-4的主题可以可选地包括:其中,与衬底正交的第一垂直轴与接触凸块、氮化物层、过孔、和顶部金属层部分相交。
在示例6中,示例1-5的主题可以可选地包括:其中,与衬底正交的第二垂直轴与接触凸块、氮化物层、电介质、和顶部表面相交。
在示例7中,示例1-6的主题可以可选地包括:其中,与第一垂直轴正交的水平轴与氮化物层、第一侧壁表面和第二侧壁表面、以及过孔相交。
示例8包括半导体结构,其包括:后端部分,该后端部分包括位于底部金属层与顶部金属层之间的多个金属层;该顶部金属层包括具有第一侧壁表面和第二侧壁表面和使侧壁表面彼此耦合的顶部表面的顶部金属层部分,其中,第一侧壁表面与第二侧壁表面相对;绝缘体层,该绝缘体层直接接触顶部表面;以及过孔,该过孔将接触凸块耦合至顶部金属层部分;其中,与耦合至后端部分的衬底正交的第一垂直轴与接触凸块、氮化物层、过孔、以及顶部金属层部分相交。
在示例9中,示例8的主题可以可选地包括:其中,过孔在第一位置和第二位置处直接接触位于氮化物层正下方的顶部金属层部分。
在示例10中,示例8-9的主题可以可选地包括:其中,过孔沿着从第一位置延伸到第二位置的曲线与顶部表面直接接合。
在示例11中,示例8-10的主题可以可选地包括:其中,该曲线大体上呈抛物线状,该曲线具有位于过孔和接触凸块正下方并位于第一位置和第二位置与衬底之间的抛物线顶点。
在示例12中,示例8-11的主题可以可选地包括:其中,顶部金属层部分包括互连线。
在示例13中,示例8-12的主题可以可选地包括:其中,与衬底正交的第二垂直轴与接触凸块、氮化物层、电介质、和顶部表面相交。
在示例14中,示例8-13的主题可以可选地包括:其中,与第一垂直轴正交的水平轴与氮化物层、第一侧壁表面和第二侧壁表面、以及过孔相交。
在示例15中,示例8-14的主题可以可选地包括:其中,与第一垂直轴正交的水平轴与氮化物层、第一侧壁表面和第二侧壁表面、以及过孔相交。
在示例16中,示例8-15的主题可以可选地包括:其中,绝缘体包括氮化物。例如,氮化硅可以被用作为绝缘体和化学阻挡/钝化层。其它绝缘体可以包括(SiNxHy)、二氧化硅、等等。
示例17包括一种方法,包括:在衬底上形成前端部分,该前端部分包括器件层;在前端部分上形成多个金属层;在多个金属层上形成顶部金属层;顶部金属层包括具有第一侧壁表面和第二侧壁表面以及使侧壁表面彼此耦合的顶部表面的顶部金属层部分,其中,第一侧壁表面与第二侧壁表面相对;在顶部表面上形成氮化物层;在顶部金属层部分的顶部上形成过孔;在过孔上形成接触凸块;其中,与衬底正交的第一垂直轴与接触凸块、氮化物层、过孔、以及顶部金属层部分相交。
在示例18中,示例17的主题可以可选地包括:其中,过孔在第一位置和第二位置处直接接触位于氮化物层正下方的顶部金属层部分。
在示例19中,示例17-18的主题可以可选地包括:其中,过孔沿着从第一位置延伸到第二位置的曲线与顶部表面直接接合。
在示例20中,示例17-19的主题可以可选地包括:其中,曲线大体上呈抛物线状,该曲线具有位于过孔和接触凸块正下方并位于第一位置和第二位置与衬底之间的抛物线顶点。
在示例21中,示例17-20的主题可以可选地包括:其中,顶部金属层部分包括互连线。
在示例22中,示例17-21的主题可以可选地包括:其中,与衬底正交的第二垂直轴与接触凸块、氮化物层、电介质、以及顶部表面相交。
在示例23中,示例17-22的主题可以可选地包括:其中,与第一垂直轴正交的水平轴与氮化物层、第一侧壁表面和第二侧壁表面、以及过孔相交。
在示例24中,示例17-23的主题可以可选地包括:其中,与第一垂直轴正交的水平轴与氮化物层、第一侧壁表面和第二侧壁表面、以及过孔相交。
出于例示和描述的目的,已经呈现了对本发明的实施例的前述描述。其并非旨在是详尽的或者将本发明限于所公开的精确形式。本描述和所附权利要求包括术语,例如左、右、顶部、底部、上方、下方、上部、下部、第一、第二、等等,这些术语仅用于描述性的目的而并非被解释为限制。例如,标示相对垂直位置的术语指代其中衬底或集成电路的器件侧(或有源表面)是该衬底的“顶部”表面的情形;该衬底实际上可以以任何取向,以使得在标准的地球参考系中,衬底的“顶部”侧可能低于“底部”侧,并且仍然落入术语“顶部”的含义内。除非明确指出,否则如本文中(包括在权利要求书中)使用的术语“在……上”并非指示“位于”第二层“上”的第一层直接位于第二层上并且与第二层直接接触;在第一层与第一层上的第二层之间可以存在第三层或其它结构。本文中所描述的器件或项的实施例可以在多个位置和方位中被制造、使用、或运输。本领域技术人员可以意识到,鉴于以上教导,许多修改和变型是可能的。本领域技术人员将认识到对于附图中示出的各部件的各种等同的组合和替代。因此,旨在本发明的范围并非由本具体实施方式来限定,而是由所附权利要求来限定。
Claims (23)
1.一种半导体结构,包括:
前端部分,所述前端部分包括位于衬底上的器件层;
后端部分,所述后端部分包括底部金属层、顶部金属层、以及位于所述底部金属层与所述顶部金属层之间的多个金属层;所述顶部金属层包括具有第一侧壁表面和第二侧壁表面以及使所述侧壁表面彼此耦合的顶部表面的顶部金属层部分,其中,所述第一侧壁表面与所述第二侧壁表面相对;
氮化物层,所述氮化物层在第一位置处直接接触与所述第一侧壁表面直接相邻的所述顶部表面,并在第二位置处直接接触与所述第二侧壁表面直接相邻的所述顶部表面;
所述氮化物层上的电介质层,所述电介质层包括在固化期间具有百分之十五或更少的收缩的低收缩聚合物;以及
接触凸块和将所述接触凸块耦合至所述顶部金属层部分的过孔;
其中,(a)所述后端部分在所述底部金属层与所述前端部分的顶部之间不包括金属层;(b)所述后端部分在所述顶部金属层与所述后端部分的顶部之间不包括金属层;并且(c)所述过孔在所述第一位置和所述第二位置两者处直接接触位于所述氮化物层正下方的所述顶部金属层部分。
2.根据权利要求1所述的结构,其中,所述过孔沿着从所述第一位置延伸到所述第二位置的曲线与所述顶部表面直接接合。
3.根据权利要求2所述的结构,其中,所述顶部金属层部分包括互连线。
4.根据权利要求2所述的结构,其中,所述曲线大体上呈抛物线状,所述曲线具有位于所述过孔和所述接触凸块正下方并位于所述第一位置和所述第二位置与所述衬底之间的抛物线顶点。
5.根据权利要求1所述的结构,其中,与所述衬底正交的第一垂直轴与所述接触凸块、所述氮化物层、所述过孔、和所述顶部金属层部分相交。
6.根据权利要求5所述的结构,其中,与所述衬底正交的第二垂直轴与所述接触凸块、所述氮化物层、所述电介质层、和所述顶部表面相交。
7.根据权利要求6所述的结构,其中,与所述第一垂直轴正交的水平轴与所述氮化物层、所述第一侧壁表面和所述第二侧壁表面、以及所述过孔相交。
8.一种半导体结构,包括:
后端部分,所述后端部分包括位于底部金属层与顶部金属层之间的多个金属层;所述顶部金属层包括具有第一侧壁表面和第二侧壁表面以及使所述侧壁表面彼此耦合的顶部表面的顶部金属层部分,其中,所述第一侧壁表面与所述第二侧壁表面相对;
氮化物层,所述氮化物层直接接触所述顶部表面;
所述氮化物层上的电介质层,所述电介质层包括在固化期间具有百分之十五或更少的收缩的低收缩聚合物;以及
过孔,所述过孔将接触凸块耦合至所述顶部金属层部分;
其中,与耦合至所述后端部分的衬底正交的第一垂直轴与所述接触凸块、所述氮化物层、所述过孔、以及所述顶部金属层部分相交。
9.根据权利要求8所述的结构,其中,所述氮化物层在第一位置处直接接触与所述第一侧壁表面直接相邻的所述顶部表面,并在第二位置处直接接触与所述第二侧壁表面直接相邻的所述顶部表面,所述过孔在所述第一位置和所述第二位置处直接接触位于所述氮化物层正下方的所述顶部金属层部分。
10.根据权利要求9所述的结构,其中,所述过孔沿着从所述第一位置延伸到所述第二位置的曲线与所述顶部表面直接接合。
11.根据权利要求10所述的结构,其中,所述曲线大体上呈抛物线状,所述曲线具有位于所述过孔和所述接触凸块正下方并位于所述第一位置和所述第二位置与所述衬底之间的抛物线顶点。
12.根据权利要求8所述的结构,其中,所述顶部金属层部分包括互连线。
13.根据权利要求8所述的结构,其中,与所述衬底正交的第二垂直轴与所述接触凸块、所述氮化物层、所述电介质层、和所述顶部表面相交。
14.根据权利要求13所述的结构,其中,与所述第一垂直轴正交的水平轴与所述氮化物层、所述第一侧壁表面和所述第二侧壁表面、以及所述过孔相交。
15.根据权利要求8所述的结构,其中,与所述第一垂直轴正交的水平轴与所述氮化物层、所述第一侧壁表面和所述第二侧壁表面、以及所述过孔相交。
16.一种制造半导体结构的方法,包括:
在衬底上形成前端部分,所述前端部分包括器件层;
在所述前端部分上形成多个金属层;
在所述多个金属层上形成顶部金属层;所述顶部金属层包括具有第一侧壁表面和第二侧壁表面以及使所述侧壁表面彼此耦合的顶部表面的顶部金属层部分,其中,所述第一侧壁表面与所述第二侧壁表面相对;
在所述顶部表面上形成氮化物层;
在所述氮化物层上形成电介质层,所述电介质层包括在固化期间具有百分之十五或更少的收缩的低收缩聚合物;以及
在所述顶部金属层部分的顶部上形成过孔;
在所述过孔上形成接触凸块;
其中,与所述衬底正交的第一垂直轴与所述接触凸块、所述氮化物层、所述过孔、以及所述顶部金属层部分相交。
17.根据权利要求16所述的方法,其中,所述氮化物层在第一位置处直接接触与所述第一侧壁表面直接相邻的所述顶部表面,并在第二位置处直接接触与所述第二侧壁表面直接相邻的所述顶部表面,所述过孔在所述第一位置和所述第二位置处直接接触位于所述氮化物层正下方的所述顶部金属层部分。
18.根据权利要求17所述的方法,其中,所述过孔沿着从所述第一位置延伸到所述第二位置的曲线与所述顶部表面直接接合。
19.根据权利要求18所述的方法,其中,所述曲线大体上呈抛物线状,所述曲线具有位于所述过孔和所述接触凸块正下方并位于所述第一位置和所述第二位置与所述衬底之间的抛物线顶点。
20.根据权利要求16所述的方法,其中,所述顶部金属层部分包括互连线。
21.根据权利要求16所述的方法,其中,与所述衬底正交的第二垂直轴与所述接触凸块、所述氮化物层、所述电介质层、以及所述顶部表面相交。
22.根据权利要求16所述的方法,其中,与所述第一垂直轴正交的水平轴与所述氮化物层、所述第一侧壁表面和所述第二侧壁表面、以及所述过孔相交。
23.根据权利要求22所述的方法,其中,与所述第一垂直轴正交的水平轴与所述氮化物层、所述第一侧壁表面和所述第二侧壁表面、以及所述过孔相交。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1989604A (zh) * | 2004-07-29 | 2007-06-27 | 京瓷株式会社 | 功能元件及其制造方法、以及功能元件装配结构体 |
CN102723317A (zh) * | 2011-03-28 | 2012-10-10 | 飞兆半导体公司 | 芯片尺寸封装内的可靠焊料块耦合 |
CN103378049A (zh) * | 2012-04-16 | 2013-10-30 | 台湾积体电路制造股份有限公司 | 用于ic封装的应力减小结构 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
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US6632704B2 (en) | 2000-12-19 | 2003-10-14 | Intel Corporation | Molded flip chip package |
JP2002231748A (ja) * | 2001-02-01 | 2002-08-16 | Sanyo Electric Co Ltd | バンプ電極の形成方法 |
US6853076B2 (en) * | 2001-09-21 | 2005-02-08 | Intel Corporation | Copper-containing C4 ball-limiting metallurgy stack for enhanced reliability of packaged structures and method of making same |
JP2004304151A (ja) * | 2003-03-20 | 2004-10-28 | Seiko Epson Corp | 半導体ウエハ、半導体装置及びその製造方法、回路基板並びに電子機器 |
KR100691151B1 (ko) * | 2005-02-24 | 2007-03-09 | 삼성전기주식회사 | 솔더범프 앵커시스템 |
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JP2008016514A (ja) * | 2006-07-03 | 2008-01-24 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
US8309856B2 (en) | 2007-11-06 | 2012-11-13 | Ibiden Co., Ltd. | Circuit board and manufacturing method thereof |
DE102009035437B4 (de) * | 2009-07-31 | 2012-09-27 | Globalfoundries Dresden Module One Llc & Co. Kg | Halbleiterbauelement mit einem Verspannungspuffermaterial, das über einem Metallisierungssystem mit kleinem ε gebildet ist |
JP2012059738A (ja) * | 2010-09-03 | 2012-03-22 | Toshiba Corp | 半導体装置 |
US8853072B2 (en) * | 2011-06-06 | 2014-10-07 | Micron Technology, Inc. | Methods of forming through-substrate interconnects |
US9343411B2 (en) * | 2013-01-29 | 2016-05-17 | Intel Corporation | Techniques for enhancing fracture resistance of interconnects |
US9478509B2 (en) * | 2014-03-06 | 2016-10-25 | GlobalFoundries, Inc. | Mechanically anchored backside C4 pad |
-
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CN102723317A (zh) * | 2011-03-28 | 2012-10-10 | 飞兆半导体公司 | 芯片尺寸封装内的可靠焊料块耦合 |
CN103378049A (zh) * | 2012-04-16 | 2013-10-30 | 台湾积体电路制造股份有限公司 | 用于ic封装的应力减小结构 |
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