TWI604587B - 穿矽孔堆疊結構暨其製作方法 - Google Patents

穿矽孔堆疊結構暨其製作方法 Download PDF

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TWI604587B
TWI604587B TW101147253A TW101147253A TWI604587B TW I604587 B TWI604587 B TW I604587B TW 101147253 A TW101147253 A TW 101147253A TW 101147253 A TW101147253 A TW 101147253A TW I604587 B TWI604587 B TW I604587B
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林柏均
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南亞科技股份有限公司
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Description

穿矽孔堆疊結構暨其製作方法
本發明大體上與一種半導體技術有關，更具體言之，其係關於一種漸縮式的穿矽孔(through silicon via,TSV)堆疊結構暨其製作方法。
就習知的半導體晶片而言，積體電路會形成在具有電性終端(如一接墊結構)的半導體晶片或基底的主動面上。為了達成高密度的電互連結構，業界中開發出了立體式的晶片堆疊結構(3D chip)，其電性終端不僅會設在半導體晶片的主動面上，也會設在對應的晶背上。在這樣的立體堆疊結構中，穿矽孔(through silicon via,TSV)就是用來連接數個垂直堆疊的晶片或晶圓的結構，以使其組裝成具有高功率、高密度、以及微縮尺寸的立體晶片堆疊封裝結構/模組或是晶圓接合結構。穿矽孔結構，顧名思義，就是一種穿過晶片內部的導電性貫孔結構，其會貫通晶片的底面與底面，其不需使用任何的介板(interposer)或接線(bonding wire)即可形成多層垂直電性連結，也不會經過晶片邊緣的側壁部位，故可以大幅縮短電路徑。穿矽孔結構亦能進一步地藉由大幅減少封裝結構的高度與尺寸之方式來增強電子裝置的積集度與效能，進而 增加電子裝置的速度並減少其能耗。
為了連接彼此堆疊的晶片，晶片上的穿矽孔結構需要加以對齊。然而，隨著半導體業界中電路尺寸微縮的趨勢，穿矽孔結構的大小亦變得越來越小。因此，要將晶片或基底上的每個穿矽孔與另一晶片或基底上對應的穿矽孔準確地對準變得越為困難。
在美國專利公告號第6,908,785號揭露了一種具有穿矽孔結構的半導體晶片。在此結構中，每個半導體晶片都具有複數個貫通的穿矽孔。這些穿矽孔的周圍設置有導電性的金屬材質連結半導體晶片上下兩面的電性終端或電路。在此發明中，上述週壁設置有導體金屬的穿矽孔即為其穿矽孔結構。此發明的特徵在於其載體上會預先設有複數個導電針腳來作為垂直堆疊的半導體晶片的電互連結構。然而，為了要將所有的半導體晶片電性連接到載體上，上述所有的導電針腳都必須筆直凸出，不能有任何彎曲、變形或移位的情形，且還須對準所有對應的貫孔並插入其中才能達到連結的效果。只要其堆疊期間任一半導體晶片中有一個導電針腳有彎曲、變形、或移位的情形，導電針腳就無法輕易地插入所對應半導體晶片上的貫孔中。故這樣的作法容易發生上述對位以及產品良率差的問題。
美國專利公告號第7,838,967號中揭露了一種具有穿矽孔結構的半導體晶片，其晶片上具有複數個接墊分別設置在基底的上下兩面，並具有貫孔穿過其中。此發明的特點在於 其每個接墊上具有凸起的環狀體。這些環狀體有兩種大小，可彼此對合。在疊合的過程中，接墊上較小的環狀體會嵌入環設在另一基底上所對應較大的環狀體之中。以此方式，半導體晶片將可精準地對位並彼此堆疊。然而，使用上述從接墊凸出的環狀體之方式來達成晶片連結，不可避免地，會增加整體堆疊結構的高度。此外，在實際的堆疊實作中，要將所有凸起的環狀體準確地嵌入環徑尺寸恰好對合的另一環形結構中其實是非常困難的工序。
故此，目前業界仍需要就現有的穿矽孔結構進行改良，以期使堆疊晶片或基底間的穿矽孔結構的精確對位暨結合工序更為簡便易行，並能同時改善其間的接合品質。
為了改進上述先前技術作法之缺失，本發明提出了一種新穎的穿矽孔堆疊結構暨其製作方法。本發明的特點在於漸縮式的穿矽孔設計，其較粗端具有凹部來於對應凸出的較細端連結。
本發明的目的之一在於提出一種由多個基底疊合而成的穿矽孔堆疊結構，其每個基底都會含有至少一個漸縮式的穿矽孔貫穿其中。其中，漸縮式穿矽孔的較粗端會具有一凹部從基底面裸露出來，而較細端則從基底的另一面凸出。基底會採行將穿矽孔的較細端裝入另一穿矽孔較粗端對應的凹部 中之方式來逐一疊合並接合。
本發明的另一目的在於提出一種穿矽孔堆疊結構的製作方法，其步驟包含提供複數個基底、在每一基底的表面上形成至少一個漸縮式穿矽孔、在每個漸縮式穿矽孔中填滿導電性材質以形成穿矽孔結構、在每個漸縮式穿矽孔結構的較粗端上形成凹部、移除部分的基底直到穿矽孔的較細端從基底的另一面凸出、以及將基底以穿矽孔的較細端裝入另一穿矽孔較粗端對應的凹部中之方式來逐一疊合並接合。
無疑地，本發明的這類目的與其他目的在閱者讀過下文以多種圖示與繪圖來描述的較佳實施例細節說明後將變得更為顯見。
在下文的細節描述中，元件符號會標示在隨附的圖示中成為其中的一部份，並且以可實行該實施例之特例描述方式來表示。這類實施例會說明足夠的細節俾使該領域之一般技藝人士得以具以實施。閱者須瞭解到本發明中亦可利用其他的實施例或是在不悖離所述實施例的前提下作出結構性、邏輯性、及電性上的改變。因此，下文之細節描述將不欲被視為是一種限定，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
現在下文中將提供多個實施例搭配圖示來說明本發明之 製程，以讓閱者能更瞭解本發明。本發明的標的物，亦即穿矽孔堆疊結構，係使用複數個相同或相似的基底藉由對應的穿矽孔逐一堆疊建構而成。為了詳細解說本發明穿矽孔堆疊結構的細部特徵與各部件，文中以第1~7圖繪示出一具有穿矽孔的單一基底的製作流程。
首先，請參照第1圖，此製作流程是從提供一半導體基底100開始，其係用來作為發明中所用的多種半導體元件與接線結構的設置基礎。在本實施例中，半導體基底100包含但不限定是一種矽基材。在其他實施例中，基底100可為但不限定是一種磊晶矽基材、矽鍺(SiGe)基材、矽碳(SiC)基材、或是一種矽覆絕緣(silicon-on-insulator,SOI)基材等。基底100的其中一面(後文中將稱之為主動面)上係形成有多個電路層101。每一電路層101可含有電路圖形或電路元件形成在其中，如電晶體、電容、二極體以及/或接線等結構。基底100的主動面上係蓋覆有一保護性鈍化層103，如一聚醯亞胺(polyimide,PI)層，以在製程期間保護電路層101不受到外界環境的污染或損害。前述有電路層101形成在其上的基底100可為一半導體晶圓或是已切晶完成的晶粒(die)，其可分別用於立體晶片(3D chip)組裝、晶圓級封裝(wafer-level packaging,WLP)、或是晶圓接合(wafer bonding)等製程或技術領域中。基底100在這類製程中將會彼此堆疊且以多個對應的穿矽孔結構作為互連結構來建構出一整合的積體電路結構。
上述的穿矽孔結構之製作將在後文中說明。首先，復參 照第1圖，在基底100主動面上預定的位置處會形成至少一導孔(via)105。導孔會深入基底100中，但並不貫穿整個基底100。如此，方可在導孔105中填入導電材質，並再後續進行一晶背薄化製程在相對於基底100主動面的另一面(後文中將稱之為被動面)上裸露出填有導電材質的導孔105。導孔105可以雷射鑽孔、Bosch深反應性離子蝕刻(Bosch Deep Reactive Ion Etching,Bosch DRIE)、低溫型深反應性離子蝕刻(Cryogenic DRIE)、或是濕蝕刻(不論是等向性或是異向性)等製程來形成。
基底100中形成導孔105之後，在導孔中填滿介電質107，如氧化物、氮化物或聚合物等。在此實施例中，介電質107係可作為基底100與後續所要形成的穿矽孔結構之間的襯層或絕緣層。填入介電質107後，接著在每個導孔105的介電質107中形成一漸縮式的孔洞(後文中將稱之為漸縮孔)109。漸縮孔109係具有一開放性的較粗端位在基底100的主動面上，以及一封閉性的較細端深入基底100中。這類漸縮孔109可以使用一般的蝕刻製程來形成，所形成的漸縮孔109側壁會因為其高深寬比而自然地往內傾斜。藉由採用這樣的漸縮孔設計，後續的製程中將可輕易地製作出具有所欲漸縮外型的穿矽孔結構。
形成具有所需漸縮形狀的漸縮孔109後，之後在漸縮孔109中填滿穿矽孔導體111。在本發明中，填入後的穿矽孔導體111結構會與介電質107以及保護性鈍化層103齊平。上 述的穿矽孔導體111可使用習知的電鍍製程或是高階的化學氣相沉積(CVD)製程來填入銅、鋁、鎳及/或鎢等金屬材質後形成。這些形成在漸縮孔19中的穿矽孔導體111會與漸縮孔109具有完全相同的漸縮外型。
形成穿矽孔導體111後，在第2圖中，進行一光學微影製程在基底100的主動面上形成光阻113。光阻113會具有一開口115裸露出穿矽孔導體111的較粗端。在較佳的情況下，開口115會形成在穿矽孔導體111較粗端的正中央，且其從光阻113中裸露出的區域呈圓形，得以在後續製程中製作出所欲的同心圓圖形。
將光阻113覆蓋在基底100主動面後，如第3圖所示，以此光阻作為蝕刻遮罩進行一蝕刻製程，以在穿矽孔導體111的裸露區域上形成一凹部117。與第1圖所示形成漸縮孔109的製程相似，可以採用一般的蝕刻製程來形成如第3圖所示具有所需傾斜側壁態樣的漸縮式凹部117。漸縮式凹部117之設計可使後續堆疊製程中漸縮式穿矽孔導體111之間有更佳的對合與接合機制。在較佳的情況下，本發明中的凹部117會形成在穿矽孔導體111的裸露區域正中央，凹部117會為凸出的環狀部119所圍繞，而此環狀部119則與介電質107以及周圍的保護性鈍化層103齊平。
在穿矽孔導體111上形成凹部117後，如第4圖所示，光阻113會從基底100上拔除，於此階段即完成了基底100主動面上的製程。另一方面，復參照第4圖，在基底100的 被動面上進行一選擇性蝕刻製程來移除部分的基底100以及介電質107，直到基底100中的每個漸縮式穿矽孔導體111的較細端121從基底100的被動面凸出為止。此步驟的選擇性蝕刻製程對基底100以及周圍的介電質107(如Si或SiO2)有高度的蝕刻率，使得穿矽孔導體111在蝕刻製程後會保留下來，而與穿矽孔導體111位在同一水平上的基底100與周圍的介電質107則會被蝕去。在較佳的情況下，穿矽孔導體111凸出的較細端121會與凹部117具有相同的漸縮外型，且此較細端121凸出的長度會與凹部117的凹陷深度相同或略小之。如此，在堆疊製程中凸出的較細端121將可對合地裝入另一基底100上對應的凹部117中。這樣的設計亦可有效地減少所完成的堆疊結構的整體厚度。
接著，如第5圖所示，為了要進一步改善穿矽孔導體111之間的接合，穿矽孔導體111凸出的較細端121上可以設置一凸塊態樣的導電質123來填滿接合後凹部117與較細端121之間的空隙。導電質123可以透過下列方式來形成：先進行一塗佈製程在基底100的被動面上覆蓋一層光阻(未示於圖中)，該光阻具有開口裸露出凸起的較細端121以及鄰近區域，之後再進行一電鍍製程經由光阻的開口在凸起的較細端121上鍍上導電質123。導電質123可以選自電鍍錫、電鍍銅、或是無電鍍錫等材質。在較佳的情況下，導電質123的熱膨脹係數會小於漸縮穿矽孔導體111的熱膨脹係數，使得堆疊結構在頻繁的熱循環使用環境下能有較佳的耐受性。至此階 段，製作具有穿矽孔導體111的單一基底流程即告一段落。
接著如第6圖所示，在為所製備好的基底100進行堆疊製程之前，基底100的被動面上可以再蓋上一非導電性膜(non-conductive film,NCF)125。此非導電性膜125可以覆蓋整個基底100被動面，包含穿矽孔導體111凸起的較細端121以及形成於其上的導電質123凸塊，以增強堆疊基底100之間的接合。在其他實施例中，如在玻璃覆晶(Chip-on-Glass,COG)的製程應用中，非導電性膜125可以異向性導電膜(anisotropic conductive film,ACF)來替代，來與基底100上的電路形成電性連結。
最後，如第7圖所示，複數個基底100會以將一基底100上各漸縮式穿矽孔導體111的較細端121裝入另一基底100上對應的漸縮式穿矽孔導體111凹部117之方式來逐一堆疊並相互接合。導電質123會填滿每個相互接合的凹部117與穿矽孔導體111較細端121之間的空隙。非導電性膜125則中介在相互堆疊的基底100之間。本發明的穿矽孔堆疊結構於斯完成。在本發明中，填滿凹部117與較細端121之間空隙的導電質123可以促進穿矽孔導體111之間的接合並避免空隙的形成，因而改進了穿矽孔導體111的導電性。再者，與習知使用額外的凸起結構來達成接合的習知作法不同，本發明基底100之間的接合部位(如凹部117與凸起的較細端121)是形成自原有的穿矽孔導體111。以此設計，凹部117會凹入穿矽孔導體111中並與周圍的環狀部119齊平，使得 環狀部位119不會阻礙到基底100之間的對位，且可以有效地減少整體堆疊結構的厚度。特殊的「漸縮式」穿矽孔導體111以及「漸縮式」凹部117設計使得本發明有相當簡單易行的組裝接合機制，能夠進一步地改善基底100之間的對位與疊合。
根據上述本發明的製作流程，其中亦揭露出一種穿矽孔堆疊結構。如第5圖所示，其結構包含：一基底100，含有至少一漸縮式穿矽孔導體111貫穿其中。此漸縮式穿矽孔導體111的較粗端會具有一凹部117從基底100的主動面裸露而出。凸起的環狀部119係圍繞著凹部117並與基底100表面齊平。漸縮式穿矽孔導體111的較細端121會從基底100的被動面凸出並為一導電質123凸塊結構所覆蓋。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
100‧‧‧基底
101‧‧‧電路層
103‧‧‧保護性鈍化層
105‧‧‧導孔
107‧‧‧介電質
109‧‧‧漸縮孔
111‧‧‧穿矽孔導體
113‧‧‧光阻
115‧‧‧開口
117‧‧‧凹部
119‧‧‧環狀部
121‧‧‧較細端
123‧‧‧導電質
125‧‧‧非導電性膜
本說明書含有附圖併於文中構成了本說明書之一部分，俾使閱者對本發明實施例有進一步的瞭解。該些圖示係描繪了本發明一些實施例並連同本文描述一起說明了其原理。在該些圖示中：第1~7圖繪示出根據本發明實施例一穿矽孔堆疊結構的製作流程。
須注意本說明書中的所有圖示皆為圖例性質。為了清楚 與方便圖示說明之故，圖示中的各部件在尺寸與比例上可能會被誇大或縮小地呈現。圖中相同的參考符號一般而言會用來標示修改後或不同實施例中對應或類似的特徵。
100‧‧‧基底
101‧‧‧電路層
103‧‧‧保護性鈍化層
105‧‧‧導孔
107‧‧‧介電質
109‧‧‧漸縮孔
111‧‧‧穿矽孔導體
117‧‧‧凹部
119‧‧‧環狀部
121‧‧‧較細端
123‧‧‧導電質
125‧‧‧非導電性膜

Claims (12)

  1. 一種穿矽孔堆疊結構，包含複數個疊合的基底，其中每個該基底包含：至少一漸縮式穿矽孔導體貫穿該基底；一介電質，位於該漸縮式穿矽孔導體與該基底之間，其中該漸縮式穿矽孔導體具有一較粗端以及一較細端，該較粗端具有一凹部從該基底的一主動面裸露而出，且具有一凸出部環繞於該凹部周圍，其中該凸出部具有一頂面與該介電質的一頂面齊平，該較細端從與該基底的該主動面相對的一被動面凸出；其中該複數個基底係以將一該基底的每一穿矽孔導體的較細端裝入另一該基底的穿矽孔導體的較粗端上對應的該凹部中之方式來逐一疊合。
  2. 如申請專利範圍第1項所述的穿矽孔堆疊結構，更包含一導電質填滿每一接合的該凹部與該較細端之間的空隙。
  3. 如申請專利範圍第1項所述的穿矽孔堆疊結構，更包含一非導電性膜設置在每一該疊合的基底之間。
  4. 如申請專利範圍第1項所述的穿矽孔堆疊結構，更包含一保護性鈍化層設置在每一該疊合的基底之間。
  5. 如申請專利範圍第1項所述的穿矽孔堆疊結構，其中該凹部呈漸縮形。
  6. 一種穿矽孔堆疊結構的製作方法，其步驟包含：提供複數個基底；在每一該基底的一表面中形成一介電質，並於該介電質中形成至少一漸縮式導孔；在每個該漸縮式導孔中填滿一漸縮式穿矽孔導體，其中該漸縮式穿矽孔導體的一頂面與該介電質的一頂面齊平；在每個該漸縮式穿矽孔導體的一較粗端上形成一凹部；移除部分的該基底，直到該漸縮式穿矽孔導體的一較細端從該基底的另一表面凸出為止；以將一該基底的每一穿矽孔導體的較細端裝入另一該基底的穿矽孔導體的較粗端上對應的該凹部中之方式來將該複數個基底逐一疊合。
  7. 如申請專利範圍第6項所述的穿矽孔堆疊結構的製作方法，更包含在疊合該複數個基底之前在每個該漸縮式穿矽孔導體的該凸出的較細端上設置一導電質凸塊。
  8. 如申請專利範圍第7項所述的穿矽孔堆疊結構的製作方 法，其中該導電質凸塊係以一光阻塗佈製程以及一電鍍製程來形成。
  9. 如申請專利範圍第6項所述的穿矽孔堆疊結構的製作方法，更包含在該基底的一表面上覆蓋一介電層。
  10. 如申請專利範圍第6項所述的穿矽孔堆疊結構的製作方法，更包含在該基底的一表面上覆蓋一非導電性膜。
  11. 如申請專利範圍第6項所述的穿矽孔堆疊結構的製作方法，其中該漸縮式穿矽孔導體的較粗端上的該凹部係以一光學微影製程以及一蝕刻製程來形成。
  12. 如申請專利範圍第6項所述的穿矽孔堆疊結構的製作方法，其中移除部分該基底之步驟係透過進行一選擇性蝕刻製程來達成。
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