CN105990343B - 具有用于嵌入锗材料的成形腔的半导体器件及其双沟槽制造工艺 - Google Patents

具有用于嵌入锗材料的成形腔的半导体器件及其双沟槽制造工艺 Download PDF

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CN105990343B
CN105990343B CN201510079521.5A CN201510079521A CN105990343B CN 105990343 B CN105990343 B CN 105990343B CN 201510079521 A CN201510079521 A CN 201510079521A CN 105990343 B CN105990343 B CN 105990343B
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李芳�
朱也方
陈锟
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Shanghai Huali Microelectronics Corp
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Abstract

本发明涉及半导体工艺及器件。更具体地，本发明的实施例提供一种半导体器件，该半导体器件包括由两个沟槽结构形成的成形腔，并且该成形腔填充有硅和锗材料。还提供了其他实施例。

Description

具有用于嵌入锗材料的成形腔的半导体器件及其双沟槽制造 工艺
技术领域
本发明涉及半导体工艺及器件。
背景技术
自从早年德州仪器的Jack Kilby博士发明了集成电路之时起，科学家和工程师已经在半导体器件和工艺方面作出了众多发明和改进。近50年来半导体尺寸已经有了明显的降低，这导致了不断增长的处理速度和不断降低的功耗。迄今为止，半导体的发展大致遵循着摩尔定律，摩尔定律大意是指密集集成电路中晶体管的数量约每两年翻倍。现在，半导体工艺正在朝着20nm以下发展，其中一些公司正在着手14nm工艺。这里提供一个参考，硅原子约为0.2nm，这意味着通过20nm工艺制造出的两个独立组件之间的距离仅仅约为一百个硅原子。
半导体器件制造因此变得越来越具有挑战性，并且朝着物理上可能的极限推进。华力微电子有限公司TM是致力于半导体器件和工艺研发的领先的半导体制造公司之一。
半导体技术的近期发展之一是将硅锗(SiGe)用在半导体制造中。例如，SiGe可被用于制造具有可调带隙的互补金属-氧化物-半导体(CMOS)。对于基于SiGe的工艺，尽管已经有一些常规技术，很遗憾这些技术出于以下提出的原因都是不足的。因此，需要改善的方法和系统。
发明内容
根据一实施例，本发明提供了一种半导体器件。该器件包括基板，该基板包括硅材料。该器件还包括位于基板内的腔区域。该腔区域包括与基板交界的两个凸侧壁和底部表面。该底部表面具有凹陷区域。该器件还包括至少部分地位于该腔区域内的填充材料，该填充材料包括硅和锗材料。
根据另一实施例，本发明提供了一种用于制造半导体器件的方法。该方法包括提供基板，该基板基本由硅材料组成。该方法还包括形成覆盖基板的多个隔离物。这多个隔离物包括第一隔离物、第二隔离物和第三隔离物。第一隔离物与第二隔离物由第一沟槽区域隔开。第二隔离物与第三隔离物由第二沟槽区域隔开。该方法还包括使用至少第一蚀刻剂执行第一蚀刻工艺以在第一沟槽区域处形成第一沟槽以及在第二沟槽区域处形成第二沟槽。该方法还包括移除这多个隔离物。该方法包括使用至少第二蚀刻剂执行第二蚀刻工艺以形成成形腔。该成形腔包括与基板交界的两个凸区域。该方法另外包括用硅和锗材料填充该成形腔。
附图简述
图1是图解SiGe材料的常规U形腔的简化示图。
图2是根据本发明的实施例图解腔结构的简化示图。
图3是根据本发明的实施例图解填充了SiGe材料的腔结构的简化示图。
图4A-F是根据本发明的实施例图解用于制造腔结构的处理的简化示图。
具体实施方式
本发明涉及半导体工艺及器件。更具体地，本发明的实施例提供一种半导体器件，该半导体器件包括由两个沟槽结构形成的成形腔，并且该成形腔填充有硅和锗材料。还提供了其他实施例。
给出以下描述以使得本领域技术人员能够实施和使用本发明并将其结合到具体应用背景中。各种变型、以及在不同应用中的各种使用对于本领域技术人员将是容易显见的，并且本文定义的一般性原理可适用于范围广阔的实施例。由此，本发明并不限于本文中给出的实施例，而是应被授予与本文中公开的原理和新颖性特征相一致的最广义的范围。
在以下详细描述中，阐述了许多特定细节以提供对本发明的透彻理解。然而，对于本领域技术人员显而易见的是，本发明的实践可不必局限于这些具体细节。换言之，公知的结构和器件以框图形式示出而没有详细显示，以避免淡化本发明的发明点。
请读者注意与本说明书同时提交的且对公众查阅本说明书开放的所有文件及文献，且所有这样的文件及文献的内容以参考方式并入本文。除非另有明确说明，否则本说明书(包含任何所附权利要求、摘要和附图)中所揭示的所有特征皆可由用于达到相同、等效或类似目的的可替代特征来替换。因此，除非另有明确说明，否则所公开的每一个特征仅是一组等效或类似特征的一个示例。
而且，权利要求中未明确表示“用于执行特定功能的装置”、或“用于执行特定功能的步骤”的任意组件皆不应被理解为如35 USC第112章节第6段中所规定的“装置”或“步骤”条款。特别地，在此处的权利要求中使用“….的步骤”或“….的动作”并表示涉及35 USC§112第6段的规定。
注意，在使用到的情况下，标志左、右、前、后、顶、底、正、反、顺时针和逆时针仅仅是出于方便的目的所使用的，而并不暗示任何具体的固定方向。事实上，它们被用于反映对象的各个部分之间的相对位置和/或方向。
如上所提及的，随着半导体工艺成比例地缩小，存在许多挑战。缩减IC规模提供了许多优点，包括功耗降低和计算速度提升，因为电子从一个到另一个IC组件移动的距离更短。例如，对于CMOS器件，随着各种关键尺寸(例如，栅极氧化物的大小)的减小，载流子迁移率迅速下降，这不利地影响到器件性能。当用在各种应用中时，SiGe技术可通过改善载流子迁移率来改善器件性能。
对于某些类型的器件及其制造工艺，SiGe技术能明显改善器件性能。例如，IntelTM研发了在使用90nm工艺时对SiGe的使用，以改善逻辑单元的性能。随着制造工艺移到45nm、32nm、和22nm，锗含量提升。在早期SiGe器件中，锗占到器件的不到15％。随着器件大小的减小，锗的量提升到40％甚至更高。例如，在CMOS器件中，SiGe材料嵌入在源极区域和漏极区域中。以往，为了提升SiGe材料的嵌入量，已经提出了U形和∑形腔(或者有时被称为凹槽)以用于嵌入SiGe材料。
作为示例，SiGe技术是指利用SiGe材料来改善器件性能的半导体器件和工艺。例如，SiGe可被用在异质结双极性晶体管(HBT)中，HBT相比于用来实现通信电路的常规硅双极性和硅CMOS提供了许多优势。众多特征的其中一个特征在于，Ge材料在这些器件中的使用改善了器件性能。然而，SiGe器件和工艺具有其挑战性。具体而言，在Si上生长晶格匹配的SiGe合金存在困难。在Si-STI界面上均匀生长SiGe是所期望的，因为其提升了CMOS器件的性能。例如，用于制造CMOS和其他类型器件的SiGe工艺可包括各种逻辑门图案化的滞留，诸如45/40nm、32/28nm、以及<22nm，并且维持逻辑门图案和几何非常重要。
图1是图解SiGe材料的常规U形腔的简化示图。半导体基板100包括用于容纳填充材料105的U形腔。例如，基板100包括基本上单种硅材料。填充材料105包括硅锗材料。如上文解释的，将锗材料添加到硅材料，改善了载流子迁移率和其他电气性能特性。例如，填充材料105稍后被用于形成CMOS器件。半导体基板100另外包括栅极材料101和102。例如，栅极材料包括金属栅极材料和/或多晶硅栅极材料。栅极材料101和102分别通过隔离物103和104来保护。
如上文所解释的，SiGe填充材料的重要方面是其大小或体积。较大的填充材料通常得到较佳的性能，并且应领会本发明的实施例增大了基板的腔大小，由此显著增大了SiGe填充材料的体积。
图2是根据本发明的实施例图解腔结构的简化示图。此示图仅仅是示例，不应该不当地限制权利要求的范围。本领域技术人员将领会到有许多变体、替换方案、以及变型。半导体器件200包括基板201。例如，基板201基本由硅材料构成。例如，基板是硅晶圆的一部分。半导体器件200还包括嵌入式区域202和203。在某些实现中，区域202和203包括多晶硅材料。例如，区域202和203稍后被处理以形成栅极区域。在一些实现中，区域202和203包括用于形成栅极区域的金属材料。区域202和203通过隔离物207和208保护。根据各种实施例，隔离物207和208包括氮化硅材料。特别地，隔离物207和208确保用于嵌入SiGe的腔204的开口大小。例如，在一些实现中，开口大小可高达约100nm或更大。取决于器件尺寸，其他开口大小也是可能的。例如，在20/22nm(或更小的)工艺中，开口大小可能更小。确保腔的开口大小的益处之一是使得用填充材料填充腔变为一项容易并且相容的过程。在没有隔离物的情况下，腔的开口可能变形为其他形状(例如，由于蚀刻的原因成为圆角或边)。
如在图1中所图解的，在各种常规技术中，用于嵌入SiGe材料的腔是U形的。应领会，腔204的形状包括凸区域205和206，它们有效地增大了腔204的体积以及稍后将被填充到腔204中的SiGe材料的量。另外，腔204包括突出硅基板201的底部表面的凹区域210。
应领会，SiGe材料可以各种方式沉积到腔204中，并由此可具有不同的组成。例如，SiGe材料可包括10％到50％的锗含量。另外，锗材料的浓度在腔区域内可变。
相比于∑形腔，腔204的形状提供约20％到30％的体积提升。腔204稍后用SiGe材料填充。相比于具有∑形腔的器件，具有填充到腔204中的SiGe材料的PMOS器件可提供3％或甚至更大的PMOS性能改善。相比于常规腔形状，除了性能改善之外，根据本发明的实施例的腔形状还可提供更好的产量。通过相对较大的开口大小，可有效地控制填充到腔中的SiGe材料的量。根据本发明的实施例的图2中所图解的形状的腔还有其他益处。
图3是根据本发明的实施例图解填充了SiGe材料的腔结构的简化示图。此示图仅是示例，不应该不当地限制权利要求的范围。本领域技术人员将领会到许多变体、替换方案、以及变型。如图3所示，半导体300包括被填充到成形腔中的填充材料320。填充材料320包括硅锗(SiGe)材料。如上文所解释的，嵌入在基板301中的SiGe材料可改善各种电气特性，诸如载流子迁移率。如在图1中所图解的，在各种常规技术中，用于嵌入SiGe材料的腔是U形的。应领会，腔309的形状包括凸区域，它们有效地增大了腔309的体积以及稍后将被填充到腔309中的SiGe材料的量。
图4A-F是根据本发明的实施例图解用于制造腔结构的处理的简化示图。这些示图仅仅提供示例，不应该不当地限制权利要求的范围。本领域技术人员将领会到有许多变体、替换方案、以及变型。例如，图4A-F中图解的各种步骤可增加、移除、替换、重复、修改、重新安排、和/或重叠，并且不应该不当地限制权利要求的范围。
如图4A所示，提供硅基板401以形成所要形成的半导体器件400。例如，硅基板400是半导体晶圆的一部分，在该半导体晶圆上制造了很多具有和基板401的结构(例如，腔)类似的结构的基板。在各种实施例中，硅基板400经历表面处理，诸如抛光、清洁和/或其他处理。
形成隔离物402、403和404，如图4B所示。例如，这些隔离物可通过化学沉积、定向膜沉积和/或其他工艺来形成。在各种实施例中，这些隔离物包括硅和氮材料(例如，SiN)。例如，隔离物的化学组成被特别选择成不同于基板401的化学组成，在基板401材料(例如，硅)被蚀刻掉以形成沟槽时隔离物可保持完好。在各种实施例中，基板材料的后续蚀刻是使用氟化氢(HF)材料来执行的，并且隔离物对HF具有化学抵抗力。
在各种实施例中，这些隔离物的大小和距离是根据要形成的器件和腔而预先确定的。例如，隔离物404由约10nm到20nm的宽度所表征，这定义了所要形成的两个沟槽之间的距离。在一实施例中，从隔离物404到隔离物403的距离约为40nm到50nm，这定义了沟槽的宽度。
由于隔离物定义沟槽图案，图4C图解了将在隔离物之间形成的沟槽405和406。在各种实施例中，执行定向蚀刻以形成沟槽405和406。例如，可通过等离子体蚀刻工艺来形成沟槽405和406。由隔离物所定义，沟槽可由约40nm到50nm的宽度所表征，并且相隔约10nm到20nm的距离。将领会，取决于具体实现和器件尺寸，沟槽的宽度以及沟槽之间的距离可以是不同的。
图4D图解在基板401内形成有沟槽405和406的基板。另外，隔离物402、403和404从基板被移除。根据某些实现，形成隔离物以用于促成沟槽405和406的形成。一旦形成如图4C中所示的沟槽，隔离物402、403和404就不再需要并且因此被移除。作为示例，可使用H3PO4来移除使用SiN类型的材料所构成的隔离物。取决于隔离物材料的组成，也可使用其他类型的蚀刻剂来移除隔离物。除了移除隔离物材料之外，还可执行额外的清洁工艺以移除由于蚀刻工艺所导致的残留物。例如，可使用HF材料来执行该清洁工艺。
图4E图解成形腔的形成。在各种实施例中，所示的成形腔是通过经由沟槽405和406执行蚀刻工艺来形成的。更具体地，蚀刻剂材料进入到沟槽405和406。例如，执行化学或湿式蚀刻工艺。取决于具体实现，可使用各种类型的蚀刻剂。在特定实施例中，使用四甲基氢氧化铵(TMAH)作为蚀刻剂，其有效地移除硅基板。取决于实现，也可使用其他类型的蚀刻剂。
在蚀刻工艺期间，诸如TMAH之类的一种或更多种蚀刻剂进入到沟槽405和406。例如，在湿式蚀刻工艺期间，蚀刻剂向所有方向扩展，既侧向扩展又往下扩展。例如，由于从区域410的两侧的蚀刻，区域410的整体基本被移除。如上文所解释的，区域410基本由作为基板401的部分的硅材料组成。区域410是在形成沟槽405和406之后基板的残留区域。取决于所执行的蚀刻的量，区域410可包括在蚀刻工艺期间未被完全移除的部分。例如，凹陷区域411是区域410的一部分，并且由于其处于区域410的底部，因此在蚀刻工艺期间未被移除。蚀刻剂被特别地选择成有效移除掉硅材料。如图4E中可见的，蚀刻剂蚀刻到沟槽405和406的侧壁中，并且由此分别创造了凸腔形状405A和406A。
应领会，凸腔结构有效地增大了腔大小，并且由此增大了可被填充到腔内的SiGe材料的量。例如，与∑形腔相比，通过图4E中图解的蚀刻工艺所创建的腔的形状提供约20％到30％的体积提升。该腔稍后用SiGe材料填充。相比于具有∑形腔的器件，具有填充到该成形腔中的SiGe材料的PMOS器件可提供3％或甚至更大的PMOS性能改善。相比于常规腔形状，除了性能改善之外，根据本发明的实施例的腔形状还可提供更好的产量。通过相对较大的开口大小，可有效地控制填充到腔中的SiGe材料的量。
相比于常规腔形状，除了性能改善之外，根据本发明的实施例的腔形状还可提供更好的产量。通过相对较大的开口大小，可有效地控制填充到腔中的SiGe材料的量。该腔形状还有其他益处。
现在参照图4F。在形成该成形腔之后，SiGe材料430被填充到该成形腔中。取决于实现和具体需求，SiGe材料430可具有非均匀的轮廓。例如，锗材料的浓度在腔区域内变化，这可以是锗和硅材料的逐渐沉积的结果。在某些实现中，化学气相沉积工艺被用于将SiGe材料沉积到成形腔中。半导体器件400另外可包括附加结构。例如，诸如隔离物421和423以及多晶硅嵌入物422和424之类的附加结构形成在基板401上。根据各种实施例，填充有SiGe材料430的区域可被用于形成CMOS器件的源极区域或漏极区域。
根据一实施例，本发明提供了一种半导体器件。该器件包括基板，该基板包括硅材料。该器件还包括位于基板内的腔区域。该腔区域包括与基板交界的两个凸侧壁和底部表面。该底部表面具有凹陷区域。该器件还包括至少部分地位于该腔区域内的填充材料，该填充材料包括硅和锗材料。
根据另一实施例，本发明提供了一种用于制造半导体器件的方法。该方法包括提供基板，该基板基本由硅材料组成。该方法还包括形成覆盖基板的多个隔离物。这多个隔离物包括第一隔离物、第二隔离物和第三隔离物。第一隔离物与第二隔离物由第一沟槽区域隔开。第二隔离物与第三隔离物由第二沟槽区域隔开。该方法还包括使用至少第一蚀刻剂执行第一蚀刻工艺以在第一沟槽区域处形成第一沟槽以及在第二沟槽区域处形成第二沟槽。该方法还包括移除这多个隔离物。该方法包括使用至少第二蚀刻剂执行第二蚀刻工艺以形成成形腔。该成形腔包括与基板交界的两个凸区域。该方法另外包括用硅和锗材料填充该成形腔。
尽管上文是对特定实施例的全面描述，但是也可使用各种变型、替换构造和等效方案。因此，上述描述和说明不应当被解释为限制由所附权利要求限定的本发明的范围。

Claims (12)

1.一种用于制造半导体器件的方法，所述方法包括：
提供基板，所述基板基本包括硅材料；
形成覆盖所述基板的多个隔离物，所述多个隔离物包括第一隔离物、第二隔离物和第三隔离物，所述第一隔离物与所述第二隔离物由第一沟槽区域隔开，所述第二隔离物与所述第三隔离物由第二沟槽区域隔开；
使用至少第一蚀刻剂执行第一蚀刻工艺以在所述第一沟槽区域处形成第一沟槽以及在所述第二沟槽区域处形成第二沟槽；
移除所述多个隔离物；
使用至少第二蚀刻剂执行第二蚀刻过程以形成成形腔，所述成形腔包括与所述基板交界的两个凸区域；以及
用硅和锗材料填充所述成形腔。
2.如权利要求1所述的方法，其特征在于，所述第二蚀刻剂包括TAMH材料。
3.如权利要求1所述的方法，其特征在于，还包括一个或更多个栅极区域。
4.如权利要求1所述的方法，其特征在于，还包括形成多晶硅隔离物结构。
5.如权利要求1所述的方法，其特征在于，所述多个隔离物包括氮化硅材料。
6.如权利要求1所述的方法，其特征在于，使用H3PO4材料移除所述多个隔离物。
7.如权利要求1所述的方法，其特征在于，还包括在移除所述多个隔离物之后清洁所述基板。
8.如权利要求1所述的方法，其特征在于，所述第二隔离物材料由约10nm到20nm的宽度所表征。
9.如权利要求1所述的方法，其特征在于，所述第一隔离物与所述第二隔离物之间的间距约为40nm到50nm。
10.如权利要求1所述的方法，其特征在于，所述第一蚀刻剂包括HF材料。
11.如权利要求1所述的方法，其特征在于，还包括执行化学沉积以用于形成所述多个隔离物。
12.如权利要求1所述的方法，其特征在于，还包括清洁所述基板的表面。
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US6403486B1 (en) * 2001-04-30 2002-06-11 Taiwan Semiconductor Manufacturing Company Method for forming a shallow trench isolation
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US7537994B2 (en) * 2006-08-28 2009-05-26 Micron Technology, Inc. Methods of forming semiconductor devices, assemblies and constructions
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US8329547B2 (en) * 2010-07-22 2012-12-11 United Microelectronics Corp. Semiconductor process for etching a recess into a substrate by using an etchant that contains hydrogen peroxide
CN103377925A (zh) * 2012-04-13 2013-10-30 中国科学院微电子研究所 一种半导体结构及其制造方法
JP2014120729A (ja) * 2012-12-19 2014-06-30 Fuji Electric Co Ltd 半導体基板の製造方法および半導体装置
AU2014240001B2 (en) * 2013-03-15 2017-07-27 Pacecontrols Llc Controller for automatic control of duty cycled HVAC&R equipment, and systems and methods using same
US20150048422A1 (en) * 2013-08-16 2015-02-19 International Business Machines Corporation A method for forming a crystalline compound iii-v material on a single element substrate
US9536888B2 (en) * 2014-12-23 2017-01-03 Taiwan Semiconductor Manufacturing Co., Ltd. Method to prevent oxide damage and residue contamination for memory device
CN105990342B (zh) * 2015-02-13 2019-07-19 上海华力微电子有限公司 具有用于嵌入锗材料的成形腔的半导体器件及其制造工艺
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