CN106783740B - 用于金属栅极的制造技术 - Google Patents

用于金属栅极的制造技术 Download PDF

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CN106783740B
CN106783740B CN201611169046.1A CN201611169046A CN106783740B CN 106783740 B CN106783740 B CN 106783740B CN 201611169046 A CN201611169046 A CN 201611169046A CN 106783740 B CN106783740 B CN 106783740B
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layer
npn
transistor
ild0
metal gates
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CN106783740A (zh
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雷通
陈勇跃
周海锋
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Shanghai Huali Microelectronics Corp
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Abstract

本公开内容的一个方面是一种通过在ILD0层之上形成特殊层以代替传统TiN硬掩模来制造金属栅极的方法，以避免由于传统的ILD0 CMP造成的ILD0损耗。该方法可包括：在ILD0 CMP之后，在ILD0层之上形成薄的第一可灰化膜层；然后在该第一层之上形成薄的第二介电层；在针对第一区域(例如PMOS或NMOS)的铝CMP工艺期间，通过抛光移除第二层直至第一可灰化膜层的顶表面；以及然后通过诸如燃烧之类的灰化法移除第一可灰化膜层。以此方式，可降低第一铝CMP步骤期间的ILD0损耗并由此降低ILD0的初始高度，这进而可以降低填充在腔中的初始虚栅极的高度。

Description

用于金属栅极的制造技术
技术领域
本发明涉及半导体工艺与器件。
背景技术
自从早年德州仪器的Jack Kilby博士发明了集成电路之时起，科学家们和工程师们已经在半导体器件和工艺方面作出了众多发明和改进。近50年来，半导体尺寸已经有了明显的降低，这转化成不断增长的处理速度和不断降低的功耗。迄今为止，半导体的发展大致遵循着摩尔定律，摩尔定律大致是说密集集成电路中晶体管的数量约每两年翻倍。现在，半导体工艺正在朝着20nm以下发展，其中一些公司正在着手14nm工艺。这里仅提供一个参考，一个硅原子约为0.2nm，这意味着通过20nm工艺制造出的两个独立组件之间的距离仅仅约为一百个硅原子。
半导体器件制造因此变得越来越具有挑战性，并且朝着物理上可能的极限推进。
在制造典型栅极尺寸小于50nm的晶体管时，所谓的“高k/金属栅极”(HKMG)技术已经普及。根据HKMG制造工艺流程，包括在栅电极中的绝缘层由高k材料构成。这与常规的氧化物/多晶硅(poly/SiON)方法相反，在常规的氧化物/多晶硅方法中，栅电极绝缘层通常由氧化物构成，在基于硅的器件情况下优选二氧化硅或氮氧化硅。目前，有两种不同的方法在半导体制造工艺流程中实现HKMG。第一种方法称为栅极-首先，制造工艺流程类似于传统poly/SiON方法过程中采取的流程。首先形成栅电极，包括高k电介质膜和功函数金属膜，继之以后续的晶体管制造阶段，例如，源极区域和漏极区域的限定、部分基板表面的硅化、金属化等等。另一方面，根据也称之为栅极-最后或替换栅极的第二种方案，在存在牺牲虚栅极的情况下执行各个制造阶段，诸如掺杂剂离子注入、源极区域和漏极区域形成以及基板硅化。该虚栅极在高温源极/漏极成型以及所有硅化物退火周期都已执行之后由真实的栅极替代。
发明内容
以下给出一个或多个方面的简要概述以提供对这些方面的基本理解。此概述不是所有构想到的方面的详尽综览，并且既非旨在指认出所有方面的关键性或决定性要素亦非试图界定任何或所有方面的范围。其唯一的目的是要以简化形式给出一个或多个方面的一些概念以为稍后给出的更加详细的描述之序。
根据本发明的一方面，提供了一种用于制造半导体器件的金属栅极的方法，该方法包括提供衬底；在该衬底上提供第一金属栅极型晶体管区域和第二金属栅极型晶体管区域，其中该第一金属栅极型晶体管区域和该第二金属栅极型晶体管区域的每一者包括虚栅极；在该第一金属栅极型晶体管区域和该第二金属栅极型晶体管区域周围提供零阶层间介电ILD0层；在该ILD0层之上形成可灰化的第一层；在该第一层之上形成第二层，该第二层包括碳化硅SiC；执行图案化工艺以移除该第一金属栅极型晶体管区域中的虚栅极并在该第一金属栅极型晶体管区域中形成第一金属栅极，该第一金属栅极为第一金属栅极型；执行第一化学机械抛光CMP工艺以抛光该第一金属栅极型晶体管区域中的该第一金属栅极，其中该第一CMP工艺包括移除该第二层但不移除该第一层；以及通过灰化法移除该第一层。
附图说明
图1A-1F示出用于制造半导体器件的传统两步法CMP工艺的过程。
图2A示出在根据本公开内容的制造半导体器件的改进的两步法CMP工艺期间，在ILD0CMP之后，可在ILD0层之上形成第一层和第二层。
图2B示出可在根据本公开内容的改进的两步法CMP工艺期间移除虚栅极以形成腔。
图2C示出在根据本公开内容的改进的两步法CMP工艺期间可执行图案化工艺以使替代的栅极材料可被填充到图2B所示的腔中以形成金属栅极。
图2D示出可执行铝CMP以抛光图2C中形成的栅极的顶表面，使得控制抛光在图2A中所示的第二层被移除之后在图2A中所示的第一层的顶表面处停止。
图2E示出在第二层如图2D所示地被移除之后，图2A中所示的第一层可通过灰化法来移除。
参照以下附图，可实现对各个实施例的本质和优点的进一步理解。在附图中，类似组件或特征可具有相同的附图标记。此外，相同类型的各个组件可通过在附图标记后跟随破折号以及在类似组件间进行区分的副标记来区分。如果在说明书中仅使用第一附图标记，则该描述适用于具有相同第一附图标记的任何一个类似组件而不管副附图标记。
具体实施方式
本公开内容涉及用于半导体的高k/金属栅极(HKMG)叠层的制造，尤其涉及降低该HKMG叠层形成之后O2向IL中的扩散。
给出以下描述以使得本领域技术人员能够实施和使用本发明并将其结合到具体应用背景中。各种变型、以及在不同应用中的各种使用对于本领域技术人员将是容易显见的，并且本文定义的一般性原理可适用于较宽范围的实施例。由此，本发明并不限于本文中给出的实施例，而是应被授予与本文中公开的原理和新颖性特征相一致的最广义的范围。
在以下详细描述中，阐述了许多特定细节以提供对本发明的更透彻理解。然而，对于本领域技术人员显而易见的是，本发明的实践可不必局限于这些具体细节。换言之，公知的结构和器件以框图形式示出而没有详细显示，以避免模糊本发明。
请读者注意与本说明书同时提交的且对公众查阅本说明书开放的所有文件及文献，且所有这样的文件及文献的内容以参考方式并入本文。除非另有直接说明，否则本说明书(包含任何所附权利要求、摘要和附图)中所揭示的所有特征皆可由用于达到相同、等效或类似目的的可替代特征来替换。因此，除非另有明确说明，否则所公开的每一个特征仅是一组等效或类似特征的一个示例。
而且，权利要求中未明确表示用于执行特定功能的装置、或用于执行特定功能的步骤的任意组件皆不应被理解为如35USC第112章节第6段中所规定的装置或步骤条款。特别地，在此处的权利要求中使用“….的步骤”或“….的动作”并不表示涉及35USC第112章第6段的规定。
注意，在使用到的情况下，标志左、右、前、后、顶、底、正、反、顺时针和逆时针仅仅是出于方便的目的所使用的，而并不暗示任何具体的固定方向。事实上，它们被用于反映对象的各个部分之间的相对位置和/或方向。
高k栅极结构中的金属栅极电极使用铝或铝合金具有成本和性能优势。铝栅极化学机械抛光(CMP)工艺对于制造具有铝栅极的高k金属栅极晶体管是一项非常重要的工艺。为了增加间隙填充空间，铝栅极结构的CMP工艺典型地包括两个CMP步骤：用于P型铝栅极晶体管(PFET)的CMP工艺和用于N型铝栅极晶体管(NFET)的CMP工艺。在用于PFET的CMP工艺中，首先在PMOS区域中移除虚多晶硅。在此步骤期间，随后完成PMOS区域的功函数沉积并且形成PMOS区域的金属栅极。在形成PMOS区域的金属栅极之后，在NMOS区域中移除虚多晶硅，然后完成NMOS区域的功函数沉积并且形成NMOS区域的金属栅极。尽管此两步法的CMP工艺相对较长，但是避免了功函数金属沉积的选择性蚀刻，后者更加难以控制。
图1A-1F示出用于制造半导体器件的传统两步法CMP工艺的过程。图1A示出通过此工艺可在衬底之上提供半导体器件100。如图所示，可使用双侧壁间隔物工艺在衬底之上提供间隔物106a-b。出于解说的目的，术语侧壁间隔物可指代第一侧壁间隔物106a和第二侧壁间隔物106b。在一个实施例中，侧壁间隔物106从内向外的顺序结构是第一侧壁间隔物106a的氧化硅层-第一侧壁间隔物106a的氮化硅层-第二侧壁间隔物106b的氧化硅层-第二侧壁间隔物106b的氮化硅层。在其他实施例中，可通过单侧壁间隔物工艺形成，例如侧壁间隔物可仅由氧化硅和氮化硅之一构成。
还是如图1A所示，可例如通过CVD工艺或PVD工艺在衬底上形成层间介电层104。层间介电层104可被称为零阶层间介电层或ILD0。层间介电层104可由任何恰当的绝缘材料构成，诸如氧化硅或氮化硅等。仍是如图所示，半导体器件100可包括P型金属栅极晶体管区域(PFET)中的第一虚栅极108a、N型金属栅极晶体管区域(NFET)中的第二虚栅极108b。还是如图所示，可在ILD0 104之上形成硬掩模层102。硬掩模层102可在CMP工艺之后形成于ILD0104上并且包括氮化钛(TiN)和/或HMOX。
图1B示出可执行图案化工艺以使得PFET处的虚栅极108a可被移除以形成腔110。图1C示出可向腔110中沉积PFET功函数金属栅极材料(例如，铝)以形成PFET替代金属栅极112a。图1D示出随后可使用铝CMP工艺抛光该替代金属栅极112a的顶表面以确保金属栅极112a的高度。ILD0 104一般被用于降低此CMP工艺过程中的过度损伤以确保所沉积的替代金属栅极112a的高度的精确度。此外，ILD0 104也可被用作后续形成的通孔和金属互连的应力释放层以保护半导体器件100。特别地，在此CMP过程中可使用相对较高的抛光速度来抛光该替代的金属栅极112a和ILD0 104。图1E示出NFET处的虚栅极108b被移除以形成腔110。图1F示出可向腔110中沉积功函数金属栅极材料以形成NFET替代金属栅极112b，并且可执行另一CMP工艺以使替代金属栅极112b与ILD0 104齐平。
由于上述常规的两步法CMP工艺一般采用抛光浆料，其具有比铝移除速率更大的多晶硅移除速率，因此往往对ILD0 104的表面进行过度抛光。传统上，为了解决ILD0 104的此过度抛光，可沉积额外的ILD0 104。例如，若形成PMOS和NMOS栅极之后的ILD0 104的期望厚度为600埃，且每次ILD0 CMP工艺由于此过度抛光导致100埃损耗，则可以以800埃的厚度沉积初始ILD0 104以补偿上述两步法CMP工艺过程中的ILD0损耗。
然而，由于ILD0的初始厚度也是在图1B所示的PMOS虚栅极移除过程中形成的腔110的高度。相应地，更厚的ILD0意味着更深的腔110以及腔110的深度与宽度之间比率的增大，因为ILD0的宽度相对保持不变。此增大的比率(由于必须考虑ILD0损耗)会增大在腔110中填充栅极材料的难度。
本公开内容致力于解决目前由于必须考虑两步法CMP工艺中的ILD0损耗而提高了在腔110中填充栅极材料的难度的问题。本公开内容的一个方面是一种通过在ILD0层之上形成特殊层以代替传统TiN硬掩模102来制造金属栅极的方法，以避免由于传统的ILD0CMP造成的ILD0损耗。
本公开内容的附加的方面以及其他特征将在以下说明书中陈述，且在本领域普通技术人员分析了以下内容后将部分地变得显而易见，或可从本公开内容的实施中获知。本公开内容的优点可特别如在所附权利要求中所指出地那样实现和获得。
根据本公开内容，一些技术效果可部分地通过一种制造金属栅极的方法来达成，该方法包括：在ILD0CMP之后，在ILD0层之上形成薄的第一可灰化膜层；然后在该第一层之上形成薄的第二介电层；在针对第一区域(例如PMOS或NMOS)的铝CMP工艺期间，通过抛光移除第二层直至第一可灰化膜层的顶表面；以及然后通过诸如燃烧之类的灰化法移除第一可灰化膜层。以此方式，相比于传统方法可降低第一铝CMP步骤过程中的ILD0损耗并由此降低ILD0的初始高度，这进而可以降低填充在腔中的初始虚栅极的高度，并由此相比于传统方法改善虚栅极的填充工艺。
图2A-E示出根据本公开内容的用于制造半导体器件的金属栅极的改进工艺。这些示图中示出的工艺相比于上文通过图1A-1F描述和解说的两步法CMP工艺带来了改进，因此参考图1A-F来进行描述。应理解，尽管这些图中示出的改进工艺以PMOS栅极制造开始，但这并不是限制性的。在一些其他实施例中，根据本公开内容的改进工艺可以NMOS栅极制造开始。图2A示出在此改进工艺期间，在ILD0CMP之后，可在ILD0 104之上形成两个层。如上所述，第一层204可以是薄可灰化层，诸如无定形碳膜层。在一些实施例中，可使用合适的化学气相沉积(CVD)、溅射沉积、和/或任何其他合适的工艺来生长第一层204。第一层204的无定形碳膜的属性可根据沉积期间使用的参数而变化。在一些实施例中，第一层的厚度可被控制在介于300埃至1000埃之间。还是如上所述的，在根据本公开内容的改进工艺期间可在第一层204之上形成第二层202。第二层202可包括碳化硅(SiC)。在一些实施例中，第二层202的厚度可被控制在100埃至500埃。
图2B示出虚栅极108a可被移除以形成腔110a。在一些实施例中，可通过使用能溶解多晶硅的氢氧化四甲铵(TMAH)工艺来完成该移除。在一些实现中，可以使腔110a的开口比虚栅极108的宽度更宽。图2C示出可执行图案化工艺以使得替代的栅极材料可被填充至腔110a中以形成栅极112a。图2D示出可执行铝CMP以抛光栅极112a的顶表面，使得控制抛光在第二层202被移除之后在第一层204的顶表面处停止。在一些实施例中，第二层202可使用干法蚀刻工艺例如主要通过诸如NF3之类的氟化气体来移除。图2E示出在移除第二层202之后，可通过灰化法移除第一层204。在一些实施例中，第一层204的移除可涉及使用氧化气体。例如，可使用O2烧掉包括如上所述的无定形碳的可灰化的第一层204。在图2E所示的步骤之后，用于制造金属栅极的该改进工艺可以与上述常规工艺类似的方式继续——例如，形成TiN硬掩模、移除NMOS处的虚栅极、填充替代栅极材料以形成NMOS栅极以及执行铝CMP以抛光NMOS栅极的顶表面。根据此改进的工艺，通过第一层204和第二层202，可避免此工艺中第一铝CMP步骤过程中的ILD0损耗。以此方式，相比于上述传统工艺，可以降低在此改进的两步法CMP工艺期间为了考虑ILD0损耗所需要沉积的ILD0 104的初始厚度。
如贯穿本申请的各个部分所解释的，本发明的实施例相比于现有技术和方法可提供许多优点。应领会，本发明的各实施例与现有系统和工艺相兼容。例如，根据本发明的实施例所描述的成型腔可使用现有装备来制造。根据本发明的实施例的成型腔可易于用来制造诸如CMOS、PMOS、NMOS等各种类型的器件。
尽管上文是对特定实施例的全面描述，但是也可使用各种变型、替换构造和等效方案。除了上述内容之外，还存在其他的实施例。因此，上述描述和说明不应当被解释为限制由所附权利要求限定的本发明的范围。

Claims (9)

1.一种用于制造半导体器件的金属栅极的方法，所述方法包括：
提供衬底；
在所述衬底上提供第一型晶体管区域和第二型晶体管区域，其中所述第一型晶体管区域和所述第二型晶体管区域的每一者包括虚栅极；
在所述第一型晶体管区域的虚栅极和所述第二型晶体管区域的虚栅极周围提供零阶层间介电ILD0层；
在所述ILD0层之上形成可灰化的第一层；
在所述第一层之上形成第二层，所述第二层包括碳化硅SiC；
执行图案化工艺以移除所述第一型晶体管区域中的虚栅极并在所述第一型晶体管区域中形成第一型晶体管的金属栅极；
执行第一化学机械抛光CMP工艺以抛光所述第一型晶体管的金属栅极，其中所述第一化学机械抛光CMP工艺包括移除所述第二层但不移除所述第一层；以及
通过灰化法移除所述第一层。
2.如权利要求1所述的方法，其特征在于，所述第一层的厚度介于300埃至1000埃之间。
3.如权利要求1所述的方法，其特征在于，所述第二层的厚度介于100埃至500埃之间。
4.如权利要求1所述的方法，其特征在于，使用氧化气体通过灰化法移除所述第一层。
5.如权利要求1所述的方法，其特征在于，所述第一层包括无定形碳。
6.如权利要求1所述的方法，其特征在于，所述第一型晶体管为P型金属栅极晶体管，以及所述第二型晶体管为N型金属栅极晶体管。
7.如权利要求1所述的方法，其特征在于，所述第一型晶体管为N型金属栅极晶体管，以及所述第二型晶体管为P型金属栅极晶体管。
8.如权利要求1所述的方法，其特征在于，还包括：
在移除所述第一层之后在所述ILD0层之上形成硬掩模层；
执行图案化工艺以移除所述第二型晶体管区域中的虚栅极并在所述第二型晶体管区域中形成第二型晶体管的金属栅极；
执行化学机械抛光CMP工艺以抛光所述第二型晶体管的金属栅极，其中所述化学机械抛光CMP工艺包括移除所述硬掩模层。
9.如权利要求8所述的方法，其特征在于，所述硬掩模层包括氮化钛TiN。
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