CN105990242A - 平板型rom器件的制备方法 - Google Patents
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Abstract
本发明公开了一种平板型ROM器件的制备方法,包括步骤:提供衬底,在衬底上形成P阱;在P阱上形成光刻掩膜层并进行光刻形成的注入窗口;在形成的注入窗口进行P型离子的注入形成P型区;在形成的注入窗口进行N型离子的注入从而在P型区上形成N型区;形成栅氧化层以及多晶硅栅完成器件的制备。上述平板型ROM器件的制备方法,利用同一光刻掩膜层进行P型区以及N型区的制备,从而在原来器件中的N型区与P阱的界面处形成浓度高于P阱的P型区,增加了PN结势垒高度,进而减小了器件的源漏极漏电,缓解了穿通现象,提高了器件耐压。并且,制备过程中无需增加额外的隔离掩膜版就可以有效提高器件的耐击穿特性,节省了生产成本。
Description
技术领域
本发明涉及半导体制备技术领域,特别是涉及一种平板型ROM器件的制备方法。
背景技术
在MCU(Micro Control Unit,微控制单元)、ASIC(Application SpecificIntegrated Circuit,专用集成电路)等集成电路中,往往需要大面积的平板型只读存储器(Flat Cell ROM)阵列对各种程序和数据进行存储和读取。为了提高Flat Cell ROM电路的可靠性,必须提高器件耐压(BV),降低漏电,减缓穿通(punch through)现象。传统工艺在完成N型区(N型区作为平板型ROM器件的源漏区域)的制备后还经常需要增加一块额外的隔离掩模版(Mask)来进行掺杂离子的注入以遏制源漏极之间穿通现象的发生,增加了工艺的成本以及工艺难度。
发明内容
基于此,有必要针对上述问题,提供一种成本较低且可有效降低源漏电极漏电、提高器件击穿电压的平板型ROM器件的制备方法。
一种平板型ROM器件的制备方法,包括以下步骤:提供衬底,在所述衬底上形成P阱;在所述P阱上形成光刻掩膜层并进行光刻形成注入窗口;利用所述光刻掩膜层在形成的注入窗口进行P型离子的注入形成P型区;利用所述光刻掩膜层在形成的注入窗口进行N型离子的注入从而在所述P型区上形成N型区;所述N型区包括第一N型区和第二N型区;所述第一N型区和所述第二N型区分别作为所述平板型ROM器件的源极、漏极;在形成的器件表面形成栅氧化层以及多晶硅栅完成器件的制备。
在其中一个实施例中,利用所述光刻掩膜层在形成的注入窗口区进行P型离子的注入形成P型区的步骤中P型离子为倾斜注入。
在其中一个实施例中,所述P型离子是与竖直平面呈20~30度的角度进行注入的。
在其中一个实施例中,利用所述光刻掩膜层在形成的注入窗口区进行P型离子的注入形成P型区的步骤中,注入的P型离子的剂量为7×1012~3×1013㎝-2。
在其中一个实施例中,利用所述光刻掩膜层在形成的注入窗口进行N型离子的注入从而在所述P型区上形成N型区的步骤之后还包括步骤:进行热处理。
在其中一个实施例中,所述P型离子为硼、铟和二氟化硼中的一种。
在其中一个实施例中,所述N型离子为砷、磷和锑中的一种。
在其中一个实施例中,所述P型离子为硼,所述N型离子为砷。
上述平板型ROM器件的制备方法,利用同一光刻掩膜层进行P型区以及N型区的制备,从而在器件中的N型区与P阱的界面处形成浓度高于P阱的P型区,提高了N型区与P阱形成的沟道区域的界面处的P型杂质浓度,增加了PN结势垒高度,进而减小了器件的源漏极漏电,缓解了穿通现象,提高了器件耐压。并且,N型区和P型区是利用同一光刻掩膜层进行制备的,因此无需增加额外的隔离掩膜版就可以有效提高器件的耐击穿特性,节省了生产成本。
附图说明
图1为一实施例中的平板型ROM器件的制备方法的流程图;
图2为图1所示实施例中的平板型ROM器件的制备方法中执行步骤S130后的器件结构示意图;
图3为图1所示实施例中的平板型ROM器件的制备方法中执行步骤S140后的器件结构示意图;
图4为图1所示实施例中的平板型ROM器件的制备方法中执行步骤S150后的器件结构示意图;
图5为图4所示实施例中的平板型ROM器件的N型区与沟道边界杂质分布曲线;
图6为图4所示实施例中的平板型ROM器件的电流-电压特性曲线。
具体实施方式
为使本发明的目的、特征和优点能够更为明显易懂,下面结合附图对本发明的具体实施方式做详细的说明。
在本说明书和附图中,分配给层或区域的参考标记N和P表示这些层或区域分别包括大量电子或空穴。进一步地,分配给N或P的参考标记+和-表示掺杂剂的浓度高于或低于没有这样分配到标记的层中的浓度。在下文的优选实施例的描述和附图中,类似的组件分配有类似的参考标记且该处省略其冗余说明。
图1所示为一实施例中的平板型ROM器件的制备方法的流程图,包括以下步骤。
S110,提供衬底,在衬底上形成P阱。
S120,在P阱上形成光刻掩膜层并进行光刻形成注入窗口。
S130,利用光刻掩膜层在形成的注入窗口区进行P型离子的注入形成P型区。
利用形成的光刻掩膜层作为阻挡层进行P型离子注入,形成P型区。在本实施例中,P型离子为倾斜注入,即其与垂直平面成一定的角度α进行注入。该角度α为20~30度。通过将P型离子带角度进行注入可以对注入深度以及区域进行控制。在P型离子注入过程中,P型离子浓度过高,PN结易发生雪崩击穿,器件击穿电压反而会降低。因此,P型离子注入需要选择合适剂量。具体地,注入的P型离子为硼,且注入的离子剂量为7×1012~3×1013㎝-2。在其他的实施例中,P型离子也可以为铟或者二氟化硼(BF2)。
图2为执行步骤S130的结构示意图。如图2所示,衬底(图中未示)上形成有P阱202,在P阱表面形成有光刻掩膜层20以及通过P型离子带角度注入形成的P型区。在本实施例中,P型区包括第一P型区204和第二P型区206。
S140,利用光刻掩膜层在形成的注入窗口区进行N型离子的注入从而在P型区上形成N型区。
具体地,通过N型离子的注入,在P型区内形成N+区。在本实施例中,N型离子为砷,且其注入过程为垂直器件表面注入。在其他的实施例中,注入的N型离子也可以为磷或者锑。
图3为执行步骤S140后的结构示意图。如图3,在P型区形成有第一N+区208和第二N+区210。第一N+区208和第二N+区210分别作为平板型ROM器件的源极、漏极。P阱202形成平板型ROM器件的沟道区域。而P型区位于N型区和P阱202之间的界面处,提高了N型区与沟道区域的界面处的P型杂质浓度,增加了PN结势垒高度,电子需要从一N型区域跨过该势垒才能够到达另一N型区,进而减小器件的源漏极漏电,缓解了穿通(Punch)现象,提高器件耐压。
在完成离子注入步骤后,还需要执行步骤:去除光刻掩膜层,并进行相应的热处理过程。通过炉管进行适当的热处理,可以使得P型杂质扩散至沟道区域边界,提高该区域杂质浓度且不会影响沟道尺寸。
S150,在形成的器件表面形成栅氧化层以及多晶硅栅完成器件的制备。
在进行离子注入后,在器件的表面形成栅氧化层以及多晶硅栅,并执行相应的后续工序完成器件的制备过程。图4为根据上述制备方法获得的平板型ROM器件的结构示意图。栅氧化层212形成于器件的表面,多晶硅栅216则形成于栅氧化层212的表面。
上述平板型ROM器件的制备方法,利用同一光刻掩膜层进行P型区和N型区的注入,从而在器件中的N型区与P阱的界面处形成浓度高于P阱的P型区,提高了N型区与沟道区域的界面处的P型杂质浓度,增加了PN结势垒高度,进而减小了器件的源漏极漏电,缓解了穿通现象,提高了器件耐压。制备过程中由于N型区和P型区的制备是利用同一光刻掩膜层来进行制备的,因此无需增加额外的隔离掩膜版就可以有效提高器件的耐击穿特性,节省了生产成本。通过对注入的P型离子的注入剂量的控制可以实现对器件耐压的调节。在本实施例中,注入的P型离子的注入剂量为7×1012~3×1013㎝-2,其耐压可以提高5~8V。
在本实施例中,通过对P型区的离子注入剂量的控制可以实现对该区域掺杂浓度的控制,进而实现对器件耐压能力以及防穿通能力的调整。图5为上述方法制备得到的平板型ROM器件的N型区/沟道边界杂质分布曲线,其横坐标表示离子的注入深度,单位为微米(μm);纵坐标则表示注入区域中注入离子的掺杂浓度(doping concentration)。在本实施例中,以离子注入表面为“0”起点,并以离子注入方向为正。例如图中0.05微米处表示沿离子注入方向上距离离子注入表面0.05微米的深度。通过增加P型杂质的注入剂量(dose),沟道区域杂质浓度提升,从而使得器件的耐压能力提升。图6为的平板型ROM器件的电流-电压特性曲线,其横坐标表示源-漏电压Vds,单位为伏特(V);纵坐标表示漏极电流Id,单位为安(A)。从图中可以看出,相同的漏极电流Id,注入的离子剂量越大,其源-漏电压越大,即P型区的注入剂量对器件的耐压影响较大,从而很好的说明了本方法制备得到的器件具有较好的防穿通能力。
以上所述实施例的各技术特征可以进行任意的组合,为使描述简洁,未对上述实施例中的各个技术特征所有可能的组合都进行描述,然而,只要这些技术特征的组合不存在矛盾,都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (8)
1.一种平板型ROM器件的制备方法,包括以下步骤:
提供衬底,在所述衬底上形成P阱;
在所述P阱上形成光刻掩膜层并进行光刻形成注入窗口;
利用所述光刻掩膜层在形成的注入窗口进行P型离子的注入形成P型区;
利用所述光刻掩膜层在形成的注入窗口进行N型离子的注入从而在所述P型区上形成N型区;所述N型区包括第一N型区和第二N型区;所述第一N型区和所述第二N型区分别作为所述平板型ROM器件的源极、漏极;
在形成的器件表面形成栅氧化层以及多晶硅栅完成器件的制备。
2.根据权利要求1所述的平板型ROM器件的制备方法,其特征在于,利用所述光刻掩膜层在形成的注入窗口区进行P型离子的注入形成P型区的步骤中P型离子为倾斜注入。
3.根据权利要求2所述的平板型ROM器件的制备方法,其特征在于,所述P型离子是与竖直平面呈20~30度的角度进行注入的。
4.根据权利要求1所述的平板型ROM器件的制备方法,其特征在于,利用所述光刻掩膜层在形成的注入窗口区进行P型离子的注入形成P型区的步骤中,注入的P型离子的剂量为7×1012~3×1013㎝-2。
5.根据权利要求1所述的平板型ROM器件的制备方法,其特征在于,利用所述光刻掩膜层在形成的注入窗口进行N型离子的注入从而在所述P型区上形成N型区的步骤之后还包括步骤:进行热处理。
6.根据权利要求1所述的平板型ROM器件的制备方法,其特征在于,所述P型离子为硼、铟和二氟化硼中的一种。
7.根据权利要求1所述的平板型ROM器件的制备方法,其特征在于,所述N型离子为砷、磷和锑中的一种。
8.根据权利要求1所述的平板型ROM器件的制备方法,其特征在于,所述P型离子为硼,所述N型离子为砷。
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US15/547,278 US20180006043A1 (en) | 2015-01-29 | 2015-09-23 | Preparation method for flat cell rom device |
PCT/CN2015/090375 WO2016119477A1 (zh) | 2015-01-29 | 2015-09-23 | 平板型rom器件的制备方法 |
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US6077746A (en) * | 1999-08-26 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Using p-type halo implant as ROM cell isolation in flat-cell mask ROM process |
CN1467827A (zh) * | 2002-12-27 | 2004-01-14 | ��о���ʼ��ɵ�·���죨�Ϻ������� | 改良型掩膜式只读存储器工艺与元件 |
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JPH11163167A (ja) * | 1997-11-21 | 1999-06-18 | Seiko Epson Corp | 半導体装置の製造方法 |
US7049188B2 (en) * | 2002-11-26 | 2006-05-23 | Advanced Micro Devices, Inc. | Lateral doped channel |
US6958272B2 (en) * | 2004-01-12 | 2005-10-25 | Advanced Micro Devices, Inc. | Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell |
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US5911106A (en) * | 1996-08-29 | 1999-06-08 | Nec Corporation | Semiconductor memory device and fabrication thereof |
US20010011755A1 (en) * | 1996-08-29 | 2001-08-09 | Kazuhiro Tasaka | Semiconductor memory device and fabrication thereof |
US6077746A (en) * | 1999-08-26 | 2000-06-20 | Taiwan Semiconductor Manufacturing Company | Using p-type halo implant as ROM cell isolation in flat-cell mask ROM process |
CN1467827A (zh) * | 2002-12-27 | 2004-01-14 | ��о���ʼ��ɵ�·���죨�Ϻ������� | 改良型掩膜式只读存储器工艺与元件 |
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