CN105931996A - 具有多层基底的半导体封装 - Google Patents

具有多层基底的半导体封装 Download PDF

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Publication number
CN105931996A
CN105931996A CN201610086287.3A CN201610086287A CN105931996A CN 105931996 A CN105931996 A CN 105931996A CN 201610086287 A CN201610086287 A CN 201610086287A CN 105931996 A CN105931996 A CN 105931996A
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cte
semiconductor
conductive substrates
semiconductor die
encapsulation
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CN105931996B (zh
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熊顺和
G·马隆尼
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Infineon Technologies Americas Corp
Infineon Technologies North America Corp
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Infineon Technologies North America Corp
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Abstract

提供了具有多层基底的半导体封装。一种用于安装到印刷电路板(PCB)的半导体封装包括陶瓷外壳中的半导体裸片、在导电基底的顶表面处耦合到半导体裸片的导电基底，其中，导电基底包括具有第一热膨胀系数(CTE)的第一层和具有至少一个安装片和第二CTE的第二层。导电基底被配置为减少陶瓷外壳中的热应力，其中，第一CTE与陶瓷外壳的CTE相同或稍有不同，第二CTE大于第一CTE，并且PCB的CTE大于或等于第二CTE。导电基底被配置为将半导体裸片的功率电极电气耦合到PCB。

Description

具有多层基底的半导体封装
相关申请的交叉引用
本申请要求2015年2月26日提交的标题为“Ceramic Package withComposite Base”序列号为62/121,364的临时专利申请的权益和优先权。该临时申请中的公开由此通过引用合完全合并到本申请中。
背景技术
表面安装器件(SMD)封装可以用于容纳半导体器件并且将其直接连接到印刷电路板(PCB)。由于表面安装期间可以提供的各种益处而导致大量电子电路设计已经集成了SMD封装。例如，在高可靠性是必要的军事和空间应用(例如，高性能车辆、飞机、航天飞机和卫星)中，陶瓷SMD封装可以提供在极端或者恶劣环境下所需要的稳定性，同时提供诸如更小的尺寸、更轻的重量和优异的散热性能的益处。
然而，陶瓷SMD封装的普及已经由于SMD封装和PCB材料的热膨胀系数(CTE)不兼容，并且由于越来越宽的工作温度要求而多少被影响。例如，当陶瓷SMD封装被安装到具有大的CTE的PCB时，在陶瓷SMD封装和PCB之间的CTE失配可能对陶瓷SMD封装引入热应力。热应力可能产生陶瓷SMD封装的破裂，这可能导致封装的密闭性损失以及对封装内的功率半导体器件和电路的损坏。
因此，需要通过提供可以基本上减少由于热循环而导致的半导体封装的疲劳和破裂的诸如陶瓷SMD封装的半导体封装来克服现有技术中的缺点和不足。
发明内容
本公开针对一种具有多层基底的半导体封装，基本上如附图中的至少一个所示和/或结合其描述的，并且如权利要求书中所阐述的。
附图说明
图1A图示了根据本申请的一个实施方式的示例性半导体封装的一部分的立体图。
图1B图示了根据本申请的一个实施方式的示例性半导体封装的横截面图。
图2A图示了根根据本申请的一个实施方式的示例性半导体封装的一部分的顶部平面图。
图2B图示了根据本申请的一个实施方式的示例性半导体封装的横截面图。
图3A图示了根据本申请的一个实施方式的示例性半导体封装的一部分的顶部平面图。
图3B图示了根据本申请的一个实施方式的示例性半导体封装的横截面图。
具体实施方式
以下描述包含属于本公开中的实施方式的特定信息。本申请中的附图及其详细描述仅针对示例性实施方式。除非另有说明，附图中的相同或相应的元件可以由相同或相应的附图标记来指示。此外，本申请中的附图和说明一般不是按比例的，并且不旨在对应于实际的相关尺寸。
参考图1A和图1B，图1A图示了根据本申请的一个实施方式的示例性半导体封装100的一部分的立体图。图1B图示了根据本申请的一个实施方式的图1A中的示例性半导体封装100沿线B-B的横截面图。如图1A中所示，半导体封装100被安装在衬底102上。半导体封装100包括陶瓷外壳104、导电基底106、密封环108、盖110、孔眼或者垫圈112a和112b以及引线114a和114b。如图1B中所示，半导体封装100还包括半导体裸片118，其贯穿半导体封装100的陶瓷外壳104的底部处的孔通过焊剂附连到例如导电基底106的顶表面116。
在本实施方式中，半导体封装100是密封表面安装器件(SMD)封装。例如，半导体裸片118被密闭地密封在陶瓷外壳104中，使得半导体封装100是不透湿气和有害气体种类。例如，陶瓷外壳104可以包括相对低质量密度的陶瓷材料，诸如氧化铝或氮化铝。在实施方式中，陶瓷外壳104可以具有4至7每摄氏度每百万份(ppm/℃)范围的CTE。密封环108和盖110可以包括相对高质量密度的材料，诸如科伐合金(Kovar)。在实施方式中，密封环108和盖110中的每一个可以具有5至6ppm CTE/℃范围的CTE。如在图1A中所示，孔眼或垫圈112a和112b被形成在陶瓷外壳104的侧壁上，其中，引线114a和114b分别贯穿孔眼或垫圈112a和112b延伸到陶瓷外壳104中。引线114a和114b可以通过例如一个或多个接合线(例如，接合线120a)被电气地耦合到半导体封装100内的半导体裸片118(图1B中所示)上的一个或多个电极。在实施方式中，孔眼或垫圈112a和112b可以包括陶瓷材料，诸如氧化铝。在实施方式中，孔眼或垫圈112a和112b可以包括导电材料，诸如铜、铜合金等。在实施方式中，引线114a和114b可以包括铜、铜合金等。
应当理解，在陶瓷外壳104中具有半导体裸片118、接合线120a的半导体封装100可以诸如通过注塑成型而被包封在模制料(在图1A和图1B中未明确示出)中。还应当理解，其他电路组件和/或半导体封装(在图1A和图1B未明确示出)可以在衬底102中和/或其上形成。在实施方式中，衬底102可以是具有一个或多个层的印刷电路板(PCB)。而且，衬底102可以包括用于电气连接衬底102中或上的各种其他电路组件和/或半导体封装的导电迹线(在图1A和图1B中未明确示出)。
如图1B所示，半导体裸片118贯穿半导体封装100的陶瓷外壳104的底部的孔在导电基底106的顶表面116上形成。在实施方式中，半导体裸片118包括一个或多个半导体器件(图1B未明确示出)。在实施方式中，半导体裸片118包括IV族半导体材料，诸如硅、碳化硅(SiC)等。在另一实施方式中，半导体裸片118可以包括III-V族半导体材料，诸如氮化镓(GaN)、氮化铝镓(AlGaN)等。在其他实施方式中，半导体裸片118可以包括任何其他适当的半导体材料。而且，半导体裸片118可以包括横向和/或垂直导电功率半导体器件，诸如金属氧化物半导体场效应晶体管(FET)、绝缘栅双极晶体管(IGBT)、功率二极管等。在实施方式中，半导体裸片可以包括一个或多个III-V族功率半导体功率器件或IV族功率半导体器件。
如图1B中所示，引线114a贯穿孔眼或垫圈112a延伸到陶瓷外壳104中，并且通过接合线120a电气耦合到半导体裸片118。应当理解，与引线114a类似，图1A中所示的引线114b还可以贯穿孔眼或垫圈112b(在图1A中示出)延伸到陶瓷外壳104中，并且可以通过另一接合线(在图1A和图1B中未明确示出)电气耦合到半导体裸片118。在本实施方式中，引线114a可以被耦合到半导体封装100中的顶表面半导体裸片118上的控制电极(例如，栅电极)，而引线114b可以被耦合到半导体裸片118的顶表面上的功率电极(例如，源电极)。而且，半导体裸片118可以在半导体裸片118的底表面上具有功率电极(例如，漏电极)。导电基底106的端子焊盘106a被机械和电气地耦合到半导体裸片118的底表面上的功率电极(例如，漏电极)。安装片106b中被机械和电气地耦合到衬底102。端子焊盘106a和安装片106b可以通过焊接、铜焊或任何其他工艺来被接合在一起。这样，导电基底106贯穿陶瓷外壳104的底部处的孔将半导体裸片118电气地耦合到衬底102。
在本实施方式中，导电基底106是具有至少两个导电材料层的多层基底。如图1A和图1B中所示，导电基底106包括第一层，该第一层具有机械和电气地耦合到半导体封装100内的半导体裸片118的底表面上的功率电极(例如，漏电极)的端子焊盘106a。根据本申请的实施方式，重要的是使端子焊盘106a具有与陶瓷外壳104的CTE紧密匹配的CTE。在实施方式中，端子焊盘106a可以具有等于陶瓷外壳104的CTE的CTE。在另一实施方式中，端子焊盘106a可以具有与陶瓷外壳104的CTE稍有不同(例如，大于或小于)的CTE。例如，端子焊盘106a可以具有在4至8ppm/℃的范围中的CTE。因为端子焊盘106a的CTE与陶瓷外壳104的CTE紧密匹配，所以端子焊盘106a被配置为基本上减少和/或最小化由于热循环而导致的在陶瓷外壳104上的机械和热应力，由此提高半导体封装100的结构完整性。在本实施方式、实施方式中，端子焊盘106a可以具有铜钨(CuW)的基本上均匀的组合物。在另一实施方式中，端子焊盘106a可以具有任何金属或非金属导电材料的基本上均匀的组合物，诸如科伐合金或铜-钼(CuMo)。
如图1A和图1B中所示，导电基底106还包括第二层，具有在端子焊盘106a下方形成并且被配置为将端子焊盘106a电气耦合到衬底102的安装片106b。这样，具有端子焊盘106a和安装片106b的导电基底106被配置为贯穿陶瓷外壳104的底部的孔将半导体裸片118的功率电极电气耦合到衬底102中和/或其上的一个或多个导电迹线(在图1A和图1B未明确示出)。根据本申请的实施方式，重要的是使安装片106b具有在端子焊盘106a的CTE和衬底102的CTE之间的CTE。在一个实施方式中，安装片106b的CTE可以大于或等于端子焊盘106a的CTE，并且小于或等于衬底102的CTE。例如，在衬底102是具有13至18ppm/℃的范围中的CTE的PCB(例如，具有13至14ppm/℃的CTE的FR4PCB或具有17至18ppm/℃的CTE的聚酰胺PCB)，并且半导体封装100的陶瓷外壳104是具有4至7ppm/℃的范围中的CTE的陶瓷外壳(例如，具有大约7ppm/℃的CTE的氧化铝外壳)的情况下，安装片106b可以具有7至13ppm/℃的范围中(诸如10ppm/℃)的CTE，以提供用于缓和由于在陶瓷外壳104和衬底102之间的CTE失配而产生的热应力的缓冲步骤。在另一实施方式中，安装片106b的CTE可以小于或等于端子焊盘106a的CTE，并且大于或等于衬底102的CTE。例如，在衬底102是具有比陶瓷外壳104的CTE稍小的CTE的陶瓷PCB的情况下，安装片106b可以具有在陶瓷外壳104的CTE和陶瓷PCB的CTE之间的(例如，约7ppm/℃)的CTE。因此，通过对用于安装片106b的材料的仔细选择，本申请的实施方式可以有效地减少由于在半导体封装100和由任何材料制成的衬底102之间的CTE失配而产生的机械和热应力。这样，具有安装片106b的半导体封装100可以被表面安装在所有类型的PCB上。
因为安装片106b的CTE在端子焊盘106a的CTE和衬底102的CTE之间，所以安装片106b被配置为用作缓冲层，以基本上减少和/或最小化由于在陶瓷外壳104和衬底102之间的CTE失配产生的机械和热应用，由此改善半导体封装100的结构完整性并且防止陶瓷外壳104破裂。在本实施方式中，安装片106b可以具有铜-钼(CuMo)的基本上均匀的组合物。在另一实施方式中，安装片106b可以具有任何金属或非金属导电材料的基本上均匀的组合物，其具有在陶瓷外壳104和诸如铜-钼的衬底102的那些之间的CTE。
因此，具有与陶瓷外壳104的CTE紧密配合的CTE的端子焊盘106a以及具有在陶瓷外壳104和衬底102的CTE之间的CTE的安装片106b的导电基底106可以提供在CTE半导体封装100和衬底102之间的CTE的逐渐改变，使得从在半导体封装100和衬底102之间的CTE失配产生的机械和热应力可以基本上被减少和/或最小化。
如图1A和图1B所示，安装片106b没有在x方向和y方向上延伸到端子焊盘106a的边缘。本申请的发明人已经发现了，在陶瓷外壳104和衬底102之间的CTE失配需要特定量的长度(例如，在x方向上)和特定量的宽度(例如，在y方向上)来建立机械和热应力。因此，x方向和y方向上的安装片106b的尺寸的减小可以显著减少在陶瓷外壳104上的平面内(例如，x-y平面)的机械和热应力的量。还可以减少在安装片106b和衬底102之间的焊接点处的机械和热应力。另外，导电基底106的安装片106b可以提供在半导体封装100和衬底102之间的大的间隙，这使得在将半导体封装100焊接到衬底102之后移除焊剂残渣更容易。
参考图2A和图2B，图2A图示了根据本申请的一个实施方式的示例性半导体封装200的一部分的顶部平面图。图2B图示了根据本申请的一个实施方式的图2A中的示例性半导体封装200沿线B-B的横截面图。如图2A所示，用表示图1A和图1B中的半导体封装100中的类似特征的类似附图标记，半导体封装200被安装在衬底202上，诸如PCB。半导体封装200包括陶瓷外壳204、导电基底206、密封环208、盖210、孔眼或者垫圈212a和212b、引线214a和214b、接合线220a、220b和220c以及半导体裸片218。注意，为了清楚起见，在图2A中省略了半导体封装200的密封环208和盖210，但是可能以其他方式被包括，如图2B所示。
如图2A和图2B中所示，半导体封装200、半导体裸片218例如通过焊剂贯穿陶瓷外壳204的底部的孔被附连到导电基底206的顶表面216。在实施方式中，半导体裸片218包括一个或多个半导体器件(在图2A中未明确示出)。在实施方式中，半导体裸片218包括IV族半导体材料，诸如硅、碳化硅(SiC)等。在另一实施方式中，半导体裸片218可以包括III-V族半导体材料，诸如氮化镓(GaN)、氮化铝镓(AlGaN)等。在其他实施方式中，半导体裸片218可以包括任何其他适当的半导体材料。而且，半导体裸片218可以包括横向和/或垂直导电功率半导体器件，诸如金属氧化物半导体场效应晶体管(FET)、绝缘栅双极晶体管(IGBT)、功率二极管等。
如图2A中所示，引线214a贯穿孔眼或垫圈212a延伸到陶瓷外壳204中，并且通过接合线220a电气耦合到半导体裸片218。引线214b贯穿孔眼或垫圈212b延伸到陶瓷外壳204中，并且通过接合线220b和220c电气耦合到半导体裸片218。在本实施方式中，引线214a可以被耦合到半导体封装200中的顶表面半导体裸片218上的控制电极(例如，栅电极)，而引线214b可以被耦合到半导体裸片218的顶表面上的功率电极(例如，源电极)。而且，半导体裸片218可以在半导体裸片218的底表面上具有功率电极(例如，漏电极)。导电基底206的端子焊盘206a被机械和电气地耦合到半导体裸片218的底表面上的功率电极(例如，漏电极)。安装片206b被机械和电气地耦合到衬底202。端子焊盘206a和安装片206b可以通过焊接、铜焊或任何其他工艺来被接合在一起。这样，导电基底206贯穿陶瓷外壳204的底部处的孔将半导体裸片218电气地耦合到衬底202。
在本实施方式中，导电基底206是具有至少两个导电材料层的多层基底。如图2A和图2B中所示，导电基底206包括第一层，该第一层具有机械和电气地耦合到半导体封装200内的半导体裸片218的底表面上的功率电极(例如，漏电极)的端子焊盘206a。根据本申请的实施方式，重要的是使端子焊盘206a具有与陶瓷外壳204的CTE紧密匹配的CTE。在实施方式中，端子焊盘206a可以具有等于陶瓷外壳204的CTE的CTE。在另一实施方式中，端子焊盘206a可以具有与陶瓷外壳204的CTE稍有不同(例如，大于或小于)的CTE。例如，端子焊盘206a可以具有在4至8ppm/℃的范围中的CTE。因为端子焊盘206a的CTE与陶瓷外壳204的CTE紧密匹配，所以端子焊盘206a被配置为基本上减少和/或最小化由于热循环而导致的在陶瓷外壳204上的机械和热应力，由此提高半导体封装200的结构完整性。在本实施方式、实施中，端子焊盘206a可以具有铜钨(CuW)的基本上均匀的组合物。在另一实施方式中，端子焊盘206a可以具有任何金属或非金属导电材料的基本上均匀的组合物，诸如科伐合金或铜-钼(CuMo)。
如图2A和图2B中所示，导电基底206还包括第二层，具有在端子焊盘206a下方形成并且被配置为将端子焊盘206a电气耦合到衬底202的安装片206b。这样，具有端子焊盘206a和安装片206b的导电基底206被配置为贯穿陶瓷外壳204的底部的孔将半导体裸片218的功率电极电气耦合到衬底202中和/或其上的一个或多个导电迹线(在图2A和图2B未明确示出)。根据本申请的实施方式，重要的是使安装片206b具有在端子焊盘206a的CTE和衬底202的CTE之间的CTE。在一个实施方式中，安装片206b的CTE可以大于或等于端子焊盘206a的CTE，并且小于或等于衬底202的CTE。例如，在衬底202是具有13至18ppm/℃的范围中的CTE的PCB(例如，具有13至14ppm/℃的CTE的FR4PCB或具有17至18ppm/℃的CTE的聚酰胺PCB)，并且半导体封装200的陶瓷外壳204是具有4至7ppm/℃的范围中的CTE的陶瓷外壳(例如，具有大约7ppm/℃的CTE的氧化铝外壳)的情况下，安装片206b可以具有7至13ppm/℃的范围中(诸如10ppm/℃)的CTE，以提供用于缓和由于在陶瓷外壳204和衬底202之间的CTE失配而产生的热应力的缓冲步骤。在另一实施方式中，安装片206b的CTE可以小于或等于端子焊盘206a的CTE，并且大于或等于衬底202的CTE。例如，在衬底202是具有比陶瓷外壳204的CTE稍小的CTE的陶瓷PCB的情况下，安装片206b可以具有在陶瓷外壳204的CTE和陶瓷PCB的CTE之间的(例如，约7ppm/℃)的CTE。因此，通过对用于安装片206b的材料的仔细选择，本申请的实施方式可以有效地减少由于在半导体封装200和由任何材料制成的衬底202之间的CTE失配而产生的机械和热应力。这样，具有安装片206b的半导体封装200可以被表面安装在所有类型的PCB上。
因为安装片206b的CTE在端子焊盘206a的CTE和衬底202的CTE之间，所以安装片206b被配置为用作缓冲层，以基本上减少和/或最小化由于在陶瓷外壳204和衬底202之间的CTE失配产生的机械和热应用，由此改善半导体封装200的结构完整性并且防止陶瓷外壳204破裂。在本实施方式中，安装片206b可以具有铜-钼(CuMo)的基本上均匀的组合物。在另一实施方式中，安装片206b可以具有任何金属或非金属导电材料的基本上均匀的组合物，其具有在陶瓷外壳204和诸如铜-钼的衬底202的那些之间的CTE。
因此，具有与陶瓷外壳204的CTE紧密配合的CTE的端子焊盘206a以及具有在陶瓷外壳204和衬底202的CTE之间的CTE的安装片206b的导电基底206可以提供在CTE半导体封装200和衬底202之间的CTE的逐渐改变，使得从在半导体封装200和衬底202之间的CTE失配产生的机械和热应力可以基本上被减少和/或最小化。
如图2A和图2B所示，安装片206b和端子焊盘206a在x方向上具有相同的长度。然而，在本实施方式中，安装片206b没有在y方向上延伸到端子焊盘206a的边缘。因此，在y方向上的安装片206b的尺寸的减小可以显著减少在陶瓷外壳204上的平面(例如，x-y平面)内机械和热应力的量。还可以减少在安装片206b和衬底202之间的焊接点处的热和机械应力。此外，导电基底206的安装片206b还可以提供在半导体封装200和衬底202之间的大的间隙，这使得在将半导体封装200焊接到衬底202之后移除焊剂残渣更容易。在一个实施方式中，安装片206b和端子焊盘206a可以具有相同的长度(例如，在x方向)和相同的宽度(例如，在y方向上)。
参考图3A和图3B，图3A图示了根据本申请的一个实施方式的示例性半导体封装300的一部分的俯视图。图3B图示了根据本申请的一个实施方式的图3A中的示例性半导体封装300沿线B-B的横截面图。如图3A所示，用表示图1A和图1B中的半导体封装100中的类似特征的类似附图标记，半导体封装300被安装在衬底302上，诸如PCB。半导体封装300包括陶瓷外壳304、导电基底306、密封环308、盖310、孔眼或者垫圈312a和312b、引线314a和314b、接合线320a、320b和320c以及半导体裸片318。注意，为了清楚起见，在图3A中省略了半导体封装300的密封环308和盖310，但是可能以其他方式被包括，如图3B所示。
如图3A和图3B中所示，半导体封装300、半导体裸片318例如通过焊剂贯穿陶瓷外壳304的底部的孔被附连到导电基底206的顶表面316。在实施方式中，半导体裸片318包括一个或多个半导体器件(在图3A中未明确示出)。在实施方式中，半导体裸片318包括IV族半导体材料，诸如硅、碳化硅(SiC)等。在另一实施方式中，半导体裸片318可以包括III-V族半导体材料，诸如氮化镓(GaN)、氮化铝镓(AlGaN)等。在其他实施方式中，半导体裸片318可以包括任何其他适当的半导体材料。而且，半导体裸片318可以包括横向和/或垂直导电功率半导体器件，诸如金属氧化物半导体场效应晶体管(FET)、绝缘栅双极晶体管(IGBT)、功率二极管等。
如图3A中所示，引线314a贯穿孔眼或垫圈312a延伸到陶瓷外壳304中，并且通过接合线320a电气耦合到半导体裸片318。引线314b贯穿孔眼或垫圈312b延伸到陶瓷外壳304中，并且通过接合线320b和320c电气耦合到半导体裸片318。在本实施方式中，引线314a可以被耦合到半导体封装300中的顶表面半导体裸片318上的控制电极(例如，栅电极)，而引线314b可以被耦合到半导体裸片318的顶表面上的功率电极(例如，源电极)。而且，半导体裸片318可以在半导体裸片318的底表面上具有功率电极(例如，漏电极)。导电基底306的端子焊盘306a被机械和电气地耦合到半导体裸片318的底表面上的功率电极(例如，漏电极)。安装片306b被机械和电气地耦合到衬底302。端子焊盘306a和安装片306b可以通过焊接、铜焊或任何其他工艺来被接合在一起。这样，导电基底306贯穿陶瓷外壳304的底部处的孔将半导体裸片318电气地耦合到衬底302。
在本实施方式中，导电基底306是具有至少两个导电材料层的多层基底。如图3A和图3B中所示，导电基底306包括第一层，该第一层具有机械和电气地耦合到半导体封装300内的半导体裸片318的底表面上的功率电极(例如，漏电极)的端子焊盘306a。根据本申请的实施方式，重要的是使端子焊盘306a具有与陶瓷外壳304的CTE紧密匹配的CTE。在实施方式中，端子焊盘306a可以具有等于陶瓷外壳304的CTE的CTE。在另一实施方式中，端子焊盘306a可以具有与陶瓷外壳304的CTE稍有不同(例如，大于或小于)的CTE。例如，端子焊盘306a可以具有在4至8ppm/℃的范围中的CTE。因为端子焊盘306a的CTE与陶瓷外壳204的CTE紧密匹配，所以端子焊盘306a被配置为基本上减少和/或最小化由于热循环而导致的在陶瓷外壳304上的机械和热应力，由此提高半导体封装300的结构完整性。在本实施方式、实施中，端子焊盘306a可以具有铜钨(CuW)的基本上均匀的组合物。在另一实施方式中，端子焊盘306a可以具有任何金属或非金属导电材料的基本上均匀的组合物，诸如科伐合金或铜-钼(CuMo)。
如图3A和图3B中所示，导电基底306还包括第二层，具有在端子焊盘306a下方形成并且被配置为将端子焊盘306a电气耦合到衬底302的安装片306b。这样，具有端子焊盘306a和安装片306b的导电基底306被配置为贯穿陶瓷外壳304的底部的孔将半导体裸片318的功率电极电气耦合到衬底302中和/或其上的一个或多个导电迹线(在图3A和图3B未明确示出)。根据本申请的实施方式，重要的是使安装片306b具有在端子焊盘306a的CTE和衬底302的CTE之间的CTE。在一个实施方式中，安装片306b的CTE可以大于或等于端子焊盘306a的CTE，并且小于或等于衬底302的CTE。例如，在衬底302是具有13至18ppm/℃的范围中的CTE的PCB(例如，具有13至14ppm/℃的CTE的FR4PCB或具有17至18ppm/℃的CTE的聚酰胺PCB)，并且半导体封装300的陶瓷外壳304是具有4至7ppm/℃的范围中的CTE的陶瓷外壳(例如，具有大约7ppm/℃的CTE的氧化铝外壳)的情况下，安装片306b可以具有7至13ppm/℃的范围中(诸如10ppm/℃)的CTE，以提供用于缓和由于在陶瓷外壳304和衬底302之间的CTE失配而产生的热应力的缓冲步骤。在另一实施方式中，安装片306b的CTE可以小于或等于端子焊盘306a的CTE，并且大于或等于衬底302的CTE。例如，在衬底302是具有比陶瓷外壳304的CTE稍小的CTE的陶瓷PCB的情况下，安装片306b可以具有在陶瓷外壳304的CTE和陶瓷PCB的CTE之间的(例如，约7ppm/℃)的CTE。因此，通过对用于安装片306b的材料的仔细选择，本申请的实施方式可以有效地减少由于在半导体封装300和由任何材料制成的衬底302之间的CTE失配而产生的机械和热应力。这样，具有安装片306b的半导体封装300可以被表面安装在所有类型的PCB上。
因为安装片306b的CTE在端子焊盘306a的CTE和衬底302的CTE之间，所以安装片306b被配置为用作缓冲层，以基本上减少和/或最小化由于在陶瓷外壳304和衬底302之间的CTE失配产生的机械和热应用，由此改善半导体封装300的结构完整性并且防止陶瓷外壳304破裂。在本实施方式中，安装片306b可以具有铜-钼(CuMo)的基本上均匀的组合物。在另一实施方式中，安装片306b可以每个具有任何金属或非金属导电材料的基本上均匀的组合物，诸如铜-钼。
因此，具有与陶瓷外壳304的CTE紧密配合的CTE的端子焊盘306a以及具有在陶瓷外壳304和衬底302的CTE之间的CTE的安装片306b的导电基底306能够提供在CTE半导体封装300和衬底302之间的CTE的逐渐改变，使得从在半导体封装300和衬底302之间的CTE失配产生的机械和热应力可以基本上被减少和/或最小化。
如在图3A和3B所示，安装片306b中的每一个没有在x方向和y方向上延伸到端子焊盘306A的边缘。
因此，安装片306b中的每一个的尺寸在x和y方向上的减少可以显著减少陶瓷外壳304上的平面(例如，x-y平面)内的机械和热应力的量。还可以减少在安装片306b和衬底302之间的焊接点处的热和机械应力。此外，导电基底306的安装片306b还可以提供在半导体封装300和衬底302之间的大的间隙，这使得在将半导体封装300焊接到衬底302之后移除焊剂残渣更容易。应当理解，导电基底306的第二层可以具有多于两个的安装片306b。例如，在一个实施方式中，导电基底306的第二层可以具有在端子焊盘306a的每个角附近的四个安装片306b。多个安装片306b可以将平面内的机械和热应力的总量分为几个局部区域，从而减少在陶瓷外壳304上的总体机械和热应力。
从上面的描述很明显，在不脱离这些概念的范围的情况下，各种技术可以用于实施在本申请中描述的概念。此外，虽然已经通过对特定实施方式的具体参考描述了概念，但是本领域的普通技术人员将认识到，在不脱离这些概念的范围的情况下，可以进行形式和细节上的改变。这样，所描述的实施方式是作为说明性的而不是限制性的所有方面被考虑。还应当理解，本申请不限于本文描述的具体实施方式，而是在不脱离本公开的范围的情况下，许多重新布置、修改和替换是可能的。

Claims (20)

1.一种用于安装到印刷电路板(PCB)的半导体封装，所述半导体封装包括：
陶瓷外壳中的半导体裸片；
导电基底，在所述导电基底的顶表面处耦合到所述半导体裸片；
其中，所述导电基底包括具有第一热膨胀系数(CTE)的第一层以及具有至少一个安装片和第二CTE的第二层，所述导电基底被配置为减少所述陶瓷外壳中的热应力。
2.根据权利要求1所述的半导体封装，其中，所述第一CTE与所述陶瓷外壳的CTE相同或稍有不同。
3.根据权利要求1所述的半导体封装，其中，所述第二CTE大于所述第一CTE。
4.根据权利要求1所述的半导体封装，其中，所述PCB的CTE大于或等于所述第二CTE。
5.根据权利要求1所述的半导体封装，其中，所述导电基底的所述第一层包括铜-钨。
6.根据权利要求1所述的半导体封装，其中，所述导电基底的所述第二层包括铜-钼(CuMo)。
7.根据权利要求1所述的半导体封装，其中，所述导电基底被配置为将所述半导体裸片的功率电极电气耦合到所述PCB。
8.根据权利要求1所述的半导体封装，其中，所述半导体裸片被密闭地密封在所述陶瓷外壳中。
9.根据权利要求1所述的半导体封装，其中，所述半导体裸片包括III-V族功率半导体器件或IV族功率半导体器件。
10.根据权利要求1所述的半导体封装，其中，所述半导体裸片包括功率场效应晶体管、功率绝缘栅双极晶体管(IGBT)或功率二极管。
11.一种表面安装器件(SMD)封装，包括：
密闭地密封在陶瓷外壳中的半导体裸片；
导电基底，在所述导电基底的顶表面处耦合到所述半导体裸片；
其中，所述导电基底包括具有第一热膨胀系数(CTE)的第一层以及具有至少一个安装片和第二CTE的第二层，所述导电基底被配置为减少所述陶瓷外壳中的热应力。
12.根据权利要求11所述的SMD封装，其中，所述第一CTE与所述陶瓷外壳的CTE相同或稍有不同。
13.根据权利要求11所述的SMD封装，其中，所述第二CTE大于所述第一CTE。
14.根据权利要求11所述的SMD封装，其中，所述导电基底的所述第二层被安装到印刷电路板(PCB)。
15.根据权利要求14所述的SMD封装，其中，所述PCB的CTE大于或等于所述第二CTE。
16.根据权利要求11所述的SMD封装，其中，所述导电基底的所述第一层包括铜-钨。
17.根据权利要求11所述的SMD封装，其中，所述导电基底的所述第二层包括铜-钼(CuMo)。
18.根据权利要求11所述的SMD封装，其中，所述半导体裸片包括III-V族功率半导体器件或IV族功率半导体器件。
19.根据权利要求11所述的SMD封装，其中，所述半导体裸片包括功率场效应晶体管、功率绝缘栅双极晶体管(IGBT)或功率二极管。
20.根据权利要求11所述的SMD封装，其中，所述半导体裸片包括垂直导电功率半导体器件。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112864103A (zh) * 2020-12-31 2021-05-28 西安交通大学 一种可级联的大功率碳化硅器件半桥高温封装结构

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10903128B2 (en) * 2019-02-15 2021-01-26 Microsemi Corporation Hermetic package for power semiconductor
CN112216665A (zh) * 2019-07-11 2021-01-12 苏州旭创科技有限公司 一种光模块
CN112216672A (zh) * 2019-07-11 2021-01-12 苏州旭创科技有限公司 一种混合载板及其制作方法、组件和光模块
US11121048B1 (en) 2020-03-12 2021-09-14 Infineon Technologies Americas Corp. System and method for a device package
US11929310B2 (en) 2021-12-09 2024-03-12 Nxp Usa, Inc. Radio frequency packages containing substrates with coefficient of thermal expansion matched mount pads and associated fabrication methods

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1388580A (zh) * 2001-05-30 2003-01-01 株式会社萌利克 半导体器件
US20060249835A1 (en) * 2005-03-22 2006-11-09 Kyocera Corporation Package for receiving electronic parts, and electronic device and mounting structure thereof
CN101218671A (zh) * 2005-07-07 2008-07-09 株式会社丰田自动织机 散热装置及功率模块
CN103579130A (zh) * 2012-08-03 2014-02-12 三菱电机株式会社 半导体装置以及半导体装置的制造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4935086A (en) 1986-01-13 1990-06-19 Raytheon Company Process of bonding an electrical device package to a mounting surface
JPH02146748A (ja) 1988-11-28 1990-06-05 Nec Corp 半導体容器
EP0482812B1 (en) 1990-10-26 1998-01-07 Sumitomo Electric Industries, Ltd. Method for manufacturing semiconductor-mounting heat-radiative substrates and semiconductor package using the same
US6056186A (en) 1996-06-25 2000-05-02 Brush Wellman Inc. Method for bonding a ceramic to a metal with a copper-containing shim
US6399892B1 (en) 2000-09-19 2002-06-04 International Business Machines Corporation CTE compensated chip interposer
US7115812B2 (en) 2003-09-05 2006-10-03 Solid State Devices, Inc. Radiation shielded semiconductor package
US7372133B2 (en) * 2005-12-01 2008-05-13 Intel Corporation Microelectronic package having a stiffening element and method of making same
WO2008013279A1 (fr) 2006-07-28 2008-01-31 Kyocera Corporation Boîtier de stockage de composant électronique et dispositif électronique
US20080083980A1 (en) 2006-10-06 2008-04-10 Advanced Chip Engineering Technology Inc. Cmos image sensor chip scale package with die receiving through-hole and method of the same
ATE532215T1 (de) 2008-02-01 2011-11-15 Imec Halbleiterkapselung und deren herstellung
US8492203B2 (en) 2011-01-21 2013-07-23 Stats Chippac, Ltd. Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers
US9538659B2 (en) 2013-08-21 2017-01-03 Nxp Usa, Inc. Solder wettable flanges and devices and systems incorporating solder wettable flanges

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1388580A (zh) * 2001-05-30 2003-01-01 株式会社萌利克 半导体器件
US20060249835A1 (en) * 2005-03-22 2006-11-09 Kyocera Corporation Package for receiving electronic parts, and electronic device and mounting structure thereof
CN101218671A (zh) * 2005-07-07 2008-07-09 株式会社丰田自动织机 散热装置及功率模块
CN103579130A (zh) * 2012-08-03 2014-02-12 三菱电机株式会社 半导体装置以及半导体装置的制造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112864103A (zh) * 2020-12-31 2021-05-28 西安交通大学 一种可级联的大功率碳化硅器件半桥高温封装结构

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