CN105874589A - 混合高k第一和高k最后替代栅极工艺 - Google Patents

混合高k第一和高k最后替代栅极工艺 Download PDF

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Publication number
CN105874589A
CN105874589A CN201480071545.XA CN201480071545A CN105874589A CN 105874589 A CN105874589 A CN 105874589A CN 201480071545 A CN201480071545 A CN 201480071545A CN 105874589 A CN105874589 A CN 105874589A
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gate
pmos
dielectric
nmos
electrolyte
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CN105874589B (zh
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H·尼米
M·梅郝特瑞
M·楠达库玛
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

集成电路被提供具有金属栅极NMOS晶体管(130)和金属栅极PMOS晶体管(132)，其中金属栅极NMOS晶体管(130)具有在高质量热生长的界面电介质(106)上的高k第一栅极电介质(108)，该金属栅极PMOS晶体管(132)具有在化学生长的界面电介质(134)上的高k最后栅极电介质(136)。工艺流程被提供用于形成具有金属栅极NMOS晶体管(130)和金属栅极PMOS晶体管(132)的集成电路，该金属栅极NMOS晶体管(130)具有在高质量热生长的界面电介质(106)上的高k第一栅极电介质(108)，该金属栅极PMOS晶体管(132)具有在化学生长的界面电介质(134)上的高k最后栅极电介质(136)。

Description

混合高k第一和高k最后替代栅极工艺
技术领域
本发明总体涉及集成电路，并且具体涉及集成电路中的替代栅极晶体管。
背景技术
随着集成电路的几何形状已经按比例缩放到越来越小的尺寸，多晶硅晶体管栅极已经用金属栅极替代，以使按比例缩放继续到较小尺寸。当电压施加于多晶硅栅极时，紧靠栅极电介质的多晶硅晶粒消耗载流子，从而增加栅极电介质的电厚度并且加剧短沟道效应。当电压施加于金属栅极时金属栅极不耗尽。
因为当金属栅极经受高温(诸如用于激活掺杂剂)时，PMOS金属栅极的功函数常常改变，所以已经开发出替代栅极工艺以避免PMOS功函数问题。在替代栅极工艺中，通常首先使用具有二氧化硅栅极电介质的多晶硅栅极以惯例方式构建晶体管。多晶硅栅极和栅极电介质然后被去除并且用高k栅极电介质和金属栅极替代。薄二氧化硅电介质在高k栅极电介质的沉积之前生长在单晶硅晶体管沟道上。因为当薄二氧化硅生长时硅化物在晶片上，所以此薄二氧化硅可生长的温度受限制。因此，薄二氧化硅电介质通常使用SC1(NH4OH+H2O2)化学生长。化学生长的二氧化硅电介质的质量可能是临界的。
发明内容
集成电路具有金属栅极NMOS晶体管和金属栅极PMOS晶体管，该金属栅极NMOS晶体管带有在高质量热生长的界面电介质上的高k第一栅极电介质，该金属栅极PMOS晶体管带有在化学生长的界面电介质上的高k最后栅极电介质。集成电路工艺形成金属栅极NMOS晶体管和金属栅极PMOS晶体管，金属栅极NMOS晶体管具有在高质量热生长的界面电介质上的高k第一栅极电介质，金属栅极PMOS晶体管具有在化学生长的界面电介质上的高k最后栅极电介质。
附图说明
图1A至图1H是以示例制造顺序的连续阶段描绘的示例集成电路的横截面。
图2A至图2E是以另一个示例制造顺序的连续阶段描绘的示例集成电路的横截面。
具体实施方式
图1H示出根据示例实施例形成的集成电路，该集成电路具有NMOS晶体管，NMOS晶体管具有包括沉积在高质量栅极电介质106上的高k第一电介质108的栅极电介质堆叠。实施例中的PMOS晶体管132具有栅极电介质堆叠，该栅极电介质堆叠包括沉积在第二栅极电介质134上的高k最后电介质136。示例工艺为NMOS晶体管130提供高质量栅极氧化物106，同时也为PMOS晶体管132提供期望功函数。另外，示例工艺提供能够独立优化NMOS晶体管的高k电介质108和PMOS晶体管的高k电介质136的柔性。NMOS晶体管上的较高质量栅极电介质可改善载流子移动性，从而改善晶体管性能，并且也可减少栅极电流，从而减少待机电流并且延长电池寿命。
图1A至图1H示出说明用于形成具有NMOS晶体管130和PMOS晶体管132的集成电路的工艺的工艺流程中的主要步骤，其中该NMOS晶体管130具有高质量栅极电介质106和高k第一栅极(first gate)电介质108，该PMOS晶体管132具有高k最后栅极(last gate)电介质134。
图1A是部分加工的具有NMOS晶体管130和PMOS晶体管132的CMOS集成电路的横截面，NMOS晶体管130具有多晶硅替代栅极114，PMOS晶体管132具有多晶硅替代栅极116。NMOS多晶硅替代栅极114和PMOS多晶硅替代栅极116被形成在高质量栅极电介质106(诸如二氧化硅或氮化二氧化硅)上。使用诸如原子层沉积(ALD)的工艺将具有厚度范围为1nm至4nm的高k第一电介质(诸如HfOx、HfSiOx、HfSiON、ZrO2、HfZrOx、AlOx和TiOx)沉积在高质量热生长的栅极电介质106上。(可选的牺牲层诸如二氧化硅可以被沉积在高k第一电介质108上，以在去除多晶硅替代栅极114期间保护该高k第一电介质108)。N型源极和漏极延伸部118以与NMOS多晶硅替代栅极114自对准而被植入。P型源极和漏极延伸部120以与PMOS多晶硅替代栅极116自对准而被植入。N型深源极和漏极扩散部124以与NMOS多晶硅替代栅极114上的侧壁115自对准而被植入。P型深源极和漏极扩散部126以与PMOS多晶硅替代栅极116上的侧壁115自对准而被植入。替代栅极电介质128被沉积在晶体管栅极114和116上方并且使用化学机械抛光(CMP)被平坦化，以暴露NMOS多晶硅替代栅极114的顶部和PMOS多晶硅替代栅极116的顶部。
高质量栅极电介质106可以是使用原位蒸汽氧化(ISSG)生长到厚度范围为0.5nm至1.5nm的并且在大于850℃的温度下的SiO2。解耦等离子体氮化(DPN)可以被用来将高质量SiO2 106的表面转换为氧氮化硅。在示例实施例中，具有0.8nm的ISSG氧化物的高质量热生长的SiO2的NMOS晶体管生长，并且使用ALD将大约1.5nm的HfOx 108被沉积在二氧化硅106上。
如图1B所示，NMOS晶体管光致抗蚀图案115被形成在NMOS晶体管130上方，以防止NMOS多晶硅替代栅极114被去除。PMOS多晶硅替代栅极116通过蚀刻被去除，以形成PMOS替代栅极晶体管沟槽。高k第一栅极电介质108和高质量栅极电介质108从PMOS替代栅极晶体管沟槽的底部被蚀刻。
参考图1C，光致抗蚀图案115被去除，并且低温栅极电介质134在PMOS晶体管132的沟道上方生长或沉积。然后沉积高k最后栅极电介质136。低温栅极电介质134可以为使用SC1湿式化学法生长的SiOx。在示例实施例中，使用SC1化学生长大约0.6nm的SiOx。高k最后电介质可以是厚度在约1nm至3nm范围内的高k电介质(诸如HfOx、HfSiOx、HfSiON、ZrO2、HFZrOx、AlOx和TiOx)。在示例实施例中，使用ALD来沉积大约1.5nm的HfOx。
如图1D所示，PMOS金属栅极材料138然后被沉积到PMOS替代栅极沟槽中并且被沉积在NMOS晶体管130上方。例如，PMOS金属栅极材料138可以包含来自由氮化钛、氮化钽、铝和铂组成的组中的一种或多种金属。在示例实施例中，PMOS金属栅极材料154为约8nm的氮化钛。
在图1E中，PMOS金属栅极光致抗蚀图案140被形成在集成电路上，以防止PMOS金属栅极材料138从PMOS晶体管132被去除。PMOS金属栅极材料138、高k最后电介质136和NMOS多晶硅替代栅极114从NMOS晶体管130被去除，从而形成NMOS替代栅极晶体管沟槽。(在去除高k最后电介质之前，可选的牺牲层若存在则可被去除。)
参考图1F，光致抗蚀图案140被去除，并且NMOS晶体管金属栅极材料142被沉积到NMOS晶体管替代栅极沟槽中。例如，NMOS金属栅极材料142可包含来自由钛、铝、钛铝合金和钨组成的组中的一种或多种金属。在示例实施例中，NMOS金属栅极材料142为约3nm的钛铝合金。
CMP被用于从如图1G所示的替代栅极电介质128的表面去除NMOS金属栅极材料142溢出和PMOS金属栅极材料138溢出。
如图1H所示，前金属介电层(PMD)144可以被沉积，并且接触插头146可穿过PMD144层并穿过替代栅极介电层128被形成，以影响深源极扩散部124与第一互连层148以及深漏极扩散部126与第一互连层148之间的电连接。通过通孔电连接的附加介电层和互连层可以被形成在第一互连层148上方以完成集成电路。
图2A至图2F示出用于在NMOS晶体管130上的高质量界面电介质106上形成高k第一栅极电介质108和在PMOS晶体管132上的化学生长的界面电介质134上形成高k最后栅极电介质134的替换实施例。在该实施例中，在图2A之前的工艺步骤与多达图1A的工艺步骤并且图1A中包括的工艺步骤相同。
如图2A所示，在图1A中描述的工艺步骤之后，多晶硅替代栅极114和116被去除。在示例实施例中，高k第一栅极电介质108是使用ALD沉积的具有在1nm至3nm范围内的厚度的HfOx，并且高质量栅极电介质106是使用ISSG在大于850℃温度下生长为在0.5nm至1.5nm范围内的厚度的二氧化硅。
在图2B中，NMOS晶体管光致抗蚀图案135被形成在具有在NMOS晶体管区域130上方的图案的集成电路上，以防止高k第一栅极电介质108和高质量栅极电介质106从NMOS晶体管130去除。对单晶硅具有高选择性的蚀刻用于从PMOS晶体管替代栅极沟槽的底部去除高k第一栅极电介质108和高质量栅极电介质106。
参考图2C，光致抗蚀图案135被去除，并且低温栅极电介质134在PMOS晶体管132替代栅极沟槽的底部中的沟道上方生长或沉积。高k最后栅极电介质136然后被沉积。在该实施例中，高k最后栅极电介质136以高选择性可从高k第一栅极电介质108被去除。栅极氧化物电介质134可以使用SC1湿式化学法生长。在示例实施例中，使用SC1化学生长大约0.6nm栅极氧化物134。高k最后栅极电介质可以为在约1nm至2nm厚的范围内的高k电介质(诸如HfOx、HfSiOx、HfSiON、ZrO2、HFZrOx、AlOx和TiOx)。在示例实施例中，高k最后栅极电介质136是使用ALD沉积的具有约40％的硅含量和在约1nm至3nm范围的厚度的HfSiON。在另一个示例实施例中，高k最后栅极电介质137是使用ALD沉积的具有在约1nm至2nm范围内的厚度的ZrO2。
如图2D所示，PMOS金属栅极材料138然后被沉积到NMOS晶体管替代栅极沟槽和PMOS晶体管替代栅极沟槽中。例如，PMOS金属栅极材料138可包含来自由氮化钛、氮化钽、铝和铂组成的组中的一种或多种金属。在示例实施例中，PMOS金属栅极材料138为约8nm的氮化钛。
在图2E中，PMOS金属栅极光致抗蚀图案140被形成在集成电路上，以防止PMOS金属栅极材料138从PMOS晶体管132被去除。PMOS金属栅极材料138和高k最后电介质136从NMOS晶体管130去除。在示例实施例中，HfSiON高k最后栅极电介质使用1000∶1的HF在约80℃的温度下从HfOx高k栅极第一电介质被蚀刻掉。可以使用该蚀刻获得约20∶1的HfSiON对HfOx或ZrO2对HfOx的蚀刻选择性。
在该示例实施例中，在图2D中描述的步骤之后的随后加工与在先前实施例的图1F至图1H中示出的步骤中描述的工艺相同。
在权利要求声明的范围内，所述实施例中的修改是可能的，并且其他实施例是可能的。

Claims (19)

1.一种集成电路，其包括：
具有第一栅极电介质堆叠的NMOS晶体管，所述第一栅极电介质堆叠包括沉积在高质量栅极电介质上的高k第一电介质，所述高质量栅极电介质在大于850℃高k第一电介质的温度下热生长；以及
具有第二栅极电介质堆叠的PMOS晶体管，所述第二栅极电介质堆叠包括沉积在化学生长的栅极电介质上的高k最后栅极电介质。
2.根据权利要求1所述的集成电路，其中所述高质量栅极电介质是使用ISSG在大于约850℃的温度下生长的具有在0.5nm至1.5nm之间的厚度的二氧化硅。
3.根据权利要求1所述的集成电路，其中所述高质量栅极电介质是具有在0.5nm至1.5nm范围内的厚度的氮化二氧化硅，其中所述二氧化硅使用ISSG在大于约850℃的温度下生长，并且其中所述二氧化硅使用解耦等离子体氮化被氮化。
4.根据权利要求1所述的集成电路，其中所述高k第一栅极电介质选自由HfOx、HfSiOx、HfSiON、ZrO2、HfZrOx、AlOx和TiOx组成的所述组，并且其中所述高k最后栅极电介质选自由HfOx、HfSiOx、HfSiON、ZrO2、HfZrOx、AlOx和TiOx组成的组。
5.根据权利要求1所述的集成电路，其中所述晶体管是NMOS晶体管，所述高k第一栅极电介质是HfO2，并且所述NMOS金属栅极材料选自由钛、铝、钛铝合金和钨组成组。
6.根据权利要求1所述的集成电路，还包括：
NMOS晶体管金属栅极，其中所述NMOS晶体管金属栅极的材料选自由钛、铝、钛铝合金和钨组成的组；以及
PMOS晶体管金属栅极，其中所述PMOS晶体管金属栅极的材料选自由氮化钛、氮化钽、铝和铂组成的组。
7.根据权利要求1所述的集成电路，还包括：
NMOS晶体管金属栅极，其中所述NMOS晶体管金属栅极的材料是具有约3nm厚度的钛铝合金；以及
PMOS晶体管金属栅极，其中所述PMOS晶体管金属栅极的材料是具有约8nm厚度的氮化钛。
8.一种形成集成电路的工艺，所述工艺包括：
提供所述集成电路的部分加工的晶片；
在至少850℃的温度下使高质量第一栅极电介质在所述部分加工的晶片上生长；
在所述高质量第一栅极电介质上沉积高k第一栅极电介质；
在所述高k第一栅极电介质上形成替代栅极NMOS晶体管的NMOS多晶硅替代栅极；
在所述高k第一栅极电介质上形成替代栅极PMOS晶体管的PMOS多晶硅替代栅极；
在所述替代栅极NMOS晶体管上方以及在所述替代栅极PMOS晶体管上方沉积替代栅极电介质；
使所述替代栅极电介质平坦化，以暴露所述PMOS多晶硅替代栅极的顶部并且暴露所述NMOS多晶硅替代栅极的顶部；
形成NMOS晶体管光致抗蚀图案，其中所述NMOS晶体管光致抗蚀图案覆盖所述NMOS多晶硅替代栅极并且暴露所述PMOS多晶硅替代栅极；
去除所述PMOS多晶硅替代栅极以形成PMOS替代栅极晶体管沟槽；
从所述PMOS替代栅极沟槽的底部去除所述高k第一栅极电介质并且去除所述高质量第一栅极电介质；
去除所述NMOS晶体管光致抗蚀图案；
在所述集成电路上形成第二栅极介电层，其中所述第二栅极电介质覆盖所述PMOS替代栅极沟槽的所述底部；
在所述集成电路上沉积高k最后栅极电介质；
在所述高k最后栅极电介质上沉积PMOS金属栅极材料；
形成PMOS晶体管光致抗蚀图案，其中所述PMOS光致抗蚀图案覆盖所述PMOS晶体管并且暴露所述NMOS晶体管区；
从所述NMOS晶体管区蚀刻所述PMOS金属栅极材料；
从所述NMOS晶体管区蚀刻所述高k最后栅极介电层；
蚀刻所述NMOS多晶硅替代栅极以形成NMOS替代栅极晶体管沟槽；
去除所述PMOS晶体管光致抗蚀图案；
在所述集成电路上沉积NMOS金属栅极材料并且将所述NMOS金属栅极材料沉积到所述NMOS替代栅极沟槽中；以及
抛光所述集成电路，以从所述前金属电介质平坦表面去除所述NMOS金属栅极材料和所述PMOS金属栅极材料，并且在所述NMOS替代栅极沟槽中形成NMOS金属栅极，并且在所述PMOS替代栅极沟槽中形成PMOS金属栅极。
9.根据权利要求8所述的工艺，其中所述高质量第一栅极电介质是具有在0.5nm至1.5nm范围内的厚度的二氧化硅，并且其中所述第二栅极电介质是利用SC1化学生长为约0.6nm的厚度的SiOx。
10.根据权利要求8所述的工艺，其中所述高k第一栅极电介质选自由HfOx、HfSiOx、HfSiON、ZrO2、HfZrOx、AlOx或TiOx组成的组，并且其中所述高k最后栅极电介质选自由HfOx、HfSiOx、HfSiON、ZrO2、HfZrOx、AlOx或TiOx组成的组。
11.根据权利要求8所述的工艺，其中所述NMOS金属栅极材料选自由钛、铝、钛铝合金和钨组成的组，并且其中所述PMOS金属栅极材料选自由氮化钛、氮化钽、铝和铂组成的组。
12.根据权利要求8所述的工艺，其中所述高质量第一栅极电介质是具有在约0.5nm至1.5nm范围内的厚度的氮化二氧化硅；所述高k第一栅极电介质是具有在约1nn至3nm范围内的厚度的HfOx；所述NMOS金属栅极材料是具有约3nm厚度的钛铝合金；所述第二栅极介电层利用SC1化学生长成具有约0.6nm的厚度；所述高k最后栅极电介质是具有在约1nm至3nm范围内的厚度的HfOx；并且所述PMOS金属栅极材料是具有在约8nm范围内的厚度的氮化钛。
13.一种形成集成电路的工艺，所述工艺包括：
提供所述集成电路的部分加工的晶片；
将高质量第一栅极电介质在至少850℃的温度下在所述部分加工的晶片上生长；
在所述高质量第一栅极电介质上沉积高k第一栅极电介质；
在所述高k第一栅极电介质上形成替代栅极NMOS晶体管的NMOS多晶硅替代栅极；
在所述高k第一栅极电介质上形成替代栅极PMOS晶体管的PMOS多晶硅替代栅极；
在所述替代栅极NMOS晶体管上方以及在所述替代栅极PMOS晶体管上方沉积替代栅极电介质；
使所述替代栅极电介质平坦化，以暴露所述PMOS多晶硅替代栅极的顶部和所述NMOS多晶硅替代栅极的顶部；
去除所述NMOS多晶硅替代栅极，从而形成NMOS替代栅极沟槽；
去除所述PMOS多晶硅替代栅极，从而形成PMOS替代栅极沟槽；
形成NMOS晶体管光致抗蚀图案，其中所述NMOS晶体管光致抗蚀图案覆盖所述NMOS替代栅极沟槽并且暴露所述PMOS替代栅极沟槽；
从所述PMOS替代栅极沟槽的底部去除所述高k第一栅极电介质并且去除所述高质量第一栅极电介质；
去除所述NMOS晶体管光致抗蚀图案；
在所述集成电路上形成第二栅极介电层，其中所述第二栅极电介质覆盖所述PMOS替代栅极沟槽的所述底部；
在所述集成电路上沉积高k最后栅极电介质；
沉积PMOS金属栅极材料；
形成PMOS晶体管光致抗蚀图案，其中所述PMOS光致抗蚀图案覆盖所述PMOS晶体管并且暴露所述NMOS晶体管区；
从所述NMOS晶体管区蚀刻所述PMOS金属栅极材料；
从所述NMOS晶体管区蚀刻所述高k最后栅极介电层；
在所述集成电路上沉积NMOS金属栅极材料并且将所述NMOS金属栅极材料沉积到所述NMOS替代栅极沟槽中；以及
抛光所述集成电路，以从所述前金属电介质平坦表面去除所述NMOS金属栅极材料和所述PMOS金属栅极材料，并且在所述NMOS替代栅极沟槽中形成NMOS金属栅极，并且在所述PMOS替代栅极沟槽中形成PMOS金属栅极。
14.根据权利要求13所述的工艺，其中所述高k第一栅极电介质是HfOx，其中所述高k最后栅极电介质是HfSiON，并且其中蚀刻所述高k最后栅极电介质包括使用1000∶1的HF在约80℃的温度下蚀刻所述高k最后栅极电介质。
15.根据权利要求13所述的工艺，其中所述高k第一栅极电介质是HfOx，其中所述高k最后栅极电介质是ZrO2，并且其中蚀刻所述高k最后栅极电介质包括使用1000∶1的HF在约80℃的温度下蚀刻所述高k最后栅极电介质。
16.根据权利要求13所述的工艺，其中所述高质量第一栅极电介质是具有在0.5nm至1.5nm范围内的厚度的二氧化硅，并且其中所述第二栅极电介质是在SC1中化学生长为约0.6nm厚度的氧化物。
17.根据权利要求13所述的工艺，其中所述高k第一栅极电介质选自由HfOx、HfSiOx、HfSiON、ZrO2、HfZrOx、AlOx或TiOx组成的组，并且其中所述高k最后栅极电介质选自由HfOx、HfSiOx、HfSiON、ZrO2、HfZrOx、AlOx或TiOx组成的组。
18.根据权利要求13所述的工艺，其中所述NMOS金属栅极材料选自由钛、铝、钛铝合金和钨组成的组，并且其中所述PMOS金属栅极材料选自由氮化钛、氮化钽、铝和铂组成的组。
19.根据权利要求13所述的工艺，其中所述高质量第一栅极电介质是具有在约0.5nm至1.5nm范围内的厚度的氮化二氧化硅；所述高k第一栅极电介质是具有在约1nm至3nm范围内的厚度的HfOx；所述NMOS金属栅极材料是具有约3nm厚度的钛铝合金；所述第二栅极介电层利用SC1化学生长成具有约0.6nm的厚度；所述高k最后栅极电介质是具有在约1nm至3nm范围内的厚度的HfSiON或ZrO2；并且所述PMOS金属栅极材料是具有在约8nm范围内的厚度的氮化钛。
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