CN105789074A - 用于制造半导体器件的方法 - Google Patents

用于制造半导体器件的方法 Download PDF

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Publication number
CN105789074A
CN105789074A CN201510918239.1A CN201510918239A CN105789074A CN 105789074 A CN105789074 A CN 105789074A CN 201510918239 A CN201510918239 A CN 201510918239A CN 105789074 A CN105789074 A CN 105789074A
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China
Prior art keywords
semiconductor chip
instrument
pressed against
semiconductor
chip
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CN201510918239.1A
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English (en)
Inventor
冲嶋和彦
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN105789074A publication Critical patent/CN105789074A/zh
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Abstract

本申请涉及用于制造半导体器件的方法。包括在将焊料材料以熔化状态涂覆在裸片焊盘上方的同时将校正工具按压在半导体芯片的主表面上并使焊料材料硬化的步骤以及从芯片释放校正工具并将芯片安装在裸片焊盘上方的步骤。校正工具包括第一部分和第二部分，第一部分具有第一表面作为沿着用于支撑裸片焊盘的支撑部件的支撑表面的表面，第二部分具有与第一表面相交的第二表面。在芯片倾斜校正工艺中，在校正工具的第一表面被按压在芯片的上表面上并且校正工具的第二部分被按压在引线框上的同时焊料材料被硬化。

Description

用于制造半导体器件的方法
相关申请的交叉引用
在此通过参考并入2015年1月9日提交的日本专利申请No.2015-003553的全部公开内容，包括说明书、附图和摘要。
技术领域
本发明涉及用于制造半导体器件的方法，更具体地涉及用于半导体器件的技术，其中半导体芯片通过焊料材料(接合材料)安装在芯片安装区域上方。
背景技术
对于将焊料材料用作裸片接合材料来键合半导体芯片的半导体器件来说，在组装工艺的裸片接合步骤中，放置引线框并以超过焊料材料的熔点的温度在高温台上加热，并且将焊料材料供给到引线框的芯片安装区域并熔化。
然后，将半导体芯片放置在熔化的焊料材料上方并向半导体芯片施加规定的裸片键合重量。释放并冷却熔化的焊料材料，从而被固化来键合半导体芯片。
例如在日本审查专利申请公开Hei6(1994)-82697、日本未审查专利申请公开No.2000-34909和日本未审查专利申请公开No.2013-197146中，公开了用于使用工具在引线框或衬底上方安装半导体芯片或半导体元件的技术。
发明内容
在组装半导体器件的上述工艺中，半导体芯片下方的焊料材料的量根据焊料材料对于引线框或半导体芯片的芯片安装区域的润湿性的波动或者焊料材料供给位置的波动或芯片安装位置的波动而变化，造成半导体芯片在其厚度方向上以倾斜的方式被安装。
如果半导体芯片以倾斜方式被安装，则出现电特性、热辐射特性、接线键合性和耐冲击性明显波动的问题，导致质量不稳定并且降低半导体器件的可靠性。
本发明的上述和其他目的和新颖特征将根据本说明书和附图中的详细描述而变得更加明显。
根据本发明的一个方面，提供了一种用于制造半导体器件的方法，包括以下步骤：(a)利用接合材料涂覆引线框的芯片安装区域；(b)将半导体芯片放置在接合材料上方；(c)在接合材料处于熔化状态的情况下将工具按压在半导体芯片上，随后使接合材料硬化；以及(d)从半导体芯片释放工具并将半导体芯片安装在芯片安装区域上方。工具包括第一部分和第二部分，第一部分具有第一表面作为沿着用于支撑芯片安装区域的支撑部件的支撑表面的表面，第二部分具有与第一表面相交的第二表面。在步骤(c)中，在工具的第一部分的第一表面被按压在半导体芯片的上表面上且工具的第二部分被按压在引线框上的同时，接合材料被硬化。
根据本发明的第二方面，提供了一种用于制造半导体器件的方法，包括以下步骤：(a)提供组件，所述组件具有通过焊料膏放置在引线框的芯片安装区域上方的半导体芯片；(b)在将工具按压在半导体芯片的上表面上的情况下使组件经过回流炉以使焊料膏熔化。其进一步包括以下步骤：(c)从回流炉中取出组件，并使焊料膏硬化；以及(d)从半导体芯片释放工具并通过焊料材料将半导体芯片安装在芯片安装区域上方。工具包括第一部分和第二部分，第一部分具有第一表面作为沿着用于支撑芯片安装区域的支撑部件的支撑表面的表面，第二部分具有与第一表面相交的第二表面。在步骤(b)中，在工具的一部分的第一表面被按压在半导体芯片的上表面上且工具的第二部分被按压在引线框上的同时，焊料膏被硬化。
根据本发明，提高了半导体器件的可靠性。
附图说明
图1是示出根据本发明第一实施例的半导体器件的结构的实例的平面图；
图2是示出通过密封部件看到的图1所示半导体器件的内部结构的平面图；
图3是示出沿着图2中的线A-A截取的截面实例的截面图；
图4是示出组装图1所示半导体器件的序列的实例的流程图；
图5是示出用于组装根据第一实施例的半导体器件的引线框的实例的平面图；
图6是示出图5所示区域A的结构实例的放大的部分平面图；
图7是示出沿着图6的线A-A截取的截面实例的部分截面图；
图8是示出在组装根据第一实施例的半导体器件的工艺中的裸片键合步骤的实例的部分平面图；
图9是示出沿着图8中的线A-A截取的截面实例的部分截面图；
图10是示出在组装根据第一实施例的半导体器件的工艺中的裸片键合步骤中使用的裸片键合件的结构实例的框图；
图11是示出组装根据第一实施例的半导体器件的工艺中的裸片键合步骤的实例的部分平面图；
图12是示出沿着图11中的线A-A截取的截面实例的部分截面图；
图13是示出组装根据第一实施例的半导体器件的工艺中的裸片键合步骤的实例的部分平面图；
图14是示出沿着图13中的线A-A截取的截面实例的部分截面图；
图15是示出组装根据第一实施例的半导体器件的工艺中的裸片键合步骤的实例的部分平面图；
图16是示出沿着图15中的线A-A截取的截面实例的部分截面图；
图17是示出通过裸片键合以倾斜方式放置的半导体芯片的比较实例的侧视图；
图18是示出在根据第一实施例的裸片键合步骤中将按压在芯片上的校正工具的实例的部分截取侧视图；
图19是示出在根据第一实施例的裸片键合步骤中将按压在芯片上的校正工具的实例的部分截取侧视图；
图20是示出在根据第一实施例的裸片键合步骤中用于将校正工具按压在芯片上的定时的实例的曲线图；
图21是与立体图组合的部分平面图，其示出了在根据第一实施例的裸片键合步骤中通过校正工具按压的区域的实例；
图22是示出在组装根据第一实施例的半导体器件的工艺中的接线键合步骤的实例的部分平面图；
图23是示出沿着图22中的线A-A截取的截面实例的部分截面图；
图24是示出组装根据第一实施例的半导体器件的工艺中的模制密封步骤的实例的部分平面图；
图25是示出沿着图24中的线A-A截取的截面实例的部分截面图；
图26是示出组装根据第一实施例的半导体器件的工艺中的单一化(线切)步骤的实例的部分平面图；
图27是示出沿着图26中的线A-A截取的截面实例的部分平面图；
图28是示出根据第一实施例的变形例的校正工具的结构的部分截取侧视图；以及
图29是与立体图组合的部分平面图，其示出了根据本发明第二实施例的通过校正工具按压的区域的实例。
具体实施方式
对于下面描述的本发明的优选实施例，基本相同或相似的元件或事物将不再重复描述，除非有必要时。
本发明的优选实施例可以根据需要或为了方便在不同的部分中或单独地进行描述，但是所描述的实施例不是相互不相关，除非另有明确指定。一个实施例整体或部分地可以是另一实施例的修改、细节或补充形式。
对于下面描述的优选实施例，当用于元件的数量信息(件数、数值、量、范围等)由特定数字表示，但不限于该特定数字，除非另有指定或者理论上限于该数字，其可以比该特定数字更大或更小。
在下面描述的优选实施例中，组成元件(包括组成步骤)不是必须是必要的，除非另有指定或理论上必要。
在下面描述的优选实施例中，表述“包括A”、“由A组成”、“具有A”或“包含A”明显不排除另一元件，除非明确指定排除另一元件。类似地，在下面描述的优选实施例中，当针对元件指定特定形式或特定关系时，应该解释为包括事实上相等或类似于特定形式或位置关系的形式或位置关系，除非另有指定或理论上限于该特定形式或位置关系。这同样适用于上述数值和范围。
接下来，将参照附图详细描述优选实施例。在示出优选实施例的所有附图中，通过类似的参考标号表示具有类似功能的组件，并且省略重复描述。为了容易理解，在平面图中可以使用剖面线。
第一实施例
图1是示出根据第一实施例的半导体器件的结构的实例的平面图；图2是示出通过密封部件看到的图1所示半导体器件的内部结构的平面图；以及图3是示出沿着图2中的线A-A截取的截面实例的截面图。
<半导体器件>
根据图1至图3所示第一实施例的半导体器件是半导体封装件5，其密封半导体芯片(也称为托盘)2并包括绝缘树脂的密封部件3和被定位在密封部件5的内部和外部的多条引线1。每条引线1均包括被密封部件3覆盖的内引线部分1a和在密封部件3外露出(突出)的外引线部分1b。每个外引线部分1b均是半导体器件的外部耦合端子(外部端子)。
在根据第一实施例的半导体封装件5中，如图1和图3所示，多个外引线部分1b从密封部件3的多个侧面3a中的彼此相对的一对侧面3a中的每个侧面突出。
如图3所示，从密封部件3的下表面3b中露出板状裸片焊盘(也称为芯片安装区域、岛、头部或垫片(tab))1c的下表面1cb，其中裸片焊盘1c通过其上表面(芯片安装表面)1ca支撑半导体芯片2。即，根据第一实施例的半导体封装件5是表面安装的半导体器件。
以下将以功率晶体管(功率器件)作为具有上述结构的半导体封装件5的实例来描述第一实施例。该功率晶体管结合半导体芯片2，在半导体芯片2中形成包括漏极(D)电极、源极(S)电极和栅极(G)电极的场效应晶体管。
因此，电极(漏极电极)形成在半导体芯片2的背表面2b上，并且半导体芯片2生成许多热量。因此，焊料材料(接合材料)6被用作裸片键合材料，并且半导体芯片2的背表面2b用作热辐射路径。换句话说，半导体芯片2通过焊料材料6安装在裸片焊盘1c上方，并且从密封部件3的下表面3b露出裸片焊盘1c的下表面1cb，使得热量通过焊料材料6从裸片焊盘1c辐射。
接下来，将详细描述半导体封装件5的结构。如图3所示，半导体封装件5包括：裸片焊盘1c，具有上表面1ca和与上表面1ca相对的下表面1cb；以及半导体芯片2，通过作为裸片键合材料的焊料材料6安装在裸片焊盘1c的上表面1ca上方。半导体芯片2具有主表面(上表面)2a、形成在主表面2a上的多个电极焊盘(键合电极、键合焊盘)2c以及与主表面2a相对的背表面2b，其中背表面2b以面对裸片焊盘1c的上表面1ca的方式位于裸片焊盘1c上方。半导体芯片2的背表面2b也是用作漏极电极的电极焊盘(键合电极、键合焊盘)2d。
如图2和图3所示，半导体芯片2的主表面2a中的电极焊盘2c通过多条接线(导电部件)4电耦合至引线1的内引线部分1a。
形成在半导体芯片2的主表面2a中的电极焊盘2c包括源极电极和栅极电极。
被形成为使得从密封部件3的下表面3b露出裸片焊盘1c的下表面1cb的密封部件3密封部分裸片焊盘1c(如图3所示，上表面1ca)、内引线部分1a、半导体芯片2和接线4。
每个外引线部分1b与内引线部分1a一体地形成。
裸片焊盘1c和引线1(包括内引线部分1a和外引线部分1b)例如由Cu合金(主要由Cu(铜)组成)制成。裸片键合材料是焊料材料6。优选地，焊料材料是例如使用锡(Sn)等的无铅(Pb)焊料。代替地，其可以是Sn-Pb焊料等。
接线4例如由Al(铝)、Cu等制成。密封部件3例如由热固性环氧树脂制成。这些部件的材料不限于上述材料。
<用于制造半导体器件的方法>
图4是示出组装图1所示半导体器件的序列的实例的流程图；图5是示出用于组装根据第一实施例的半导体器件的引线框的实例的平面图；图6是示出图5所示区域A的结构实例的放大的部分平面图；以及图7是示出沿着图6中的线A-A截取的截面实例的部分截面图。图8是示出组装根据第一实施例的半导体器件的工艺中的裸片键合步骤的实例的部分平面图，以及图9是沿着图8中的线A-A截取的截面实例的部分截面图。
接下来，将在图4所示的序列中描述用于制造半导体封装件5的方法。
首先，在图4所示的晶片背面研磨步骤中，对半导体晶片的背表面进行研磨直到半导体晶片厚度变为规定厚度。
然后，对半导体晶片进行切割以得到多个没有缺陷的半导体芯片2。
然后，如下执行裸片键合。首先，如图5所示设置具有多个器件区域(半导体器件形成区域)7a的引线框7。在以下给出的第一实施例的说明中，假设引线框7具有以矩形图案配置的多个器件区域7a。引线框7是板状框架部件，例如由主要由Cu组成的金属材料(Cu合金)制成。
在组装根据第一实施例的半导体封装件5的工艺中的后续步骤的说明中，如图6所示，将以12个器件区域7a(图5)作为典型实例。如图6和图7所示，每个器件区域7a均包括裸片焊盘1c，并且多条引线1(包括内引线部分1a和外引线部分1b)被形成在裸片焊盘1c周围。
框架区域7b形成在每个器件区域7a周围，并且用于传送或定位的多个通孔7c形成在引线框7的宽度方向上的两端处。
1.裸片键合
在制备了引线框之后，执行裸片键合(图4)。
在裸片键合步骤中，如图8和图9所示，首先在引线框7的每个器件区域7a中的裸片焊盘1c上涂覆作为接合材料(裸片键合材料)的焊料材料6。
接下来，将解释在第一实施例中使用的裸片键合器。图10是示出在组装根据第一实施例的半导体器件的工艺中的裸片键合步骤中使用的裸片键合器的结构实例的框图。
图10所示的裸片键合器9的结构如下。裸片键合器9包括：框架提供部9a，用于提供引线框7作为裸片键合的目标；晶片提供部9b，用于提供经切割的半导体晶片；以及框容纳部9c，用于容纳其上执行了裸片键合的引线框7。
裸片键合器9还包括：焊料提供部9d，用于向引线框7提供焊料材料6；焊料摊开部9e，用于在引线框7上摊开焊料材料6；裸片键合部9f，用于将半导体芯片2放置在引线框7上涂覆的焊料材料6上方；以及校正部9g，用于校正放置在焊料材料6上方的半导体芯片2的倾斜。
换句话说，在其处理区域中生成还原气氛的裸片键合器9是集成处理装置，其执行从在还原气氛中拾取来自经切割的半导体晶片的半导体芯片2到将半导体芯片2裸片键合至引线框7的裸片焊盘1c上方的处理。
首先，引线框7从框提供部9a传送至焊料提供部9d。在焊料提供部9d中，引线框7被加热到期望温度(焊料材料6熔化的温度)。然后，如图8和图9所示，焊料材料6在图5所示引线框7的每个器件区域7a中涂覆(提供)在裸片焊盘1c的上表面1ca上(例如，在传送方向B上逐行涂覆)。涂覆的焊料材料6通过裸片焊盘1c加热并熔化。
接下来，将参照图11至图16描述裸片键合步骤的不同阶段。图11是示出组装根据第一实施例的半导体器件的工艺中的裸片键合步骤的实例的部分平面图，以及图12是沿着图11中的线A-A截取的截面实例的部分截面图。图13是示出组装根据第一实施例的半导体器件的工艺中的裸片键合步骤的实例的部分平面图，以及图14是沿着图13中的线A-A截取的截面实例的部分截面图。图15是示出组装根据第一实施例的半导体器件的工艺中的裸片键合步骤的实例的部分平面图，以及图16是沿着图15中的线A-A截取的截面实例的部分截面图。
如图10至图12所示，在焊料摊开部9e中摊开熔化的焊料材料6。具体地，通过拍击件(spanker)9ea来摊开焊料材料6，使其变成类似于图3所示半导体芯片2的背表面2b的四边形(图11)。
然后，在图10所示的裸片键合部9f中，如图13和图14所示，半导体芯片2被放置在每个焊料材料6上方。更具体地，使用裸片键合头9fa，通过真空抽吸等从图10所示的晶片提供部9b中的经切割的半导体晶片拾取半导体芯片2，并且将半导体芯片2放置(安装)在裸片键合部9f中放置的引线框7的裸片焊盘1c上方的焊料材料6上方。
然后，在图10所示的校正部9g中，校正放置在焊料材料6上方的半导体芯片2的倾斜。具体地，如图15和图16所示，在焊料材料6处于熔化状态的同时，校正工具9ga按压在半导体芯片2的主表面(上表面)2a上以校正半导体芯片2的倾斜。
在根据第一实施例的裸片键合器9中，校正部9g定位在裸片键合部9f之后。因此，校正工具9ga被定位在裸片键合头9fa之后，所以可以执行校正而不需要添加新步骤且没有吞吐量(也称为指标)的下降。
接下来，将详细解释为什么会在裸片键合步骤中产生半导体芯片2以倾斜方式安装的问题。图17是示出通过裸片键合以倾斜方式安装半导体芯片的比较实例的侧视图。
如图17所示，所提供的焊料材料6通过加热的裸片焊盘1c熔化并且半导体芯片2被放置在熔化的焊料材料6上方。紧接在通过图10所示的裸片键合头9fa将半导体芯片2放置在焊料材料6上方之后，如图17所示，通过裸片键合头9fa向半导体芯片2施加给定重量C。此后，缩回裸片键合头9fa。
然后，通过裸片焊料1c的加热变化为冷却阶段。同时，半导体芯片2由于焊料润湿性的波动、焊料的量的波动等而变得倾斜。这种倾斜将引起电特性的波动、热辐射特性的波动、耐冲击性的波动(焊料厚度波动)或者半导体器件中的接线键合性的波动，从而导致半导体器件的可靠性的降低。
接下来，将对半导体芯片2在焊料材料6被用作裸片键合材料(接合材料)时容易变得倾斜的原因给出解释。这与焊料材料6的低触变性相关联。触变性是由对象(流体)显示出的以下特性：对象的流动性在向其施加力的同时较高，并且当对象被释放时，其流动性变低。由于焊料材料6的触变性较低，所以当缩回裸片键合头9fa时，焊料材料6被释放并且变得容易移动。可能这就是半导体芯片2变得倾斜的原因。
另一方面，如果裸片键合材料是银膏等，则其触变性较高，即使在其随着裸片键合头9fa缩回而释放时，其也不移动。从而，半导体芯片2难以变得倾斜。
由于上述机制，当使用焊料材料6时，半导体芯片2比使用银膏等时更容易变得倾斜。
作为该问题的解决方案，在第一实施例中，在焊料材料6处于熔化状态的同时使校正工具9ga按压在半导体芯片2的主表面(上表面)2a上，并且在校正工具9ga保持按压的情况下使焊料材料6的温度降低以使焊料材料6硬化(固化)(校正工具9ga保持按压直到温度变得低于固相温度)，从而校正半导体芯片2的倾斜。
接下来，将解释第一实施例中使用的校正工具9ga的形状。图18是示出在根据第一实施例的裸片键合步骤中被按压在芯片上的校正工具的实例的部分截面侧视图，以及图19是示出在根据第一实施例的裸片键合步骤中被按压在芯片上的校正工具的实例的部分截面侧视图。图20是示出在根据第一实施例的裸片键合步骤中将校正工具按压在芯片上的定时的实例的曲线图，以及图21是与立体图组合的部分平面图，示出了在根据第一实施例的裸片键合步骤中通过校正工具按压的区域的实例。
如图18和图19所示，校正工具9ga包括第一部分9gb和第二部分9ge，第一部分9gb具有沿着能够支撑裸片焊盘1c的支撑部件9h的支撑表面9ha的第一表面9gc，第二部分9ge具有与第一表面9gc相交的第二表面9gf。
用于支撑裸片焊盘1c的支撑部件9h例如是平台，并且支撑表面9ha是平台的上表面。可选地，支撑部件9h可以是轨道等。
校正工具9ga的第一部分9gb的第一表面9gc是几乎平行于支撑部件9h的支撑表面9ha的表面，并且还是接触半导体芯片2的主表面(上表面)2a的表面。换句话说，第一表面9gc是面对半导体芯片2的主表面(上表面)2a的表面。第二部分9ge是支撑部分，具有几乎垂直于第一表面9gc的第二表面9gf。换句话说，第一实施例中的校正工具9ga是平坦U形阻挡部件，其具有朝向图18所示的按压方向D(第一方向)的开口。
为了校正半导体芯片2的倾斜，如图19所示，校正工具9ga的第一部分9gb的第一表面9gc被按压在位于熔化的焊料材料6上方的半导体芯片2的主表面2a上。
按压方向D上的校正工具9ga的第二部分9ge的第二表面9gf的高度H应该等于半导体芯片2的厚度与组装的半导体封装件5的焊料材料6的高度的总和。
在倾斜校正工艺中，在校正工具9ga的第一表面9gc被按压在半导体芯片2的主表面2a上且校正工具9ga的两个第二部分9ge的下表面9gg被按压在引线框7上的同时，焊料材料6被硬化。
因此，即使用于倾斜校正的校正工具9ga的下降位置的精度不是太高，但由于校正工具9ga的第二部分9ge(支撑部分)与引线框7接触(被按压在引线框7上)，所以包括焊料材料6的半导体芯片2的高度可以以高精度来确定。从而，在以高精度确定半导体芯片2的主表面2a的高度(位置)之后，校正半导体芯片2的倾斜。
此外，由于两个侧面上的校正工具9ga的第二部分9ge(支撑部分)被设计为接触引线框7，所以即使引线框7由于热量而翘曲，也不会损害校正能力。
在倾斜校正工艺中，当熔化的焊料材料6的温度高于焊料材料6的固相温度时，将校正工具9ga按压在半导体芯片2上，并且将校正工具9ga保持按压在半导体芯片2上直到焊料材料6的温度变得低于固相温度，然后从半导体芯片2释放校正工具9ga。
具体地，如图20所示，当焊料材料6具有大于其固相温度(T1：固相线)的高温时开始冷却(T2：焊料材料6处于熔化状态)，并且将校正工具9ga在开始冷却之后立刻按压在半导体芯片2的主表面2a(校正开始点P1)上。这将半导体芯片2的热量传送至校正工具9ga，使得半导体芯片2的温度下降。随着半导体芯片2的温度下降，焊料材料6的温度也下降。
将校正工具9ga保持按压直到焊料材料6的温度变得低于固相温度T1，并且当温度足够低于固相温度T1且焊料材料6被硬化时(校正工具释放点P2)或在其被硬化之后，从半导体芯片2释放校正工具9ga。
换句话说，在根据第一实施例的倾斜校正工艺中，在半导体芯片2被放置在裸片焊盘1c上方涂覆的熔化的焊料材料6上方之后，在焊料材料6处于熔化状态的同时开始冷却。紧接在开始冷却之后，在稍高于固相线(固相温度)的点(P1)处，将校正工具9ga的第一部分9gb的第一表面9gc(其保持为几乎平行于支撑部件9h(平台等)的支撑表面9ha)按压在半导体芯片2的主表面2a上。
因此，通过校正工具9ga，半导体芯片2的倾斜被校正并且从半导体芯片2去除热量。从而，半导体芯片2的温度下降并且焊料材料6的温度也下降。随着焊料材料6的温度变得低于固相温度(固相线)，焊料材料6硬化。由于校正工具9ga被按压在半导体芯片2的主表面2a上直到此时，所以焊料材料6被硬化且半导体芯片2被安装而没有半导体芯片2的主表面2a的倾斜。
在焊料材料6被硬化之后，从半导体芯片2的主表面2a释放校正工具9ga(P2)。
例如，如果焊料材料6是Sn-37Pb焊料，则固相温度T1为183℃，并且在达到固相温度T1+大约5℃至20℃的温度(T2)时，开始校正，即，校正工具9ga被按压在半导体芯片2的主表面2a上。然后，校正工具9ga被保持按压近似时间Q直到焊料材料6的温度变得低于固相温度T1。从P1到P2的时间Q为几秒左右。
在根据第一实施例的倾斜校正工艺中，校正工具9ga应该通过半导体芯片2从加热的焊料材料6去除热量。因此，期望校正工具9ga设置有冷却机制。由于在每次执行校正工艺时加热校正工具9ga，所以如果校正工具9ga设置有冷却机制，则裸片键合器9可以持续操作。
在根据第一实施例的倾斜校正工艺中，校正工具9ga耦合至图18所示的用于冷却校正工具9ga的冷却单元8。例如，冷却单元8为校正工具9ga提供冷却介质来用于空气或水冷却。校正工具9ga具有使冷却介质循环的冷却机制。
在校正工艺中，如图21所示，校正工具9ga的第二部分9ge被按压在图5所示的引线框7的器件区域(半导体器件形成区域)7a的外部部分上。更具体地，校正工具9ga的第二部分9ge(支撑部分)被按压在器件区域7a的外部部分(图21中的区域E(剖面线))上。
从而，校正工具9ga不接触引线框7的产品区域，从而防止损伤引线框7的产品区域，而这种损伤可能由于校正工具9ga的接触而引起。
在校正工艺中，期望在图21所示的时间将校正工具9ga按压在多个半导体芯片2的主表面2a(图3)上。换句话说，可以通过将校正工具9ga按压在多个(例如，四个)半导体芯片2上来高效地执行校正。
当校正工具9ga一次按压在多个半导体芯片2上时，期望将校正工具9ga按压至在与引线框7的传送方向B(X方向)相交的方向(Y方向)上布置的半导体芯片2的行的主表面2a。
在图10所示的裸片键合器9中，在图21所示的用于引线框7的传送方向B(X方向)上逐行地针对半导体芯片执行一系列处理阶段(焊料提供、焊料摊开、裸片键合和倾斜校正)。如果(在每个器件区域7a中)逐芯片地校正倾斜，则在Y方向的同一行中的校正器件区域7a中的焊料材料6可能在下一器件区域7a的倾斜校正期间再次熔化。
因此，通过一次将校正工具9ga按压在Y方向(与传送方向B相交的方向)上布置的半导体芯片2的行的主表面2a上，可以有效地执行校正而不影响先前执行的校正。
在上述方法中，半导体芯片2在以矩阵图案布置的引线框7的每个器件区域7a中通过焊料材料6安装在裸片焊盘1c的上表面1ca上方，同时半导体芯片2的倾斜被校正。
图22是示出组装根据第一实施例的半导体器件的工艺中的接线键合步骤的实例的部分平面图，以及图23是沿着图22中的线A-A截取的截面实例的部分截面图。图24是示出组装根据第一实施例的半导体器件的工艺中的模制密封步骤的实例的部分平面图，以及图25是沿着图24中的线A-A截取的截面实例的部分截面图。图26是示出组装根据第一实施例的半导体器件的工艺中的单一化(线切)步骤的实例的部分平面图，以及图27是沿着图26中的线A-A截取的截面实例的部分截面图。
2.接线键合
在完成裸片键合之后，执行接线键合步骤(图4)。
在接线键合步骤中，如图22和图23所示，半导体芯片2的电极焊盘2c(图3)通过接线4电耦合至内引线部分1a(图3)。
3.组装后外观检查
在完成接线键合之后，执行组装后外观检查(图4)。在该步骤中，检查接线4是否剥离等。
4.模制密封
在完成组装后外观检查之后，执行模制密封(图4)。
在模制密封步骤中，如图24和图25所示，使用密封树脂形成密封半导体芯片2、接线4和内引线部分1a的密封部件3。
在根据第一实施例的模制密封步骤中，密封部件3被形成为使得如3所示从密封部件3的下表面3b露出裸片焊盘1c的下表面1cb。例如，密封树脂是热固性环氧树脂。
5.涂覆
在完成模制密封之后，执行涂覆(图4)。
在涂覆步骤中，在裸片焊盘1c的下表面1cb和外引线部分1b上制作诸如焊料涂层的涂覆膜。
6.做标记
在涂覆之后，执行做标记(图4)。
在标记步骤中，例如，在密封部件3的表面上制造期望的标记(戳)。例如，标记表示产品的类型或型号。通过激光照射等制作标记。
7.线切(单一化)
在做标记之后，执行线切(图4)。
在线切步骤中，通过冲压每个器件区域7a来执行单一化。具体地，如图26和图27所示，通过在每个器件区域7a的F区域中冲压(切割)来分离外引线部分1b(图2)和框架区域7b(图5)，并且每个外引线部分1b被弯曲成规定形状(在这种情况下为鸥翼形状)。
通过执行上述步骤，完成半导体封装件5的组装。
此后，如图4所示，在运送之后执行老化测试、最终外观检查和包装。
在制造根据该实施例的半导体器件(半导体封装件5)的方法中，可以在裸片键合步骤中减小半导体芯片2的倾斜，使得由芯片倾斜引起的热阻问题或导通阻抗问题减少。
更具体地，该方法减少了由倾斜方式安装的半导体芯片2引起的电特性、热辐射特性、接线键合性、半导体封装件5的耐冲击性的波动，从而有助于半导体封装件5的质量的稳定性。从而，提高了半导体封装件5的可靠性。
此外，可以减少接线键合步骤中归因于半导体芯片2的倾斜的识别错误，使得键合性(接线键合性)得到提高。
此外，校正工具9ga具有第二部分9ge作为支撑部分，并且第二部分9ge的末端(下表面9gg)在校正工艺中接触引线框7。从而，即使引线框7在裸片键合器9中加热到高温而翘曲，也可以执行倾斜校正。
当在引线框7中以矩阵图案布置器件区域时，一次校正在与引线框传送方向B相交的方向上布置的一行芯片(针对一个循环)的倾斜，使得可以有效地执行校正而不使焊料材料6再次熔化。因此，提高了制造半导体封装件5的工艺的生产率。
此外，在裸片键合器9中，在裸片键合部9f之后设置校正部9g。从而，执行倾斜校正和裸片键合，而不需要投资新装置并且不会引起吞吐量(指标)的下降。
变形例
图28是示出作为第一实施例的变形例的校正工具的结构的部分截面侧视图。
在图28所示的校正工具9ga中，在第一部分9gb的第一表面9gc中制作凹部9gd。凹部9gd是在与按压方向D相反的方向(第二方向)上凹陷的部分。在倾斜校正工艺中，校正工具9ga的除凹部9gd之外的第一表面9gc的区域(例如，凹部9gd周围的区域(第三部分))被按压在半导体芯片2的主表面2a上。
如此在校正工具9ga的第一表面9gc中制作的凹部9gd(与半导体芯片2接触)减小了校正期间校正工具9ga与半导体芯片2的主表面2a之间的接触面积，从而减小了半导体芯片2在校正期间被玷污或损伤的可能性。
然而，凹部9gd的尺寸和位置必须被确定为使得不损害通过半导体芯片2至校正工具9ga(以在校正工艺中使焊料材料6硬化)的传送热量。
如图28所示，可以提供弹簧10、弹性部件以将校正工具9ga按压在半导体芯片2上。弹簧10保持校正工具9ga在校正期间按压在半导体芯片2和引线框7上，从而防止校正工具9ga不与引线框7接触。
这消除了对校正工具9ga的下降位置的高精度的要求(例如，±1mm的位置精度是可接受的)，并且可以以高精度确定半导体芯片2的高度。
第二实施例
图29是与立体图组合的部分平面图，其示出根据第二实施例的通过校正工具按压的区域的实例。
图29示出了通过涂覆焊料膏(膏形式的焊料材料6)作为接合材料(裸片键合材料)执行校正的情况。当使用焊料膏时，不使用图10所示的裸片键合器9，而是代替使组件7d经过回流炉(回流装置)以执行半导体芯片2的焊料键合。
首先，制备组件7d，在组件7d中半导体芯片2通过焊料膏放置在引线框7的裸片焊盘1c(图19)上方。然后，如图18和图19所示第一实施例中的校正工艺那样，在校正工具11被按压在半导体芯片2的主表面2a上的同时，使组件7d经过回流炉以熔化焊料膏。然后，从回流炉中取出组件7d以使焊料膏硬化，然后从半导体芯片2释放校正工具11，并且将半导体芯片2通过硬化的焊料材料6安装在裸片焊盘1c上方。
校正工具11与第一实施例的校正工具9ga相同。因此，如图18和图19中的校正工艺那样，在校正工具11的第一部分9ga的第一表面9gc被按压在半导体芯片2的主表面2a上并且校正工具11的第二部分9ge被按压在引线框7上的同时，焊料膏被硬化。
当使用回流炉时，校正工具11可具有较大的宽度。
例如，当引线框7具有图5所示以矩阵图案布置的多个器件区域(半导体器件形成区域)7a时，将校正工具11同时按压在多行中的半导体芯片2的主表面2a上，如图29所示，每一行均包括在与引线框7的传送方向B相交的方向(Y方向)上布置的多个半导体芯片2。
从而，可以一次对多行半导体芯片2执行校正，使得校正速度(吞吐量)大大增加。
如图29所示，可以同时使用三个校正工具11a(每一个校正工具都能够每次对一行半导体芯片执行校正)，或者可以使用单个校正工具11b(其宽度足够大来覆盖X方向上的三行)，来一次对三行执行校正。
当使用能够一次对X方向上的三行执行校正的宽校正工具11b时，大大增加了校正速度。
另一方面，当每一个都能够一次对单行的半导体芯片2执行校正的三个校正工具11a用于对X方向上的三行执行校正时，工具本身的翘曲较小，因此校正精度较高。
至此参照优选实施例解释了由本发明人作出的本发明。然而，本发明不限于此，并且明显地，是可以以各种方式来修改这些细节而不背离其精神。
例如，尽管在第一实施例和第二实施例的解释中，用于固定半导体芯片2的接合材料(裸片键合材料)被假设为焊料材料6，但接合材料可以是除焊料材料6之外的接合材料，只要其特性类似于焊料材料6的特性即可。

Claims (12)

1.一种用于制造半导体器件的方法，包括以下步骤：
(a)利用接合材料涂覆引线框的芯片安装区域；
(b)在步骤(a)之后，在所述接合材料上方放置半导体芯片；
(c)在步骤(b)之后，在所述接合材料处于熔化状态的情况将工具按压在所述半导体芯片的上表面上，然后使所述接合材料硬化；以及
(d)在步骤(c)之后，从所述半导体芯片释放所述工具，并通过所述接合材料将所述半导体芯片安装在所述芯片安装区域上方；
其中，所述工具包括第一部分和第二部分，所述第一部分具有第一表面作为沿着用于支撑所述芯片安装区域的支撑部件的支撑表面的表面，所述第二部分具有与所述第一表面相交的第二表面，并且
其中，在步骤(c)中，在所述工具的所述第一部分的所述第一表面被按压在所述半导体芯片的上表面上并且所述工具的所述第二部分被按压在所述引线框上的同时，所述接合材料被硬化。
2.根据权利要求1所述的用于制造半导体器件的方法，其中，所述接合材料是焊料材料。
3.根据权利要求1所述的用于制造半导体器件的方法，其中，在步骤(c)中，将所述工具一次按压在多个所述半导体芯片的上表面上。
4.根据权利要求1所述的用于制造半导体器件的方法，
其中，在所述引线框中以矩阵图案布置多个半导体器件形成区域，并且
其中，在步骤(c)中，将所述工具一次按压至在与所述引线框的传送方向相交的方向上布置的一行中的半导体芯片的上表面上。
5.根据权利要求1所述的用于制造半导体器件的方法，
其中，在所述工具的所述第一表面中制作凹部，并且
其中，在步骤(c)中，将所述工具的所述第一表面中除所述凹部之外的区域按压在所述半导体芯片的上表面上。
6.根据权利要求1所述的用于制造半导体器件的方法，其中，按压方向上的所述工具的所述第二部分的所述第二表面的高度等于所述半导体芯片的厚度与组装所述半导体器件之后的所述接合材料的厚度的总和。
7.根据权利要求1所述的用于制造半导体器件的方法，其中，在步骤(c)中，将所述工具的所述第二部分按压在所述引线框中的半导体器件形成区域的外部部分上。
8.根据权利要求1所述的用于制造半导体器件的方法，其中，在步骤(c)中，当处于熔化状态的所述接合材料具有比所述接合材料的固相温度更高的温度时，将所述工具按压在所述半导体芯片上。
9.根据权利要求8所述的用于制造半导体器件的方法，其中，在步骤(c)中，将所述工具按压在所述半导体芯片上直到所述接合材料的温度变得低于所述固相温度，然后从所述半导体芯片释放所述工具。
10.根据权利要求1所述的用于制造半导体器件的方法，
其中，将用于冷却所述工具的冷却单元耦合至所述工具。
11.一种用于制造半导体器件的方法，包括以下步骤：
(a)提供组件，所述组件具有通过焊料膏放置在引线框的芯片安装区域上方的半导体芯片；
(b)在步骤(a)之后，在将工具按压在所述半导体芯片的上表面上的同时使所述组件经过回流炉以使所述焊料膏熔化；
(c)在步骤(b)之后，从所述回流炉中取出所述组件并使所述焊料膏硬化；以及
(d)在步骤(c)之后，从所述半导体芯片释放所述工具，并通过焊料材料将所述半导体芯片安装在所述芯片安装区域上方，
其中，所述工具包括第一部分和第二部分，所述第一部分具有第一表面作为沿着用于支撑所述芯片安装区域的支撑部件的支撑表面的表面，所述第二部分具有与所述第一表面相交的第二表面，并且
其中，在步骤(b)中，在所述工具的所述第一部分的所述第一表面被按压在所述半导体芯片的上表面上并且所述工具的所述第二部分被按压在所述引线框上的同时，所述焊料膏被硬化。
12.根据权利要求11所述的用于制造半导体器件的方法，
其中，在所述引线框中以矩阵图案布置多个半导体器件形成区域，并且
其中，在步骤(b)中，将所述工具一次按压在多行中的所述半导体芯片的上表面上，每一行都包括在与用于所述引线框的传送方向相交的方向上布置的多个半导体芯片。
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