CN105761755A - 存储器装置、电荷帮浦电路以及其电压泵激方法 - Google Patents

存储器装置、电荷帮浦电路以及其电压泵激方法 Download PDF

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CN105761755A
CN105761755A CN201610008971.XA CN201610008971A CN105761755A CN 105761755 A CN105761755 A CN 105761755A CN 201610008971 A CN201610008971 A CN 201610008971A CN 105761755 A CN105761755 A CN 105761755A
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voltage
clock signal
charge pump
output
latch
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CN105761755B (zh
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邵启意
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eMemory Technology Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H04L9/0816—Key establishment, i.e. cryptographic processes or cryptographic protocols whereby a shared secret becomes available to two or more parties, for subsequent use
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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    • H04L63/00—Network architectures or network communication protocols for network security
    • H04L63/04—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks
    • H04L63/0428—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload
    • H04L63/0457—Network architectures or network communication protocols for network security for providing a confidential data exchange among entities communicating through data packet networks wherein the data content is protected, e.g. by encrypting or encapsulating the payload wherein the sending and receiving network entities apply dynamic encryption, e.g. stream encryption
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
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    • H02M3/00—Conversion of dc power input into dc power output
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    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
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    • H03K5/151—Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors with two complementary outputs
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    • H04—ELECTRIC COMMUNICATION TECHNIQUE
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    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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    • H02M1/00—Details of apparatus for conversion
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
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    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
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    • H02M3/073—Charge pumps of the Schenkel-type
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Abstract

存储器装置、电荷帮浦电路以及其电压泵激方法。本发明提供一种存储器装置、电荷帮浦电路以及电压泵激方法。电荷帮浦电路包括多个延迟单元、锁存电路以及多个电荷帮浦单元。根据输出时钟信号，延迟单元分别产生多个时钟信号。锁存电路接收时钟信号的最后阶段时钟信号以及锁存致能信号。锁存电路决定是否锁存最后阶段时钟信号或根据锁存致能信号产生输出时钟信号。第一级的电荷帮浦单元接收一个输入电压，以及根据时钟信号以及输出时钟信号。电荷帮浦单元针对输入电压执行电压泵激操作来产生输出电压。

Description

存储器装置、电荷帮浦电路以及其电压泵激方法
技术领域
本发明涉及一种电荷帮浦电路以及一种电压泵激方法，且特别涉及一种电荷帮浦电路与电压泵激方法，用以产生一个编程电压和/或抹除电压给存储器装置。
背景技术
近年来，非易失性的存储器装置应用在电子装置中日益普及，为了在非易失性存储器装置中提供编程电压与抹除电压，在现有技术中，电荷帮浦电路在非易失性存储器装置中是必需的。
在现有技术中，电荷帮浦电路由多个电荷帮浦单元所建构，电荷帮浦单元依序针对输入电压进行升压来产生输出电压。电压帮浦单元基于各自对应的时钟信号来进行电压泵激的操作。如果已知的电荷帮浦电路不能即时的停止时钟信号，则不需要的时钟脉冲将被传递至电荷帮浦单元中，并使输出电压产生不必要的纹波。此外，当电荷帮浦电路再次被启动时，一个因电荷帮浦单元链而造成的延迟时间在重新产生输出电压的时间上是必要的，并且，在上述的延迟时间中，输出电压的降低，以及输出电压上的其他纹波都会被产生。换句话说，在现有技术中，电荷帮浦电路存在更多的纹波与峰值电流，因此降低了输出电压的效率。
发明内容
本发明提供一种电荷帮浦电路与电压泵激方法，用以产生输出电压，具有减少输出纹波与减少峰值电流的功能。
本发明也提供一种具有电荷帮浦电路的存储器装置，电荷帮浦电路被用来提供一个编程电压与抹除电压，具有减少输出纹波与减少峰值电流的功能。
本发明提供一种电荷帮浦电路，包含多个延迟单元、锁存器以及多个电荷帮浦单元。延迟单元相互串联耦接，其中延迟单元根据输出时钟信号分别地产生多个时钟信号。锁存电路耦接延迟单元，接收时钟信号中的最后一级时钟信号以及锁存致能信号，其中锁存电路决定是否根据锁存致能信号以锁存最后一级时钟信号来产生输出时钟信号。电荷帮浦单元相互串联耦接，其中第一级电荷帮浦单元接收输入电压，并且，电荷帮浦单元根据时钟信号与输出时钟信号以针对输出电压进行电压泵激操作来产生输出电压。
本发明提供一种存储器装置，包括一电荷帮浦电路。电荷帮浦电路包含多个延迟单元、锁存器以及多个电荷帮浦单元。延迟单元相互串联耦接，其中延迟单元根据输出时钟信号分别地产生多个时钟信号。锁存电路耦接延迟单元，接收时钟信号中的最后一级时钟信号以及锁存致能信号，其中锁存电路决定是否根据锁存致能信号以锁存最后一级时钟信号来产生输出时钟信号。电荷帮浦单元相互串联耦接，其中第一级电荷帮浦单元接收输入电压，并且，电荷帮浦单元根据时钟信号与输出时钟信号以针对输出电压进行电压泵激操作来产生输出电压。其中，输出电压被使用为编程电压与抹除电压中的至少其中之一。
本发明更提供一种电压泵激方法，此电压泵激方法包括：藉由依序延迟输出时钟信号以产生多个时钟信号；接收输入电压，以及根据时钟信号与输出时钟信号针对输出电压操作电压泵激操作以产生输出电压；以及，当输出电压的电压电平到达参考电压的电压电平时，则锁存时钟信号的最后一级时钟信号的电压电平以产生输出时钟信号。
根据上述描述，本发明提供一个具有锁存电路的电荷帮浦电路。在电压泵激操作被完成的时间点，根据锁存致能信号来能锁存最后一级时钟信号，如此，不需要的时钟不会被传送至电荷帮浦单元，输出电压的电压电平稳定性可以被保持，并能减少存在于电压帮浦电路中的输出纹波与峰值电流。
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合附图作详细说明如下。
附图说明
图1绘示本发明一实施例的电荷帮浦电路的示意图。
图2绘示本发明的另一实施例的电荷帮浦电路的示意图。
图3绘示本发明再一实施例的电荷帮浦电路的示意图。
图4绘示本发明再一实施例的电荷帮浦电路的示意图。
图5绘示本发明实施例说明的调整电路的示意图。
图6绘示本发明实施例的存储器装置的示意图。
图7绘示本发明实施例的电压泵激方法的流程图。
【符号说明】
100、200、300、400、620：电荷帮浦电路
111-11N、211-214、311-314、411-414：电荷帮浦单元
121-12M、221-223、321-323、421-423：延迟单元
IN1-IN5、IN9、INA-D：反相器
130、230、330、430：锁存电路
CKO：输出时钟信号
CK1-CKM：时钟信号
VOUT：输出电压
VIN：输入电压
ENPUMP：锁存致能信号
Vref：参考电压
Vfb：反馈电压
C1：电容
R1：电压
GND：参考接地端
DCK3：迟时钟信号
LAT1：锁存器
OP1：操作放大器
I1：负输入端
I2：正输入端
510：分压器
600：存储器装置
610：存储器晶胞阵列
ERS：抹除电压
PGM：编程电压
S710、S720、S730：电压泵激的步骤
具体实施方式
请参考图1，图1绘示本发明一实施例的电荷帮浦电路的示意图。电荷帮浦电路100包括电荷帮浦单元111-11N、延迟单元121-12M以及锁存电路130。延迟单元121-12M相互串联耦接，延迟单元121-12M根据一个输出时钟信号CKO以分别产生多个时钟信号CK1-CKM。电荷帮浦单元111-11N相互串联耦接。
详细说明，第一级电荷帮浦单元111接收输入电压VIN，以及针对输入电压VIN进行电压泵激操作。第一级电荷帮浦单元111传递其电压泵激结果至下一级的电荷帮浦单元112以进行另一次的电压泵激操作。在此实施例中，藉由通过电荷帮浦单元111-11N进行的电荷泵激操作，可产生具有高于输入电压VIN的电压电平的输出电压VOUT。再者，延迟单元121-12M藉由依序的延迟输出信号CKO来分别产生多个时钟信号CK1-CKM。举例说明，第一阶段延迟单元121接收输出时钟信号CKO，并延迟输出时钟信号CKO以产生时钟信号CK1。接着，延迟单元122从延迟单元121接收时钟信号CK1，并藉由延迟时钟信号CK1产生时钟信号CK2。
锁存电路130耦接最后一级延迟单元12M，且锁存电路130接收最后一级时钟信号CKM以产生输出时钟信号CKO。锁存电路130更接收锁存致能信号ENPUMP，锁存电路130根据锁存致能信号ENPUMP来决定是否锁存最后一级时钟信号CKM以产生输出时钟信号CKO。详细说明，锁存致能信号ENPUMP被用来指示电压泵激操作是否已完成。如果电压帮泵激操作尚未完成，锁存电路130可以延迟最后阶段时钟信号CKM并通过延迟最后一级时钟信号以根据锁存至能信号ENPUMP来产生输出时钟信号CKO。另一方面，如果电压泵激操作已完成，锁存电路130可根据锁存致能信号ENPUMP来锁存最后一级时钟信号CKM来产生输出时钟信号CKO，并保持输出时钟信号CKO的电压电平，如此，输出时钟信号CKO不会产生多个电压转态现象。
也就是说，输出时钟信号CKO的电压电平能在当锁存致能信号ENPUMP被用来停止电压泵激操作的时间点被锁住。不会有不必要脉冲信号能被传递至电荷帮浦单元11N，输出电压VOUT上不需要的纹波也可以被减少。
另一方面，在电压泵激操作被停止的时间点之前，输出时钟信号CKO上的脉冲信号可以被传递至延迟单元121，以及当电压泵激操作被停止后，延迟单元121-12M还能在短暂的时间周期中正常的运作。例如，电荷帮浦单元111-11M能在短暂的时间周期正常运作。此外，如果电压泵激操作需要被重新启动，则能够在输出时钟信号CKO上产生一个新的脉冲信号，电荷帮浦单元11N则可根据输出时钟信号CKO藉由电压泵激操作立即产生输出电压VOUT，输出电压VOUT的电压降可以被减低，以及输出电压VOUT的纹波可以对应被降低。
在此实施例中，藉由延迟单元121-12M分别提供的延迟可以相同或不同。每一延迟单元121-12M可以藉由任意其他的电路结构来建构，例如，一个或多个的逻辑门。
各电荷帮浦单元111-11N根据针对时钟信号CK1-CKM上的脉冲信号以及输出时钟信号CKN以分别进行电压泵激操作。
请参考图2，图2绘示本发明的另一实施例的电荷帮浦电路的示意图。电荷帮浦电路200包括电荷帮浦单元211-214，延迟单元221-223以及锁存电路230。延迟单元221-223相串联耦接，并根据输出时钟信号CKO分别的产生多个时钟信号CK1-CK3。电荷帮浦单元211-214相互串联耦接，分别接收时钟信号CK1-CK3以及输出时钟信号CKO，并依据分别接收到的时钟信号进行电压泵激操作。
在本实施例中，延迟单元221-223分别包括反相器IN1-IN3，且时钟信号CK1与时钟信号CK2互补，时钟信号CK2与时钟信号CK3互补。锁存电路230包括反相器IN4-IN5以及锁存器LAT1。反相器IN4-IN5被做为一延迟电路，且反相器IN4-IN5延迟所接收的时钟信号CK3来产生延迟时钟信号DCK3。延迟时钟信号DCK3为锁存器LAT1所接收，且锁存器LAT1更接收锁存致能信号ENPUMA以及产生输出时钟信号CKO。
值的注意的是，锁存器LAT1可以为一个逻辑锁存门，以及当锁存致能信号ENPUMP为第一逻辑电平时，锁存器LAT1可以传递延迟时钟信号DCK3以作为输出时钟信号CKO，以及当锁存致能信号ENPUMP是为第二逻辑电平时，锁存器LAT1可以锁存延迟时钟信号DCK3的电压电平来产生输出时钟信号CKO。
最后一级电荷帮浦单元214另耦接至电阻R1以及电容C1。电阻R1耦接在电荷帮浦单元214的输出端与参考接地端GND间。电容C1耦接在电荷帮浦单元214的输出端以及参考接地端GND之间。电阻R1与电容C1可以形成用来消除针对输出电压VOUT的纹波的电路。
参考图3，图3绘示本发明再一实施例的电荷帮浦电路的示意图。电荷帮浦电路300包括电荷帮浦单元311-314、延迟单元321-323、锁存电路330以及反相器IN9。在此实施例中，所有的电荷帮浦单元311-314的电路结构可以都相同，且时钟信号CK1与时钟信号CK2互补，时钟信号CK2与时钟信号CK3互补，时钟信号CK3则与输出时钟信号CKO互补。
参考图4，图4绘示本发明再一实施例的电荷帮浦电路的示意图。电荷帮浦电路400包括电荷帮浦单元411-414、延迟单元421-423以及锁存电路430。在本实施例中，在延迟单元421-423中的反相器的数量可以不相同。例如，延迟单元421仅包括一个反相器IN1。延迟单元422包括两个反相器INA与INB，而延迟单元423则包括两个反相器INC与IND。在此可清楚发现，时钟信号CK1与时钟信号CK2不相互补，时钟信号CK2与时钟信号CK3不相互补，以及时钟信号CK3与输出时钟信号CKO不相互补。
参考图5，图5绘示本发明实施例说明的调整电路的示意图。图5中的调整电路接收输出电压VOUT，其中的输出电压VOUT可以藉由电荷帮浦电路100、200、300或400来产生，而调整电路则被用来产生锁存致能信号ENPUMP。详细来说明，图5的调整电路包括分压器510以及操作放大器OP1。分压器510接收输出电压VOUT并针对输出电压进行分压来产生反馈电压Vfb。电压分压器510包括两个电阻R1与R2。电阻R1与R2相互串联耦接，电阻R1的一端接收输出电压VOUT，电阻R1的另一端耦接电阻R2的一端，而电阻R2的另一端则耦接至参考接地端GND。
另一方面，操作放大器OP1具有一个正输入端I2以及一个负输入端I1。正输入端I2接收一个参考电压Vref，负输入端I1则接收反馈电压Vfb。操作放大器OP1比较参考电压Vref以及反馈电压Vfb来产生锁存致能信号ENPUMP。在实施例中，如果参考电压Vref大于反馈电压Vfb，则电压泵激操作不能被停止，以及操作放大器OP1产生锁存致能信号ENPUMP及逻辑电平“1”。相反的，如果参考电压Vref小于反馈电压Vfb，则电压帮浦操作可被停止，而操作放大器OP1则产生逻辑电平“0”的锁存致能信号ENPUMP。
参考图6，图6绘示本发明实施例的存储器装置的示意图。存储器装置600包括多个存储器晶胞，且存储器晶胞被排列成存储器晶胞阵列610。存储器装置600还包括电荷帮浦电路620。存储器晶胞阵列610中的存储器晶胞可以是非易失性存储器晶胞。电荷帮浦电路620则可以藉由电荷帮浦电路100、200、300以及400来实施。电荷帮浦电路620用来提供抹除电压ERS以及编程电压PGM中一个或是两者。
参考图7，根据本公开的实施例，图7绘示本发明实施例的电压泵激方法的流程图。在步骤S710中，藉由依序的延迟输出时钟信号来产生多个时钟信号。接着，在步骤S720中，接收输入电压，以及针对输入电压操作电压帮浦操作，并且根据时钟信号与输出时钟信号对应的产生输出电压。更进一步说明，在步骤S730中，当输出电压的电压电平到达参考电压的电压电平时，时钟信号中的最后一级时钟信号的电压电平被锁存并藉以产生输出时钟信号。换句话说，当输出电压的电压电平达到参考电压的电压电平，则进行锁存输出时钟信号的电压电平的动作，如此，不再有脉冲信号被传递至最后一级电荷帮浦单元。输出电压的纹波可以被减少，且电荷帮浦电路所产生的峰值电流也能被减少。
有关于步骤S710-730详细的操作，在上述的实施例中已经有详细的描述，在此不再重复说明。
虽然本发明已以实施例公开如上，然其并非用以限定本发明，本领域技术人员在不脱离本发明的精神和范围内，当可作些许的更动与润饰，故本发明的保护范围当视所附权利要求书界定范围为准。

Claims (14)

1.一种电荷帮浦电路，包含：
多个延迟单元，所述多个延迟单元相互串联耦接，其中所述多个延迟单元根据一输出时钟信号分别地产生多个时钟信号；
锁存电路，耦接该延迟单元，接收所述多个时钟信号的最后一级时钟信号以及锁存致能信号，其中该锁存电路根据该锁存致能信号决定是否锁存该最后一级时钟信号以产生该输出时钟信号；以及
多个电荷帮浦单元，所述多个电荷帮浦单元相互串联耦接，其中第一级电荷帮浦单元接收一输入电压，该电荷帮浦单元并根据该时钟信号与该输出时钟信号对该输出电压进行电压泵激操作来产生输出电压。
2.如权利要求1所述的电荷帮浦电路，其中所述多个延迟单元的其中之一包含：
至少一反相器，具有输入端耦接前一级的延迟单元的输出端，以及输出端耦接下一级的延迟单元的输入端。
3.如权利要求1所述的电荷帮浦电路，其中该锁存电路包括：
延迟电路，接收该最后一级时钟信号以及产生延迟时钟信号；以及
一锁存器，接收该延迟时钟信号以及该锁存致能信号，以及根据该锁存致能信号决定是否保持该延迟时钟信号的电压电平。
4.如权利要求1所述的电荷帮浦电路，还包括：
调整电路，耦接该帮浦单元以及该锁存电路，接收该输出电压以及比较该输出电压及参考电压来产生该锁存致能信号。
5.如权利要求4所述的电荷帮浦电路，其中该调整电路包括：
分压器，接收该输出电压以及分压该输出电压以产生反馈电压；以及
运算放大器，具有负输入端以接收该反馈电压的，正输入端以接收该参考电压，以及输出端以产生该锁存致能信号。
6.一种存储器装置，包括：
电荷帮浦电路，提供编程电压与一抹除电压中至少其中之一至该存储器装置的多个存储器晶胞，其中该电荷帮浦电路包括：
多个延迟单元，所述多个延迟单元相互串联耦接，其中所述多个延迟单元根据输出时钟信号分别产生多个时钟信号；
锁存电路，耦接该延迟单元，接收该时钟信号的最后一级时钟信号以及锁存致能信号，其中该锁存电路根据该锁存致能信号来决定是否锁存该最后一级时钟信号以产生该输出时钟信号；以及
多个电荷帮浦单元，所述多个电荷帮浦单元相互串联耦接，其中一第一级电荷帮浦单元的接收输入电压，并根据该时钟信号与该输出时钟信号以针对该输出电压进行电压泵激操作以产生输出电压。
其中该输出电压被用以做为该编程电压与该抹除电压中的至少其中之一。
7.如权利要求6所述的存储器装置，其中该延迟单元的其中之一包括：
至少一反相器，具有输入端耦接至前一级延迟单元的输出端，以及输出端其耦接至下一级延迟单元的输入端。
8.如权利要求6所述的存储器装置，其中该锁存电路包括：
延迟电路，接收该最后一级时钟信号并产生一延迟时钟信号；以及
锁存器，接收该延迟时钟信号以及该锁存致能信号，以及根据该锁存致能信号决定是否保持该延迟时钟信号的电压电平。
9.如权利要求6所述的存储器装置，其中该电荷帮浦电路还包含：
调整电路，耦接该帮浦单元以及该锁存电路，接收该输出电压以及比较该输出电压及参考电压来产生该锁存致能信号。
10.如权利要求6所述的存储器装置，其中该调节电路包括：
分压器，接收该输出电压以及分压该输出电压以产生一反馈电压；以及
运算放大器，具有负输入端以接收该反馈电压，正输入端以接收该参考电压，以及输出端以产生该锁存致能信号。
11.一种电压泵激方法，包括：
藉由依序延迟输出时钟信号以产生多个时钟信号；
接收输入电压，以及根据该时钟信号与该输出时钟信号针对该输出电压操作电压泵激操作以产生输出电压；以及
当该输出电压的电压电平到达参考电压的电压电平，锁存该时钟信号的最后一级时钟信号的电压电平以产生该输出时钟信号。
12.如权利要求11所述的电压泵激方法，还包括：
当该输出电压的电压电平小于该参考电压的电压电平时，延迟该最后一级时钟信号以产生该输出时钟信号。
13.如权利要求11所述的电压泵激方法，其中当该输出电压的电压电平达到该参考电压的电压电平时，锁存该时钟信号的该最后一级时钟信号的电压电平以产生该输出时钟信号的步骤包括：
比较该输出电压的电压电平以及该参考电压的电压电平以产生锁存致能信号；以及
根据该锁存致能信号锁存该时钟信号的该最后一级时钟信号的电压电平以产生该输出时钟信号。
14.如权利要求12所述的电压泵激方法，其中比较该输出电压的电压电平与该参考电压的电压电平以产生该锁存致能信号的步骤包括：
分压该输出电压以产生反馈电压；以及
比较该反馈电压以及该参考电压以产生该锁存致能信号。
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