TWI229500B - Soft-start charge pump circuit - Google Patents

Abstract

A charge pump is driven by at least one clock signal, for converting a supply voltage source into a pumping voltage. The pumping voltage is a function of an amplitude of the at least one clock signal such that an absolute value of the pumping voltage is larger when the amplitude of the at least one clock signal is larger. The amplitude of the at least one clock signal is so modulated as to gradually change from an activation value during an amplitude modulation period. The amplitude modulation period lasts longer than a period of the at least one clock signal by one or more metric orders. The charge pump is activated by the at least one clock signal with the amplitude of the activation value. After the activation, the charge pump is controlled in such a way that the absolute value of the pumping voltage gradually changes along with the modulation of the amplitude of the at least one clock signal.

Description

1229500 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a charge pump circuit, and in particular to a charge pump circuit capable of generating a slow start pump voltage (gj〇ft_g [tart pumping Voltage). The power switch (power switch) is properly driven to achieve the effect of suppressing the inrush current at startup. 0 [Prior art] The charge pump circuit, or capacitive voltage multiplier, (Capacitive Voltage Multiplier) Is a circuit for generating a higher voltage than the voltage source supplied to itself. With this boosting capability, the internal W components require electronic systems with different operating voltages. For example, in a portable computer, a charge pump circuit can be used to supply voltage from a supply voltage source. 〇urce) to provide the required increased voltage, while reducing the need for an additional independent high voltage source. On the other hand, connecting to many peripheral devices via USB (Universal Serial Bus) ports or other types of ports also requires no energy from the supply voltage source. In ==, the charge pump circuit can be used to drive power. This power switch is implemented by an NMOS transistor and is set to control the switching operation between the supply voltage source and the edge device. The idler voltage of the crystal is much higher than its non-polar voltage. The charge-based circuit can completely conduct the NMOS power switching transistor to provide the minimum on-resistance of 4 1229500 in the normal operation of the edge device. Refer to Figure 1 (a) for details. Explain that the conventional charge pump circuit is used to drive the power switch circuit block diagram. The drain D and the source S of the power gate 10 implemented by the NMOS transistor are used as the input terminals of the power switch 10 respectively. Output. The drain D of the power switch 10 is connected to the supply voltage source Vin, and its source S provides the output voltage ν_ to an external load (not shown / for example, a peripheral device with a USB connection). In addition, the output capacitor & amp Connected between the source s of the power switch 1G and the ground potential. The charge pump circuit η converts the supply voltage source Vin into a raised pump voltage V "to control the gate G of the power switch 10. When the gate 〇 Pump voltage Vpp phase When the supply voltage source Vin is higher than the drain D, the power switch 10 can be fully turned on to provide the maximum on-resistance, so that the output voltage at the source s of the power switch 10 is almost equal to the drain D Η. As a result, the supply voltage source Vin must be efficiently supplied to the external load. When the power switch ㈣ is turned on, the supply voltage source Vin flows through the drain / source of the power switch 10. The ON current S of the S is supplied to the external load and the output capacitor C0. The boost operation of the charge pump circuit 11 is controlled by up to ^ heavy or non-overlapping fixed amplitude clock signals 13 output from the clock generator 12 In terms of driving, each of the fixed-amplitude clock signals 13 is a synchronous pulse signal whose frequency is determined by a cover signal 15 having a predetermined frequency output from the oscillator 14. For example, a charge pump circuit 丨丨 It is a well-known Dickson-type charge pump, as shown in Figure 1 (b). Specifically, the charge mill circuit includes a plurality of series charge stages, and the 1229500 first stage is marked with the reference number U 〇。 Every # Μ 1 ^ _ pump, and includes a diode ill and a pump capacitor 112, and has-and an output node 114. Here, the Dickson type electric master is', 113 U, ^ electric pump, the slave clock 13 series of fixed-amplitude clock signals produced by CL 2-pairs of complementary clock signals Π, used to drive the capacitors at all levels. The clock signal ⑽ = odd, and the clock signal CLK2 drives even-numbered pumps. The first stage is a series charge pump. The input node n 5 is connected to the supply voltage source via V 0... 3,... The crane is connected to the supply voltage source & the last known isolated diode 116 can be regarded as a part of the last series charge pump and the charge is obtained from its T The results of the pump circuit ^ non-repeated ΐ 1 and 2 2 can have amplitude 乂 2 overlap or 且, 、, j j5 ★, used to drive each level of charge results into the voltage well of the node; i; T, V, 7 , ,, tearing up (Vclk ~ Vd) ', that is, the amplitude Vcn ^ to the second pole ° ridge Vd. If the effect of blocking the diode 116 at the extreme end is considered, the theoretical maximum electric charge that can be achieved by the charge pump circuit 11 shown by Γ / Γ. PP (N + 1) · Vd ′ where N is the number of charge pump stages. Figures 2 (a) to 2 (c) show the conventional charge timing circuit U = operation timing diagram of driving power switch 1G shown in FIG. 2⑻ series power switch

The timing diagram of the output voltage of 10 V V ° ut; and Fig. 2 (c) is the timing diagram of the 10-on: current Ion of the power switch. Referring to Fig. 2 (a), before time, the electric circuit 11 is in a disabled state, so its pump posture Vpp is zero.雷 # $ n ^ The electric pump circuit 11 starts at time TA, and starts to rise = first use. At the transition from time to time Tβ, the pumping power i vpp of the charge fruit circuit is rapidly increased from zero to a stable maximum value, such as N · Vclk— (N + 1) ·% as described in 1229500 above. The charge fruit circuit u achieves a stable operating state at that time, so that the pump voltage Vpp remains stable. Referring to Figures 2 (b) and 2 (c) at B, before the start time Ta, the pump voltage v / κ ^ Φ ^ τ of the circuit 11 is less than the threshold voltage, so the power switch 10 goes through: After the output voltage I vout is zero and the conducting current L and the conducting mercury voltage vpp reach the threshold voltage, the switch 10 can be turned on and the capacitor C can be output to the wheel. Charging makes the power on and output voltage Vout increase. Since the pump voltage v switch of the charge pump circuit 11 is driven to provide the smallest on-resistance, the power switch = the output voltage vout reaches almost equal to the supply voltage source% at time Tc. 1. When applied to drive the power switch 10, the conventional charge pump circuit 1 causes a problem. Because the pump voltage Vpp of the charge pump circuit 11 is fast, the power on M 10 provides the minimum on-state lightning resistance at the beginning of the startup. However, since the output voltage v- is zero in the initial start-up period, the capacitance C is zero. Not yet rammed, the # er side κ so the supply voltage source vin generates a considerable conductance: 1. „Flowing through the power switch 10, this is the full-in current. If the maximum soup input peak is not suitable for field suppression, it may cause the supply voltage to drop drastically or the power switch 10 may be burned. [Summary of the Invention] In view of the problems mentioned above, One of the objects of the invention is to provide a fruit circuit that can generate a slowly rising and slow-starting pump voltage. Another object of the present invention is to provide a charge pump circuit that can drive a power switch to achieve the effect of suppressing the maximum inrush current. 1229500 basis According to the present invention, a charge pump is driven by at least one clock signal to convert a supply voltage source into a pump voltage. The pump voltage is a function of the amplitude of the at least one clock signal. The greater the amplitude, the greater the absolute value of the pump voltage. The amplitude modulation of the at least one clock signal changes gradually from a start value within an amplitude modulation period. The amplitude modulation period is greater than the at least one One cycle of the clock signal is further extended by one or more orders of magnitude. The charge pump is based on the at least one clock number 4 and its amplitude is the start value. The absolute value of the pump voltage generated by the pump is relatively small after the startup. After the startup, the charge pump is controlled such that the absolute value of the pump voltage generated follows the amplitude of the at least one clock signal The modulation gradually changes to suppress the rising rate of the absolute value of the pump voltage. Preferably, the amplitude of the at least one clock signal reaches a stable value after the amplitude modulation period. Preferably, the stability The value is equal to the supply voltage source. Preferably, the amplitude of the at least one clock signal is determined by a potential difference that gradually rises across one of the capacitors during the charging process. Preferably, the The pump voltage is used to control a power switch. Preferably, the at least one clock signal is generated by a clock amplitude modulator. The clock amplitude modulator includes a slow start controller for generating a slow start controller. A start-up control signal; and a quasi-shifter in response to the slow-start control signal to modulate the amplitude of the at least one clock signal. Preferably, the slow-start control signal has a gradually changing The voltage signal is approximately 1229500. Preferably, the amplitude of the at least one amplitude modulation clock signal is determined by the gradually changing level of the slow start control signal. Preferably, the slow start controller includes: a The equivalent resistance of the switching capacitor has first and second terminals, the first terminal is connected to the supply voltage source; and a charging capacitor is connected between the second terminal and the ground, so that the slow start control signal Presented at the second endpoint. Preferably, the level shifter includes: at least one clock channel for generating the at least -amplitude-modulated clock signal, wherein each of the at least one clock channel has -An output stage inverter, one of the power supply terminals of the output stage inverter is used to receive the slow-start control signal to control the amplitude of each of the at least one amplitude-modulated clock signal. Preferably, the Each of the at least one clock channel further includes: an input, the inverter has a power supply terminal to receive the supply voltage source for providing a clock signal with a fixed amplitude to the output stage to be inverted . [Embodiment] The following description and drawings will make the foregoing and other objects, features, and advantages of the present invention more apparent. A preferred embodiment of the invention. The figure illustrates in detail a block diagram of a slow start charge circuit 31 according to the present invention applied to drive a power switch 30 according to the present invention. Comparing Fig. 3 (a) with Fig. L (a), it can be seen that 'as long as the conventional charge Cf: Pump circuit 31 according to the present invention + 1⑷ is replaced with Fig. 11', the circuit shown in Fig. 3 (a) 1229500 1 ( A) is the same as the block diagram in Figure 1 (a). The power switch 30 shown in FIG. 3 (a) is equivalent to the power switch shown in FIG. Therefore, the description of the phase circuit part in Fig. 3 (a) will be omitted below. Referring to FIG. 3 (a), the slow-start charge pump circuit 31 converts the supply voltage source I into a pump voltage Vpps with a slow-start feature under the control of at least one fixed clock signal 13 to control the closed-pole G of the power switch 30. The pump voltage Vpps with a slow-start characteristic refers to: Compared to the conventional pump voltage ^, the transition time of the slow-start voltage Vpps is increased from the starting value to a stable value. The start-up voltage is increased slowly during the time. Specifically, the slow-start charge pump 3 includes a clock amplitude modulator 3m and a clock amplitude-dependent circuit ^ 2. The clock amplitude modulator 3U performs at least one fixed-amplitude clock signal η that has a slow-start charge = = two amplitude-modulation clock signals ⑴. The clock amplitude of the pump J 312 means that the value of the pump voltage Vpp depends on the clock amplitude union circuit ^ circuit, that is, the electric power, as a function of the clock amplitude Velk. Millet, when the amplitude of the clock signal is larger, the effect of the clock-amplitude-dependent charge II is-that is, the larger. For example, Figure 叩) shows

Dickson-type charge pump j] However, its fruit voltage is often v \ T dependent charge fruit, if it is large, the power M / l Ik-(N + 1) · Vd, and the clock amplitude Vclk becomes larger as pp becomes larger. Slow start based on clock amplitude-dependent charge pump 312. The slow start charge pump circuit 31 according to the present invention can achieve the characteristics of the start-up charge pump circuit 31 with the characteristics of race start: true = to say 'in accordance with the slow speed of the present invention In the yoke example, at least one 1229500 clock signal 313 when the amplitude is modulated is designed so that its amplitude is slowed from the maximum value when the charge spring circuit 31 starts; I is added to a stable maximum value and becomes a continuously changing amplitude. 0, bell, and number H slow-start charge pump circuit 31 t The slow-start pump voltage VpPS will increase slowly as the amplitude of the amplitude-modulated clock signal 313 increases slowly. Fig. 3 (b) shows a waveform timing chart of an example of an amplitude-modulated clock signal according to the present invention. Referring to Fig. 3 (b), the amplitude modulation clock signal clks i and the amplitude modulation clock 构成 CLKS2 constitute a pair of complementary amplitude modulation clocks 313. The amplitude-modulated clock signals CLKS1 and clks2 can be generated by using the clock-amplitude modulator 311 to convert the clock signals CLK1 and CLK2 with fixed amplitude as shown in FIG. 1 (b). As a result, the amplitude-modulated clock signals CLKS1 and CLKS2 have the minimum amplitude when the charge pump is started, and then the amplitude slowly increases. After a predetermined amplitude modulation period, the amplitude reaches a stable maximum value Veik. In one embodiment according to the present invention, the stable maximum value Vclk is set equal to the supply voltage source. Tamp during the vibration field modulation period can be adjusted to an appropriate value according to the needs of the actual circuit application. The length of the amplitude modulation period Tamp will directly affect the length of the transition time required for the slow-start pump voltage VPPs from the start value to reach a stable value. In one embodiment according to the present invention, the amplitude modulation period is set to be at least an order of magnitude longer than the clock period Tclk. In another embodiment according to the present invention, the 'clock period Tclk is about 10 nanoseconds, and the amplitude modulation period Tamp is about 2.5 microseconds. Please note that in the slow-start charge pump circuit 31 according to the present invention, the clock amplitude-dependent charge pump 3 12 is activated within the amplitude modulation period Tamp 11 1229500 = boost operation, not waiting for the amplitude modulation clock signal 3i3 to stabilize The boost operation is performed only after the large value vclk. It ’s just that the amplitude is adjusted Γ. Due to the slow start of the clock amplitude-dependent charge, the voltage-dependent amplitude of the voltage-dependent electrode 312 :::: is small, so when the clock oscillates, the "start pump voltage V" will be adjusted with the amplitude. The amplitude of Zhongyan 5 increased slowly and slowly. 〇 FIG. 4 (sentence shows a circuit block diagram of the clock amplitude modulator 311 according to the present invention. Referring to FIG. 4 (a), the clock amplitude modulator 311 includes a slow-start controller 41 and a level shifter 42. The slow-start controller 41 outputs _, 'controls u vss to the level shifter 42. In response to the slow-start control signal Vss, the level shifter 42 converts it into a fixed amplitude of the clock signal 13 and converts it into Amplitude modulation clock ㈣313. The slow start control signal Vss is used to determine the amplitude modulation of the amplitude modulation clock signal 313, that is, the minimum value at startup, the maximum value at stability, the amplitude modulation period Tamp, and / or The amplitude change mode during the amplitude modulation period Tamp. Figure 4 (b) shows a detailed circuit diagram of an example of a clock amplitude modulator 3 丨 丨 according to the present invention. Referring to Figure 4 (b), the controller 41 is slowly started Includes two switches sj s2 and two capacitors. 丨 and C2. Switches 8 and s "are controlled to be in a conducting state staggered with each other and will not be in a non-conducting state at the same time. When the switch S! Is conducting, the supply voltage The source Vin charges the capacitor c! When the field switch S2 is turned on, The capacitor Ci is discharged through the switch h. From the well-known Switch Capacitor technology, it can be inferred that the circuit of the switches 81 and h and the capacitor Cl is equivalent to an equivalent resistance Req, which is coupled between the supply voltage source Vin and the capacitor q. Therefore, the supply voltage source charges capacitor 2 through the equivalent 1222950 ohm resistor Req, which causes the potential difference across capacitor c2 to be turned away and has a dark p. Π deer, the number of suspensions Req · C2. Across the capacitor The potential above C: 2 is the instantaneous application as the control signal for the starter ^ ^ ^ start control signal vss. In the practical example shown in Figure 4 (b), the potential difference across the electricity 4. ^ ^ h It is output to the level ^ ^ local shift state 42 via an output buffer circuit 43 to obtain a slow-start control signal V ^ t. Ss with enhanced driving capability. The wheel-out buffer circuit 43 includes a buffer current source ib and a buffer current.骋 v v Qb. The buffer current source Ib is connected to the supply voltage source

Vin is used for tart supply, such as: $ _ /, the required driving current. The buffer transistor Qb is implemented by an electric body, so that the potential difference across the capacitor C2 and the actual display ^ slow start control signal tiger Vss is slightly different from a fixed value, that is, the threshold value of the buffer transistor Qb Voltage. The level shifter 42 shown in Fig. 1 (b) is used to modulate the clock signals CLK1 and CLK2 with fixed amplitude vcik shown in Fig. I (b). Therefore, a clock channel is provided correspondingly. Specifically, the inverter 県 :: 2 constitutes a clock channel in a Cascade manner, in which the inverter I is used as a rounded stage and the inverter M% is used as an output stage. Similarly, the inverting f INVS and 1NV4 constitute another clock channel in a cascade manner, where the inverting 'mv3 is used as the input stage and the inverter INv4 is used as the output stage. The power supply terminals of the input stage inversion $ INV! And inv3 are both connected to the supply voltage source Vin :, while the power supply terminals of the output stage inverters INV2 and INV4 are used to slow-start the control signal Vss. Since each clock channel is composed of two inverters, the phase will not change when the clock signal passes through the clock channel. However, 'because the power supply terminals of the output stage inverter 2 and INV4 are coupled to the slow start control signal Vss, the output of the level shifter 42 is as shown in Figure 3 (b). 13 12522 ::: The amplitude-modulated clocks k CLKS1 and CLKS2 of the slow-start control signal Vss vary. In this example, the amplitude modulation period Tamp in the previous ^ m is controlled by the time constant% · of the slow start control signal Vss. Decided. Although the slow start charge system uses a clock signal in the embodiment described above, the present invention is not limited to this & the slow start charge I thunder ^ h Μ 3 y, stacked Or a non-clock signal or three or more non-4 clock signals. In the case of a slow clock signal, the level shifter 42 = η 日 ##, S 令 八 ^ 传 correspondingly set n, '里 ,， 刀 Don't use to modulate η clocks _ in $ # shifter ... Clock channels also have to construct the amplitude. Level offset = Clock signal provides different modulation methods. Or α: 得 ::: rr The slow-start control signal is used to provide different modulation methods for the n clock signals. The ST force Γ is used to display the slow-start charge circuit 31 according to the present invention, which is used to drive the operation of the power switch 30. ^, Sequence diagram 'Where Figure 5 (a) is the slow start control signal 4i, the slow start control signal I is the slow start charge pump circuit 31, and the slow start is: ^ ㈨ Figure 5 is the timing diagram of the output of the power switch 30_ ; 5⑷ is the ON current of the power switch 30 = timing diagram; and in Figure 5⑷, the solid line is used in Table 2 " B '. In Figure 5 (b) to the dotted line is used to indicate the operating characteristics obtained in Figure 2 ⑷ 2 ^ Ming, to compare with each other and suddenly replace the': conventional operating characteristics' effect. Please note the figure 5 = Kang: The practicality and superiority achieved by Λ Ming provide a slow start line according to the present invention because the control technology Vss has not been activated by the conventional skill order. 14 1229500, as shown in FIG. 5, the slow start control signal I Start at the place = slowly rise to a stable value (in this implementation, the stable value is set to "", vin), so that the amplitude of the amplitude modulation clock signal 313 increases slowly with the slow start control signal vss to approximately Vin, as mentioned before. Referring to FIG. 5 (b), before the time Ta, since the slow-start charge circuit 3! Is not enabled, its slow-start fruit circuit is repeatedly zero. Slow start of charge pump circuit 31 & time Ta starts and start ramping up Use: Since the amplitude modulation clock money 313 < amplitude increases slowly from start time Dingba, slow start of pump voltage of charge pump circuit 31 VA is slower than the voltage Vpp of the conventional charge spring circuit η: high. The conventional pump voltage Vpp has stabilized at the center of time. However, the slow start voltage Vpps according to the present invention still needs a considerable time to reach stability. Referring to FIGS. 5 (a) and 5 (b), because the slow-start system voltage vpps rises slowly, the power switch 30 is turned on later than the power switch 10, resulting in the output voltage Mv of the power switch 30. 』I rose at night. As mentioned earlier, the slow start voltage Vpps controls the gate of the power switch 30. Since the on-resistance of the power switch Chuan is proportional to its gate „, the on-resistance of the power on_ 30 decreases with the rise of the slow-start pump voltage Vpps. Because the slow-start pump voltage Vpps is greater than the conventional pump voltage Vpp It rises at a slower rate, so the on-resistance of the power switch 30 will not decrease to a minimum value in the early stage of the startup. As a result, the slowly decreasing on-resistance of the power_3G t successfully suppresses the on-current of the power on II 30 Ion, especially the inrush current when the output capacitor cQ is not charged in the initial stage of startup. 15 1229500 Voltage source vin. When the clock signal CLKS 1 goes low and the clock signal CLKS2 goes high, the NMOS transistor 621 The gate voltage does not turn on, and the pump voltage vpp is boosted to the supply voltage source Vin plus the clock amplitude V e 1 k. Refer to Figure 6 (c) 'The charge pump stage 63 includes two NMOS transistors 63 1 And 633 and ^ a PMOS transistor 632 and 634 to form a cross-coupled latch circuit. The charge pump stage 63 further includes two pump capacitors 635 and 636 driven by the clock signals CLKS1 and CLKS2 respectively. When the clock signal CLKS1 is When the clock signal CLKS2 is low, the NMOS transistor 631 is turned on and the pump capacitor 636 is charged to the supply voltage source Vin. When the clock signal CLKS1 is changed to low and the clock signal CLKS2 is changed to high, the pM0§ transistor 632 is turned on so that The pump voltage Vpp is boosted to the supply voltage source plus the clock amplitude Vclk. At this time, the NMOS transistor 633 is also turned on and the pump capacitor 635 is charged to the supply voltage source 4. When the clock signal clksi goes high and the clock signal When CLKS2 goes low, the pMOS transistor 634 is turned on and the pump voltage Vpp is boosted to the supply voltage source L plus the clock amplitude veIk. Although the present invention has been made clear, it should be understood that the present invention does not Specifically, the present invention is intended to cover various modifications and similar configurations that are familiar to each other. Because of the widest interpretation, it is limited to the disclosed embodiment by exemplifying all the preferred embodiments. Instead, those skilled in the art will instead It is obvious that the scope of the scope of the patent application should be based on such modifications and similar configurations. [Simplified illustration of the figure] 1229500 Component symbol description: 10 Power switch 11 Charge pump circuit 12 Clock generation Device 13, CLK1, CLK2 Fixed amplitude clock signal 14 Oscillator 15 Oscillation signal 30 Power switch 31 Slow start charge pump circuit 41 Slow start controller 42 Level shifter 43 Output buffer circuit 61 ~ 6 3 Clock amplitude dependent type He Guo 110, charge pump 111, diode 112, pump capacitor 113, input node 114, output node 115, input node of the first series charge pump 116, isolated diode 311, clock amplitude modulator 312 clock amplitude dependent 313, CLKS1, CLKS2 Amplitude modulated clock signal 611 Diode-coupled NMOS transistor 19 1229500 612, 623, 624, 635, 636 Pump capacitors 621, 622, 63 1, 633 NMOS transistors 632, 634 PMOS electric Crystal C1? C2 Capacitor D Drain G Gate INV! ~ INV4 Inverter lb Buffer Current Source

Ion on current

Ipeak maximum sink current

Ipeaks Slow start maximum thirst current

Qb buffer transistor

Req Switched Capacitor Equivalent Resistance S Source

Si? S2 switch

Tamp period

Tclk clock period V elk clock amplitude

Vin supply voltage source V〇ut output voltage

Vpp pump voltage

Vpps Slow Start Pump Voltage

Vss slow start control signal 20

Claims (1)

1229500 Patent application scope: 1 · A slow-start charge pump circuit including: a charge pump driven by at least one clock signal for converting a supply voltage source into a pump voltage, the pump voltage being the at least one clock A function of the signal ^ amplitude, so that as the amplitude of the at least one clock signal becomes larger, an absolute value of the fruit voltage becomes larger, wherein: the amplitude of the at least one clock signal is tuned to an amplitude modulation period It gradually changes from a start value, the amplitude modulation period is one or more orders of magnitude longer than a period of the at least one clock signal, the charge pump is switched by at least one clock signal when its amplitude is the start value It is started so that the absolute value of the pump voltage generated by it is relatively small. After the start, the charge pump is controlled so that the absolute value of the pump voltage generated is adjusted with the amplitude of the at least one clock signal. Change gradually, thereby suppressing the rising rate of the absolute value of the pump voltage. 2. Slow start charge pump circuit as claimed in item 丨 of the patent scope, where:. The amplitude of the Xuanzhixi clock 彳 § reaches a stable value after the amplitude modulation period. 3. The slow-start charge pump circuit according to item 2 of the patent application scope, wherein: the stable value is equal to the supply voltage source. 4. The slow-start charge pump circuit as described in the first item of the patent application scope, wherein: the amplitude of the at least one clock signal is a potential difference gradually rising across one of the capacitors during the charging process 21 1229500. Decided. 5. The slow-start charge pump circuit as described in item 1 of the scope of patent application, wherein: the magnitude of the amplitude modulation period is in the order of microseconds. 6. The slow-start charge pump circuit according to item 1 of the patent application scope, wherein: the pump voltage is used to control a power switch. 7. A slow-start charge pump circuit, comprising: a clock amplitude modulator for generating at least one amplitude modulation clock signal; the amplitude of the at least one amplitude modulation clock signal is changed from one to one during an amplitude modulation period; The starting value changes gradually, the amplitude modulation period is one or more orders of magnitude longer than a period of the at least one amplitude modulation clock signal; and a charge pump driven by the at least one amplitude modulation clock signal, To convert a supply voltage source into a pump voltage, wherein: the charge pump is started by the at least one amplitude-modulated clock signal when its amplitude is the start value, so that an absolute value of the pump voltage generated by the charge pump is relative to After the startup, the charge pump is controlled so that the absolute value of the pump voltage generated gradually changes with the amplitude of the at least one clock signal. 8 · If the slow start charge pump circuit of item 7 of the patent application scope, further includes a clock generator for generating at least a fixed amplitude clock signal so that 22 1229500 serves the% clock M amplitude modulator in response to the i彡 —The fixed amplitude clock signal is used to generate the at least one amplitude modulated clock signal. 9. The slow-start charge pump circuit according to claim 7 of the patent scope, further comprising: an exhaustor for generating an oscillating signal to the clock generator to determine the frequency of the at least one fixed-amplitude clock signal. For example, the slow-start charge pump circuit of claim 7 is declared, wherein: the clock amplitude modulator determines the at least one by a potential difference that gradually rises across one of the capacitors during the charging process. The amplitude modulates the amplitude of the clock signal. 11 · The slow-start charge pump circuit according to item 7 of the patent application scope, wherein: the clock amplitude modulator includes: a slow-start controller for generating a slow-start control signal; and a quasi-offset device, which responds The amplitude of the at least one amplitude-modulated clock signal is modulated at the slow-start control signal. 12. The slow start charge pump circuit according to item 11 of the scope of patent application, wherein: the slow start control signal is a voltage signal having a gradually changing level. 1 3 · The slow-start charge pump circuit according to item 12 of the scope of patent application, wherein: 23 I2295 00 The amplitude of the at least one amplitude-modulated clock signal is determined by the gradually changing level of the slow-start control signal . 14. The slow-start charge pump circuit according to item 11 of the scope of patent application, wherein: the slow-start controller includes a switching power valley special resistor 'having first and second terminals, and the first terminal is connected A supply voltage source; and a charging capacitor connected between the second terminal and the ground, so that the slow start control signal is presented at the second terminal. 1 5. The slow-start charge pump circuit according to item 丨 丨 of the patent application scope, wherein: the level shifter comprises: at least one clock channel for generating the at least one amplitude-modulated clock signal, wherein the at least one Each of the clock channels has an output stage inverter, and a power supply terminal of the output stage inverter is used to receive the slow-start control signal to control each of the at least one amplitude-modulated clock signal. amplitude. 16. The slow-start charge pump circuit according to item 15 of the scope of patent application, wherein: each of the at least one clock channel further includes: an input stage inverter having a power supply terminal for receiving the supply voltage source 'for A clock signal with a fixed amplitude is provided to the output stage inverter. 24 1229500 17. —A method for starting a charge pump circuit, including. Generating at least a clock signal, the amplitude of the at least clock signal is gradually changed from a start value during the amplitude modulation period, and the amplitude modulation period is proportional The period of the at least-clock signal is further extended by one or more orders of magnitude; when the amplitude of the at least one clock signal is the starting value, a charge voltage source is started using the at least-clock signal to convert a supply voltage source Become a pump voltage; and After the start-up, an absolute value of the pump voltage is gradually changed with the modulation of the amplitude of the at least-clock signal to suppress the rate of increase of the absolute value of the pump voltage. ^ The method of circuit, and more. 18. Starting the charge pump according to item 17 of the scope of patent application, including: making the at least a stable value of the amplitude of a clock signal after the amplitude modulation period 19. The method for starting a charge pump circuit according to item 18 of the scope of patent application: < Method, wherein the stable value is equal to the supply voltage source. 20. In the starting charge pump circuit according to item 17 of the scope of patent application: a method, in the step of generating at least one clock signal, by _ ~ capacitor across 25 1229500 electricity present in the process of charging the capacitor A gradually increasing potential difference determines the amplitude of the at least one clock signal. 26