KR101715673B1 - Hysteretic buck converter using a triangular wave generator and the delay time control circuit of the pll structure - Google Patents

Abstract

The present invention relates to a hysteretic buck converter that converts a high direct current voltage to a lower direct current voltage and uses an inductor having a relatively low power consumption as compared to a resistor. In order to increase the frequency of the output voltage signal, A signal generator for outputting a periodic signal; A delay unit for delaying the phase of the modulated signal whose frequency has been increased by the periodic signal; And a control unit for selectively feeding back the modulation signal or the delay signal output from the delay unit according to the conduction mode of the current applied to the input terminal to reduce the ripple of the reduced signal.
According to the present invention, the signal generator improves the switching frequency by causing the output voltage ripple to rapidly go between the hysteresis window voltages, thereby reducing the output voltage ripple and enabling the use of the low capacity inductor. The delay section determines the precise delay time added to synchronize the phase with the reference clock. The phase frequency detector senses the phase difference between the reference clock and the comparator output and has the advantage that the switching frequency is synchronized with the reference clock by charging or discharging the loop filter with as much current as the phase difference through the charge pump. The control unit has a function of obtaining a DC voltage corresponding to the output target value by charging or discharging the current of the input terminal using the zero current detector and the conduction mode discriminator.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a triac wave signal generator and a hysteretic buck converter using a delay time control circuit of a PLL structure.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hysteretic buck converter for reducing an applied voltage and outputting the reduced voltage, and more particularly to a hysteretic buck converter having a PLL (Phase Locked Loop) structure in which a response characteristic is improved by reducing a ripple of an output voltage.

Today, portable electronic devices are increasingly used, and most of them are battery operated devices. 'Power Management' technology is becoming increasingly important because minimizing power loss is a major concern in these handheld electronic devices. In recent years, a buck converter using an inductor capable of easily obtaining a reference voltage while minimizing power consumption is often used as a DC-DC converter.

In particular, a hysteretic buck converter that uses a hysteresis comparator to control a pull-up / pull-down switch uses a reference voltage of a particular band. The hysteretic buck converter has the advantages of high transient response and stability.

On the other hand, in relation to a buck converter having hysteretic control, it is partially disclosed in Korean Patent Laid-Open No. 10-2014-0041108 (published on Apr. 04, 2014, entitled "Power supply device and hysteretic buck converter").

Because the output voltage variation due to load current variation is directly used as the input to the comparator, the ripple of a typical buck converter will have a value greater than the window voltage of the hysteretic comparator. This slow switching frequency makes it difficult to use low-capacity inductors. This has the problem of increasing the volume and manufacturing cost of the hysteretic buck converter. In addition, the hysteretic buck converter has a problem that relatively large noise is applied to the load due to the current ripple.

Accordingly, the present invention provides a hysteretic buck converter that allows the switching frequency to operate at low power. The present invention also provides a hysteretic buck converter in which the ripple of the output voltage at the lower stage composed of an IC sensitive to EMI noise is reduced.

According to an aspect of the present invention, there is provided a hysteretic buck converter for reducing an applied voltage to output an applied voltage, the hysteretic buck converter comprising: a signal generator for outputting a periodic signal in which a period of a waveform is repeated in order to increase a frequency of an output voltage signal; ; A delay unit for delaying the phase of the modulated signal whose frequency has been increased by the periodic signal; And a controller for selectively feeding back the modulation signal or the delay signal output from the delay unit according to the conduction mode of the current applied to the input terminal to reduce the ripple of the reduced signal.

Preferably, the signal generator according to the present invention may apply a periodic signal of a triangular wave to the decompressed signal.

Preferably, the delay unit according to the present invention includes: a comparator that compares a modulation signal with a reference voltage signal, which is a target output value, and outputs an error signal in a pulse waveform; A phase frequency detector that compares the phase of the error signal with the phase of the reference clock to charge the passive element if the phase of the reference clock is faster than the phase of the error signal and discharges the charge of the passive element if it is slow; And a delay controller for calculating a delay time corresponding to a phase difference between the delay signal and the error signal based on a delay time control signal having a charge amount charged and discharged to the passive element and delaying the phase of the modulated signal by a delay time have.

Preferably, the control unit according to the present invention includes a P-type power switch for charging a current applied to an input terminal and an N-type power switch for discharging a current applied to the input terminal, and a feedback circuit for feeding back a signal transmitted from the multiplexer to an input terminal Controller; A zero current detector for detecting a change in polarity of a current applied to an input terminal; A conduction mode discriminator for discriminating between a discontinuous conduction mode in which a current at an input terminal is reduced from a signal output from the zero current detector and a continuous conduction mode in which a current at an input terminal is increased; And a multiplexer to which the signal output from the conduction mode discriminator is applied and which selectively transmits the delay signal and the error signal to the delay controller.

Preferably, the zero current sensor according to the present invention may include a current source biased by a resistor, a carry-through conductance amplifier and a cascode current mirror, and the cascode current mirror may include at least one transistor.

Preferably, the conduction mode discriminator according to the present invention judges the zero current detector signal and outputs logic 1 when the input terminal is in the continuous conduction mode and logic 0 when the input terminal is the discontinuous conduction mode to the multiplexer.

Preferably, the multiplexer according to the present invention selects a delay signal when the input terminal is in the continuous conduction mode and selects the error signal when the input terminal is in the discontinuous conduction mode, and transmits the error signal to the delay controller.

According to the present invention, the signal generating unit has an advantage of improving the switching frequency by causing the ripple of the output voltage to quickly go between the hysteresis window voltages. In this case, the output voltage ripple is reduced due to the high switching frequency and the ripple of the current applied to the inductor is reduced.

Further, according to the present invention, since the switching frequency is operated at a low power, there is an advantage that a low capacity inductor can be used.

Further, according to the present invention, the use of a low-capacity inductor has the advantage of reducing the volume and manufacturing cost of the inverter.

Further, according to the present invention, the delay unit determines an accurate delay time added to synchronize the phase with the reference clock. The phase frequency detector senses the phase difference between the reference clock and the comparator output and charges or discharges the phase difference current through the charge pump to the loop filter. In this case, there is an advantage that the frequency is synchronized with the reference clock.

According to the present invention, the control unit controls the zero current sensor and the conduction mode discriminator to drive the power switch. In this case, there is an effect that the DC voltage corresponding to the output target value can be obtained by charging or discharging the current of the input terminal.

1 shows a configuration of a hysteretic buck converter according to an embodiment of the present invention.
2 shows a circuit diagram of a signal generator according to an embodiment of the present invention and a waveform output from the signal generator.
3 shows a circuit diagram of a delay controller according to an embodiment of the present invention and a waveform of an error signal delayed by a delay controller.
4 is a circuit diagram of a zero current detector and a conduction mode discriminator according to an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the exemplary embodiments. Like reference numerals in the drawings denote members performing substantially the same function.

The objects and effects of the present invention can be understood or clarified naturally by the following description, and the purpose and effect of the present invention are not limited by the following description. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

1 shows a hysteretic buck converter 1 according to an embodiment of the present invention. The hysteretic buck converter 1 may include a signal generating unit 10, a delay unit 30, a control unit 50, and a load unit 70.

The signal generator 10 may output a periodic signal in which a waveform section is repeated in order to increase the frequency of the output voltage signal.

과 접지(Gnd)를 입력으로 갖는 MUX, P형 파워 스위치(

), 저항(

), 및 저항(

)과 직렬로 연결된 커패시터(

)를 포함할 수 있다. 2 shows a circuit diagram of the signal generator 10 according to the embodiment of the present invention. Referring to FIG. 2, the signal generating unit 10 generates a signal having a voltage applied to the hysteretic buck converter 1

And ground (Gnd) as inputs, a P-type power switch (

), resistance(

), And resistance

) Connected in series with the capacitor

).

)에 삼각파 신호를 추가해줌으로써 히스테리틱 벅 변환 장치(1)의 주파수가 증가할 수 있다. 본 명세서에서는 삼각파가 합쳐져서 주파수가 증가한 신호를 변조 신호(

)라 한다. 스위칭 주파수를 증가시킬 경우, 출력 전압(

)의 리플을 감소시킬 수 있으며 저용량 인덕터(L)의 사용이 가능하다.The waveform of the periodic signal output by the signal generator 10 may be a triangular file. Output voltage (

The frequency of the hysteretic buck converter 1 can be increased. In the present specification, a signal obtained by combining triangular waves and increasing the frequency is referred to as a modulated signal (

). When increasing the switching frequency, the output voltage (

) And the use of a low capacity inductor (L) is possible.

)와 인덕터(L)의 소형 및 박형화가 용이한 이유는 용량성 임피던스와 유도성 임피던스가 모두 주파수 f의 함수라는 점에 있다. 용량성 임피던스는 Zc＝1/（jωC）, 유도성 임피던스는 ZL＝jωL로 기술할 수 있다. 따라서, 용량성 임피던스나 유도성 임피던스를 설계하는 경우, 주파수 f를 높이면 콘덴서와 인덕터 모두 소형과 박형 부품으로 사용할 수 있다. As the switching frequency is increased,

) And the inductor (L) can be easily made small and thin because the capacitive impedance and the inductive impedance are both functions of the frequency f. The capacitive impedance can be described as Zc = 1 / (jωC) and the inductive impedance as ZL = jωL. Therefore, when capacitive impedance or inductive impedance is designed, both the capacitor and the inductor can be used as small and thin parts by increasing the frequency f.

)과 합쳐져서 비교기(302)의 (-)단자로 들어갈 수 있다.The output terminal of the signal generating unit 10 may be connected to the delay unit 30. The triangular wave signal outputted from the signal generating section 10 is outputted as an output voltage (

To the (-) terminal of the comparator 302.

)을 생성할 수 있다. 신호 발생부(10)는 P형 파워 스위치(

)를 통해 MUX의 입출력을 제어할 수 있다. 신호 발생부(10)는 기존의 불연속 전도 모드에서 입력단(701)의 스텝 전압을 저역 통과 필터의 입력으로 사용 시 발생했던 문제점을 해결할 수 있다. The signal generator 10 controls the MUX to generate a step waveform having no ringing (

Can be generated. The signal generator 10 includes a P-type power switch

) To control the input and output of the MUX. The signal generating unit 10 can solve the problem that occurs when the step voltage of the input terminal 701 is used as the input of the low pass filter in the existing discontinuous conduction mode.

)이 비교기(302)로 인가되기 전에 추가함으로써, 히스테리틱 벅 변환 장치(1)의 스위칭 주파수를 증가시키고 출력 전압(

)의 기생소자 의존도를 제거할 수 있다.The output voltage of a typical buck converter is varied by the following equation (1), which makes it difficult to use a peripheral IC that is vulnerable to EMI noise. In consideration of this, the signal generating unit 10 converts the triangular wave signal into a reduced output voltage (

) Before being applied to the comparator 302, the switching frequency of the hysteretic buck converter 1 is increased and the output voltage

) Can be eliminated.

[Equation 1]

: 스위칭 주파수,

: 출력전압,

: 입력전압,

: 커패시터의 기생 직렬 저항성분,

: 내부 지연 시간,

: 출력커패시터,

: 히스테리시스 비교기의 윈도우전압,

: 커패시터의 기생 인덕터성분)
(

: Switching frequency,

: Output voltage,

: Input voltage,

: Parasitic series resistance component of the capacitor,

: Internal delay time,

: Output capacitor,

: Hysteresis The window voltage of the comparator,

: Parasitic inductor component of capacitor)

The delay unit 30 may delay the phase of the modulation signal 317. [ The delay unit 30 includes a bandgap reference voltage generator 301, a clock generator 303, a phase frequency detector 305, a charge pump 307, a loop filter 309, a comparator 302, and a delay controller 311 ).

The bandgap reference voltage generator 301 can supply a DC reference voltage for obtaining a target output voltage. Hereinafter, the target output voltage supplied by the bandgap reference voltage generator 301 is referred to as a reference voltage signal. The reference voltage signal may be input to the (+) terminal of the comparator 302 to be compared with the phase with the modulation signal 317.

)의 주파수를 고정시키는 역할을 할 수 있다.The clock generator 303 may provide a reference clock for synchronization of the error signal 313. The clock generator 303 provides a reference clock independently to the hysteretic buck converter 1, and the output voltage

) Can be fixed.

The comparator 302 compares the modulation signal 317 with the reference voltage signal, which is the target output value, and amplifies and outputs the error signal 313 in a pulse waveform. The amplified error signal 313 may be represented by a digital value. The error signal 313 may be input to the multiplexer 505 and the phase frequency detector 305 shown below.

The phase difference detector 305 can sense the phase difference between the reference clock and the output of the comparator 302. The phase frequency detector 305 compares the phase of the error signal 313 with the phase of the reference clock so that the phase of the reference clock is faster than the phase of the error signal 313 to charge the passive element. The phase frequency detector 305 can discharge the charge of the passive element if the phase of the reference clock is slower than the phase of the error signal 313. [

)이라 한다.The passive element may comprise at least one capacitor and a resistor. In this specification, the passive element is referred to as a loop filter 309. In this specification, the voltage representing the amount of charge stored in the loop filter 309 is referred to as a delay time control signal

).

The charge pump 307 may serve to charge or discharge charges to the loop filter 309. [ The amount of charges charged and discharged into the loop filter 309 can be determined according to the phase difference between the error signal 313 and the reference clock 303. [

If the error signal 313 is phase faster than the reference clock, the circuit requires more delay time. The phase frequency detector 305 may turn on the UP switch of the charge pump 307 to increase the output of the charge pump 307 if the error signal 313 is phase earlier than the reference clock. (UP = 1)

The phase frequency detector 305 may turn on the switch DW of the charge pump 307 to lower the output voltage of the charge pump 307 if the error signal 313 is phase slower than the reference clock. (DW = 1) Through such a mechanism, the switching frequency of the hysteretic buck converter 1 has the same value as the reference clock frequency.

)와 오차 신호(313)가 입력되어 산출된 지연 시간 만큼 변조 신호(317)의 위상을 지연시킬 수 있다. 딜레이 콘트롤러(311)에는 수동소자에 충·방전된 전하량을 갖는 지연 시간 제어 신호(

)와 오차 신호(313)가 입력되고, 지연 신호(315)를 출력한다. The delay controller 311 receives a delay time control signal

And the error signal 313 are input, and the phase of the modulation signal 317 can be delayed by the calculated delay time. The delay controller 311 receives a delay time control signal ("

And an error signal 313, and outputs a delay signal 315. [

)란 루프 필터(309)에 충·방전된 전하량이 전압으로 표현된 신호를 의미한다.The delay signal 315 is a signal for correcting the phase difference between the error signal 313 and the reference clock so that the frequency of the error signal 313 can be fixed. Further, the delay time control signal (

Means a signal in which the amount of charges charged and discharged into the loop filter 309 is represented by a voltage.

3 shows a delay controller 311 according to an embodiment of the present invention. 3, the delay controller 311 includes a current source I1 3117, a current source I2 3121, a capacitor C1 3119, a capacitor C2 3123, a first comparator 3111, a second comparator 3113, SR latch 3115. < RTI ID = 0.0 >

)에 비례한다. 전류원(I1, I2)과 커패시터(C1, C2)는 일정한 값을 가지기 때문에 지연 시간 제어 신호(

)를 기준으로 지연 시간이 결정될 수 있다.
The delay time calculated by the delay controller 311 is delay time control signal

). Since the current sources I1 and I2 and the capacitors C1 and C2 have constant values, the delay time control signal

The delay time can be determined based on the delay time.

가 상승한다. 지연 시간은 기산점으로부터

의 전압 값이 지연 시간 제어 신호(

)의 전압 값과 같아지는 순간까지로 산출될 수 있다. More specifically, the starting point for calculating the delay time can be the moment when the error signal 313 becomes logic zero at logic one. From the moment the error signal 313 becomes logic zero at logic one, the capacitor C2 3123 can be charged with a current. When the capacitor C2 (3123) is charged with current, the voltage across the capacitor C2 (3123)

. The delay time is calculated from the starting point

The voltage value of the delay time control signal

) Of the voltage value of the battery.

The transistors M1 and M2 of the cascode current mirror 511 can be driven in accordance with the error signal 313. [ The transistors M1 and M2 operate as follows to drive the current sources I1 and I2. The logic of the delay signal 315 means the output waveform of the delay signal 315.

The output process of the delay signal will be described in detail as follows.

이 지연 시간 제어 신호(

)를 넘어서는 순간 제1 비교기(3111)는 로직 1을 출력하고 SR래치(3115)의 S입력을 구동하면서 지연 신호(315)는 로직 1이 될 수 있다. The transistor M1 of the cascode current mirror 511 is shut off and the current source I1 3117 of the delay controller 311 is charged to the capacitor C1 3121 when the error signal 313 changes from logic 0 to logic 1 have. The voltage charged in the capacitor C1 3121

This delay time control signal (

The first comparator 3111 outputs logic 1 and drives the S input of the SR latch 3115 so that the delay signal 315 can be a logic one.

가 지연 시간 제어 신호(

)를 넘어서는 순간 제2 비교기(3113)는 로직 1을 출력하고 SR 래치(3115)의 R입력을 구동하면서 지연 신호(315)는 로직 0이 될 수 있다. Conversely, when the error signal 313 becomes logic zero at logic 1, the current source I2 3119 of the delay controller 311 can be charged to the capacitor C2 3123. [ The voltage charged in the capacitor C2 3123

Lt; RTI ID = 0.0 >

The second comparator 3113 outputs logic 1 and drives the R input of the SR latch 3115 so that the delay signal 315 can be a logic zero.

)에 비례하고 커패시터 C1(3119), 커패시터 C2(3123)에 반비례하는 것을 알 수 있다.That is, the delay time is determined by the current source I1 3117, the current source I2 3121,

) And inversely proportional to the capacitor C1 (3119) and the capacitor C2 (3123).

) 및 N형 파워 스위치(

), 클럭 지연기(515)를 포함할 수 있다. 제어부(50)는 입력단(701)으로 인가된 전류의 전도 모드에 따라 변조 신호(317)또는 지연 신호(315)를 선택적으로 피드백 하여 출력 신호(

)의 리플을 감소시킬 수 있다. The control unit 50 includes a zero current detector 501, a conduction mode discriminator 503, a multiplexer 505, a four-phase controller 507, a P-type power switch

) And N-type power switch (

, And a clock delay 515. [ The control unit 50 selectively feeds back the modulation signal 317 or the delay signal 315 according to the conduction mode of the current applied to the input terminal 701,

) Can be reduced.

The zero current detector 501 can sense a change in the polarity of the current applied to the input terminal 701. The zero current detector 501 may be electrically connected to the input terminal 701, the conduction mode discriminator 503, and the jitter controller 507.

The zero current detector 501 senses the reverse current of the inductor L and can output a signal to the conduction mode discriminator 503.

The conduction mode discriminator 503 can distinguish the discontinuous conduction mode in which the current of the input terminal 701 is decreased from the continuous conduction mode in which the current of the input terminal 701 is increased from the output signal of the zero current detector 501.

4 is a circuit diagram of a zero current detector 501 and a conduction mode discriminator 503 according to an embodiment of the present invention. Referring to FIG. 4, the zero current detector 501 may sense a change in the polarity of the current applied to the input terminal 701. The conduction mode discriminator 503 receives the logic 1 when the input terminal 701 is in the continuous conduction mode and outputs the logic 0 to the multiplexer 505 when the input terminal is in the discontinuous conduction mode .

The zero current detector 501 may include a current source 509 biased by a resistor, a cascode current mirror 511, and a zero current comparator 513. The cascode current mirror 511 may include at least one transistor M1, M2, M4, M5, M7, and M8.

The biased current source 509 may comprise a resistor R1 connected in series with transistors M3 and M3. The cascode current mirror 511 is connected to the biased current source 509, the transistor M6 and the transistor M9. The cascode current mirror 511 can supply a constant current to the transistors M6 and M9 by copying the reference current applied from one common biased current source 509 in the entire integrated circuit.

만큼 이동시킨다. 트랜지스터 M6에 인가되는 인덕터 입력 전압

과 트랜지스터 M9의 전압 0V가 영 전류 비교기(513)를 통해 비교될 수 있다.Since the zero current comparator 513 has no input of 0 V or less, the zero-state ground voltage can be obtained by using the transistors M6 and M9 of the source follower structure

. The inductor input voltage applied to transistor M6

And the voltage 0V of the transistor M9 can be compared through the zero current comparator 513.

The cascode current mirror 511 and the transistor M6 may be connected to the (+) terminal of the zero current comparator 513 and the cascode current mirror 511 and the transistor M9 may be connected to the (-) terminal.

)에 걸리는 전압의 극성이 바뀌면서 입력단(701)에 양의 전압이 인가되도록 할 수 있다. 이 경우, 영 전류 비교기(513)는 로직 1을 출력하여 입력단(701)의 인덕터의 전압이 0V 지점을 지났다는 결과를 출력할 수 있다. When the polarity of the input terminal 701 changes and flows in the negative direction, the zero current comparator 513 outputs an N-type power switch

So that a positive voltage can be applied to the input terminal 701. In this case, In this case, the zero current comparator 513 outputs logic 1 and can output the result that the voltage of the inductor of the input stage 701 has passed the 0V point.

)는 로직 0이 되고, 전도 모드 판별기(503)로 인가된다. 이 경우 P형 파워 스위치(

)는 구동될 수 있다.More specifically, when the polarity of the inductor input terminal 701 changes and the current flows in the reverse direction, the instantaneous zero current comparator 513, which exceeds the 0V ground voltage, becomes logic 1, and this signal becomes a flip flop of the zero current detector 501 . According to the logic of the flip-flop, the N-type power switch cut-off signal (

Becomes logic zero, and is applied to the conduction mode discriminator 503. In this case, a P-type power switch

Can be driven.

)가 로직 1을 유지하다가 오차 신호(313)의 전압 값이 기준 전압 신호를 초과하게 되면 P형 파워 스위치(

)는 로직 0을 출력할 수 있다. 이 경우, N형 파워 스위치 차단신호(

)는 로직 1이 될 수 있다. P-type power switch (

Maintains the logic 1 and when the voltage value of the error signal 313 exceeds the reference voltage signal, the P-type power switch

) Can output a logic zero. In this case, the N-type power switch shutoff signal

) Can be a logic one.

The conduction mode discriminator 503 receives the output signal of the zero current detector 501. The applied output signal goes through the clock delay 515 into the flip-flop.

The conduction mode discriminator 503 discriminates the conduction mode of the input terminal 701 and outputs the discrimination signal S to the multiplexer 505. [

)는 전도 모드 판별기(503)로 입력된다. 보다 자세히 설명하면, 전도 모드 판별기(503)에는 지연된 N형 파워 스위치 차단신호(517)가 인가될 수 있다.An N-type power switch cutoff signal (" 0 ") corresponding to the output signal of the zero current detector 501

Is input to the conduction mode discriminator 503. More specifically, the delayed N-type power switch shutoff signal 517 may be applied to the conduction mode discriminator 503.

)는 오차 신호(313)와 동기가 차이나기 때문이다. 동기가 차이나게 되는 경우 전도 모드 판별에 있어 오류를 야기할 수 있다.The reason why the delayed N-type power switch shutoff signal 517 is applied is that the input N-type power switch shutoff signal

Is different from the error signal 313 in synchronization. If the motions differ, it can lead to errors in the determination of the conduction mode.

)는 클럭 지연기(515)로 입력된다. 클럭 지연기(515)의 출력인 지연된 N형 파워 스위치 차단신호(517)가 전도 모드 판별기(503)의 인가될 수 있다.Therefore, in order to synchronize with the error signal 313, the N-type power switch shutoff signal

Is input to the clock delay 515. [ The delayed N-type power switch shutdown signal 517, which is the output of the clock delay 515, may be applied to the conduction mode determiner 503. [

)는 오차 신호(313)의 상승 에지에서 로직 0을 유지하기 때문에 전도 모드 판별기의 판별 신호(S)도 로직 1을 유지할 수 있다. (연속 전도 모드

) When the hysteretic buck converter 1 is operating in the continuous conduction mode, a delayed N-type power switch shutdown signal (

) Maintains a logic 0 at the rising edge of the error signal 313, so that the discrimination signal S of the conduction mode discriminator can also maintain the logic 1. (Continuous conduction mode

)

)는 오차 신호(313)의 상승 에지에서 로직 0을 나타내기 때문에 전도 모드 판별기의 판별 신호(S)는 로직 0을 유지할 수 있다. (불연속 전도 모드

)Conversely, when the hysteretic buck converter 1 operates in the discontinuous conduction mode, the N-type power switch shutoff signal

) Indicates a logic 0 at the rising edge of the error signal 313, the discrimination signal S of the conduction mode discriminator can maintain a logic zero. (Discontinuous conduction mode

)

The multiplexer 505 may selectively transmit the delay signal 315 and the error signal 313 to the inter-frame controller 507.

The multiplexer 505 selects the delay signal 315 when the input terminal 701 is in the continuous conduction mode and selects the error signal 313 when the input terminal 701 is in the discontinuous conduction mode and transmits the error signal 313 to the jitter controller 507 have. The multiplexer 505 receives the delay signal 315 and the error signal 313 and selects and outputs the delay signal 315 and the error signal 313 according to the reference signal of the conduction mode discriminator 503 have.

The frequency at which the power switch is driven is changed according to the discrimination signal S of the conduction mode discriminator 503 and the multiplexer 505 can be driven at a frequency lower than the switching frequency in the continuous conduction mode.

의 리플을 감소시킬 수 있다. [수학식 2]에 따르면 히스테리틱 벅 변환 장치(1)의 스위칭 손실에 의한 전력전달 효율도 증가 시킬 수 있다.The driving of the power switch of the hysteretic buck converter 1 causes the output voltage

Can be reduced. According to the equation (2), the power transfer efficiency due to the switching loss of the hysteretic buck converter 1 can also be increased.

&Quot; (2) "

: 스위칭 손실,

: 주기 시간,

: 스위칭 순시 전력,(

: Switching loss,

: Cycle time,

: Switching instantaneous power,

: 스위칭on 손실,

: 스위칭off 손실,

: 스위칭 주파수)

: Switching on loss,

: Switching off loss,

: Switching frequency)

)와 입력단(701)으로 인가된 전류를 방전하는 N형 파워 스위치(

)를 구비할 수 있다. 사구간 콘트롤러(507)는 N형 파워 스위치 차단신호(

)와 멀티플렉서(505)의 출력된 신호를 입력받아, 전도 모드에 따라 P형 파워 스위치(

) 또는 N형 파워 스위치(

)를 구동시킬 수 있다.The inter-frame controller 507 can feed back the signal transmitted from the multiplexer 505 to the input terminal 701. The interphase controller 507 includes a P-type power switch (not shown) for charging the current applied to the input terminal 701

And an N-type power switch (not shown) for discharging the current applied to the input terminal 701

). The jitter controller 507 receives the N-type power switch shutoff signal (

And a multiplexer 505. The P-type power switch

) Or N-type power switch (

Can be driven.

)는 연속 전도 모드인 경우,

전압과

에 의해서 동작할 수 있다. N형 파워 스위치(

)는

전압과

에 의해서 동작할 수 있다. 만약

전압이

보다 낮으면, P형 파워 스위치(

)는 켜지고 N형 파워 스위치(

)는 꺼진다. 이 경우, 인덕터(L)의 전류는 증가될 수 있다. 반대로

이

보다 높으면 P형 파워 스위치(

)는 꺼지고, N형 파워 스위치(

)는 켜진다. 이 경우, 인덕터(L)의 전류는 감소될 수 있다.P-type power switch (

) Is a continuous conduction mode,

Voltage and

Lt; / RTI > N-type power switch (

)

Voltage and

Lt; / RTI > if

The voltage

, A P-type power switch (

) Is turned on and the N-type power switch

) Is turned off. In this case, the current of the inductor L can be increased. Contrary

this

P-type power switch (

Is turned off and the N-type power switch (

) Is turned on. In this case, the current of the inductor L can be reduced.

가 0이하의 전압이 되었을 때, 강제로 N형 파워 스위치(

)가 꺼진다. P형 파워 스위치(

)는 출력 커패시터(

)에 충전이 되면서 전압을 증가 시키는 역할을 할 수 있다. N형 파워 스위치(

)는 출력 커패시터(

)에 충전된 전압을 방전시키는 역할을 할 수 있다. P형 및 N형 파워 스위치(

,

)는 교대로 구동되어 입력단(701)의 일정한 전류를 얻도록 하고, Shoot-Through를 제거할 수 있다.In case of discontinuous conduction mode,

Becomes a voltage of 0 or less, the N type power switch (

) Is turned off. P-type power switch (

) Is the output capacitor

And the voltage can be increased. N-type power switch (

) Is the output capacitor

To discharge the charged voltage. P-type and N-type power switches (

,

Are alternately driven to obtain a constant current of the input terminal 701 and can eliminate the shoot-through.

) 및 저항(load)을 포함할 수 있다. 부하부(70)는 입력단(701)과 전력 필터단(703) 사이에 위치하여, 출력 전압의 gain을 조절하는 역할을 할 수 있다.The load section 70 includes an inductor L, a capacitor

) And a resistor (load). The load unit 70 is positioned between the input terminal 701 and the power filter stage 703 and can control the gain of the output voltage.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. will be. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by all changes or modifications derived from the scope of the appended claims and equivalents of the following claims.

1: Hysteretic buck converter
10: signal generating unit 30: delay unit
50: control unit 70:
301: Bandgap reference voltage generator
302: comparator 303: clock generator
305: phase frequency detector 307: charge pump
309: Loop filter 311: Delay controller
3111: first comparator 3113: second comparator
3115: SR latch 3117: current source I1
3119: Capacitor C1 3121: Current source I2
3123: capacitor C2 `313: error signal
315: Delay signal 317: Modulation signal
501: Zero current detector 503: Conduction mode discriminator
505: Multiplexer 507: Four-interval control
509: Biased current source 511: Cascode current mirror
513: zero current comparator 515: clock delay
517: Delayed N-type power switch disconnect signal
701: Input terminal 703: Power filter stage

Claims (7)

A hysteretic buck converter for reducing an applied voltage and outputting a reduced voltage signal,
A signal generator for outputting a periodic signal in which a waveform section is repeated;
A delay unit connected to the signal generator for delaying the phase of the modulated signal whose frequency is increased by the periodic signal; And
A control unit for selectively feeding back the modulation signal or the delay signal output from the delay unit according to the conduction mode of the current applied to the input terminal to reduce the ripple of the reduced signal;
Wherein the hysteretic buck converter comprises:
The method according to claim 1,
Wherein the waveform of the periodic signal is a triangular wave.
The method according to claim 1,
The delay unit includes:
A comparator that compares the modulated signal with a reference voltage signal that is a target output value and outputs an error signal in a pulse waveform;
A phase frequency detector that compares the phase of the error signal with the phase of the reference clock to charge the passive element if the phase of the reference clock is faster than the phase of the error signal and discharges the charge of the passive element slowly; And
A delay controller for calculating a delay time corresponding to a phase difference between the delay signal and the error signal based on a delay time control signal having a charge amount charged and discharged to the passive element and delaying the phase of the modulation signal by the delay time, Wherein the hysteretic buck converter comprises:
The method of claim 3,
Wherein,
A P-type power switch for charging a current applied to the input terminal, and an N-type power switch for discharging a current applied to the input terminal, and for feeding back a signal transmitted from the multiplexer to the input terminal;
A zero current detector for detecting a change in polarity of a current applied to the input terminal;
A conduction mode discriminator for discriminating a discontinuous conduction mode in which the current of the input terminal is decreased from a signal output from the zero current detector and a continuous conduction mode in which the current of the input terminal is increased; And
And a multiplexer for selectively transmitting the delay signal and the error signal to the inter-slot controller when a signal output from the conduction mode discriminator is applied.
5. The method of claim 4,
Wherein the zero current sensor comprises:
A current source biased by a resistor, an operational transmittance conductance amplifier, and a cascode current mirror,
Wherein the cascode current mirror comprises at least one transistor.
6. The method of claim 5,
Wherein the conduction mode discriminator determines the zero current detector signal and outputs a logic 1 if the input terminal is a continuous conduction mode and a logic 0 if the input terminal is a discontinuous conduction mode.
The method according to claim 6,
The multiplexer comprising:
And selects the delay signal when the input terminal is in the continuous conduction mode and selects the error signal when the input terminal is in the discontinuous conduction mode, and delivers the error signal to the inter-phase controller.

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