CN105575778B - 半导体装置及其制造方法 - Google Patents

半导体装置及其制造方法 Download PDF

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CN105575778B
CN105575778B CN201610065159.0A CN201610065159A CN105575778B CN 105575778 B CN105575778 B CN 105575778B CN 201610065159 A CN201610065159 A CN 201610065159A CN 105575778 B CN105575778 B CN 105575778B
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recess
trench
isolation regions
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CN105575778A (zh
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万幸仁
柯志欣
吴政宪
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明公开了一种半导体装置及其制造方法，该半导体装置及其制造方法是一种具有外延层的半导体装置及其制造方法。半导体装置包括一基底，其内形成一沟槽且沟槽下方形成一凹口。凹口的侧壁具有(111)晶面取向(crystal orientation)。沟槽深度为大于或等于凹口侧壁的长度的一半。一外延层形成于凹口及沟槽内。沟槽的深度足以使形成于半导体基底与外延层之间界面的差排(dislocation)终止于沟槽侧壁。在本发明的半导体装置中，较大的凹口侧壁的长度具有较大的沟槽隔离区的厚度，以容许有足够的深度使差排终止于隔离区而非外延材料的上表面。

Description

半导体装置及其制造方法
本申请是申请号为201110021186.5、申请日为2011年1月14日、发明名称为“半导体装置及其制造方法”的发明专利申请的分案申请。
技术领域
本发明涉及一种半导体装置，尤其涉及一种在外延成长中使用倒梯形凹口(inverted trapezoidal recess)。
背景技术
可通过在一半导体基底上外延成长其他材料，例如三五(III-V)族材料，而提升半导体装置的效能。外延材料与半导体基底之间晶格结构的差异会在外延层内形成应力。外延层内的应力可改进集成电路的速度及效能。举例来说，为了进一步提升晶体管效能，因而使用具有应变的沟道区的半导体基底来制造晶体管。当n型沟道或p型沟道使用应变的沟道区时，可增加载子迁移率(carrier mobility)而增加其效能。一般来说，希望能够在n型沟道晶体管的沟道区中沿源极至漏极方向产生伸张应变，以增加电子迁移率，而在p型沟道晶体管的沟道区中沿源极至漏极方向产生压缩应变，以增加空穴迁移率。
然而，在外延成长期间，由于不同材料的晶格结构差异，而在外延层与半导体材料之间界面形成差排。这些差排从界面延伸通过外延层。在一些情形中，差排可能延伸至外延层的表面。在上述情形中，差排延伸至或接近于表面，差排会严重影响形成于内的装置的效能。
发明内容
为了克服现有技术中存在的缺陷，在本发明一实施例中，提供了一种半导体装置，包括：一半导体基底，具有一沟槽及位于沟槽下方的一倒梯型凹口，倒梯型凹口的侧壁具有(111)晶面取向，沟槽的深度与倒梯型凹口的侧壁的长度比率等于或大于0.5；以及一三五族外延层，形成于沟槽及倒梯型凹口内。
本发明另一实施例中，提供了一种半导体装置，包括：一半导体基底；多个第一沟槽，形成于半导体基底内并填入一第一材料；一第二沟槽，位于半导体基底内且形成于第一沟槽之间；一凹口，位于半导体基底内且位于第二沟槽下方，凹口的侧壁具有(111)晶面取向，第二沟槽的深度大于或等于凹口侧壁的长度的一半；以及一三五族外延层，形成于第二沟槽及凹口内。
本发明又一实施例中，提供了一种半导体装置的制造方法，包括：提供一基底；实施一第一蚀刻，以在基底内形成具有一第一深度的一沟槽；实施一第二蚀刻，以在基底内形成一凹口，第二蚀刻露出基底的(111)晶面，顺着基底的(111)晶面的侧壁具有一第二距离，第一深度为第二距离的至少一半；以及在凹口内外延成长一三五族材料。
本发明实施例提供的半导体装置中，较大的凹口侧壁的长度具有较大的沟槽隔离区的厚度，以容许有足够的深度使差排终止于隔离区而非外延材料的上表面。
附图说明
图1至图4示出根据一实施例的具有倒梯型凹口的半导体装置制造方法中各个阶段的剖面示意图。
图5示出根据一实施例的凹口侧壁的表面形貌示意图。
图6示出根据另一实施例的具有倒梯型凹口的半导体装置。
【主要附图标记说明】
102～基底；
104～沟槽隔离区；
206～沟槽；
310～倒梯型凹口；
408～外延材料/三五族材料；
410～穿越差排；
A～深度；
A’、B’～平面；
dmax～最大深度；
X、Y～距离；
Y1～长度。
具体实施方式
以下说明本发明实施例的制作与使用。然而，可轻易了解本发明实施例提供许多合适的发明概念而可实施于广泛的各种特定背景。所公开的特定实施例仅仅用于说明以特定方法制作及使用本发明，并非用以局限本发明的范围。
图1示出根据一实施例的一基底102，其内具有沟槽隔离区104。基底102可包括：硅块材(bulk silicon)、掺杂或未掺杂的绝缘层上覆盖半导体(semiconductor-on-insulator,SOI)型基底或SOI基底的有源(active)层。一般来说，SOI包括形成于一绝缘层上的一半导体材料层，例如硅。绝缘层可为埋入式氧化(buried oxide,BOX)层或氧化硅层。绝缘层形成于一基底上，通常为硅基底或玻璃基底，然而也可使用其他基底，例如多层或渐变(gradient)式基底。
沟槽隔离区104可通过先形成沟槽，接着在沟槽内填入一介电材料而形成。在一实施例中，利用沉积及光刻技术，将一图案化掩模(未示出)形成于基底102上，例如一光致抗蚀剂掩模和/或一硬式掩模(hard mask)。之后，实施蚀刻工艺，例如反应离子蚀刻(reactive ion etch,RIE)或其他干蚀刻、各向异性湿蚀刻或任何适当的各向异性蚀刻或图案化工艺，以在基底102内形成沟槽。
形成之后，在沟槽内填入一介电材料而形成沟槽隔离区104，如图1所示。举例来说，介电材料可包括热氧化物或化学气相沉积(chemical vapor deposition,CVD)氧化硅等等。也可包括组合的材料，例如氮化硅、氮氧化硅、高介电常数材料、低介电常数材料、CVD多晶硅或其他介电材料。可实施一平坦化工艺，例如化学机械研磨(chenical mechanicalpolish,CMP)或其他回蚀刻步骤，以平坦化介电材料的上表面以及基底102，如图1所示。
图2示出在沟槽隔离区104之间的基底10内形成一沟槽206。举例来说，沟槽206可通过各向同性干蚀刻而形成。如图2所示，各向同性干蚀刻去除沟槽隔离区104之间的基底10至一深度A。以下图3将有更详细的说明。控制深度A，使深度A与后续形成于基底102内的凹口的侧壁表面的长度的比率大于或等于0.5。
图3示出根据一实施例的实施一第二蚀刻，以顺着沟槽206底部形成一倒梯型凹口310。以下将详细说明。在基底102内形成凹口310，使基底102顺着凹口310侧壁具有{111}表面取向(surface orientation)。为了在凹口310侧壁形成{111}表面取向，基底102需具有(001)表面取向。因此，通过使用具有(001)晶向(crystal orientation)的基底以及蚀刻而露出基底的(111)面，可控制差排的方向及传导，以提供表面上具有较少差排的外延层。
对沟槽206所实施的第二蚀刻利用了结晶表面选择性各向异性湿蚀刻并可使用氢氧化四甲基铵(tetra-methyl ammonium hydroxide,TMAH)溶液，其体积浓度(volumeconcentration)在1％至10％的范围，而温度在15℃至50℃的范围。在另一实施例中，也可使用其他结晶表面选择性湿蚀刻溶液，例如氢氧化铵(ammonium hydroxide,NH3OH)、氢氧化钾(potassium hydroxide,KOH)或胺基蚀刻溶液。上述选择性湿蚀刻导致基底102顺着沟槽206侧壁露出{111}表面。如图3所示，上述工艺形成了一倒梯型凹口。
图4示出在凹口内外延成长一三五族材料408。如图3所示，穿越差排(threadingdislocation)(如附图中的线410所示)朝垂直于侧壁的{111}表面的方向延伸。在一实施例中，三五族外延层包括具有六方晶体结构的氮化镓(GaN)且形成于基底102的(111)表面上，外延材料408的穿越差排410朝GaN的(0001)方向延伸。然而，当穿越差排410与(1-100)面相交，穿越差排改变方向至(1-100)方向，其通常平行于凹口侧壁的{111}表面。
因此，选择沟槽206的深度A，以容许穿越差排终止于沟槽隔离区104的侧壁，以提供表面实质上不具有穿越差排的外延材料。为了得到上述结构，深度A大于或等于凹口310的侧壁长度(如图4的距离Y)的一半。
图5示出根据一实施例的最大深度dmax的计算(深度A的理论最大值)，其中相同的部间隙使用相同标号。平面A’表示GaN外延层的(1-101)面，而平面B’表示GaN外延层的(0001)面。两平面之间的角度已知为62°。因此，最大深度dmax与距离X的关系取决于以下的方程式：
Figure BDA0000918500230000051
(方程式1)
另外，
X＝tan(62°)×0.5×Y (方程式2)
因此，结合方程式1和2为：
Figure BDA0000918500230000052
(方程式3)
尽管深度A的理论最大值的计算如上，然而发现到可最佳化成长条件而得到较小的深度A值。举例来说，发现到通过最佳化蚀刻及成长条件，深度A/Y的值约在0.5至0.75的范围。因此，在一实施例中，沟槽206具有一深度A，使深度A/Y大于或等于0.5，而穿越差排410终止于沟槽206的侧壁。在一实施例中，通过控制干蚀刻深度(蚀刻时间)及KOH或TMAH各向异性蚀刻深度(蚀刻时间、溶液浓度及温度)，以控制凹口310的深度至小于200nm。可在成长GaN之前，在硅沟槽内形成由AlN所构成的缓冲层(成长温度为1100℃、压力为100mbar并使用五族(Group-V)成长源(例如，NH3)及三族(Group-III)前驱物(precursor)(例如，三甲基铝(trimethylaluminium))，且维持低的V/III比率(约为650))。接着可在AlN缓冲层上成长GaN(成长温度为1120℃、压力为200mbar并使用五族成长源(例如，NH3)及三族前驱物(例如，三甲基镓(trimethylgalium))，且维持相对高的V/III比率(约为1500))。
图6示出倒梯型凹口的另一范例。在本范例中，深度A延伸至沟槽隔离区104的整个厚度。如此一来，本实施例容许沟槽206及外延材料408延伸至沟槽隔离区104的下方。调整沟槽隔离区104的厚度以维持上述的比率。
可以理解的是凹口侧壁的长度Y1决定差排410如何朝外延层表面传导。因此，较大的长度Y1具有较大的沟槽隔离区104的厚度A，以容许有足够的深度使差排终止于隔离区而非外延材料408的上表面。
虽然本发明已以较佳实施例公开如上，然其并非用以限定本发明，任何所属技术领域中具有普通知识的技术人员，在不脱离本发明的精神和范围内，当可作更动、替代与润饰。再者，本发明的保护范围并未局限于说明书内所述特定实施例中的工艺、机器、制造、物质组成、装置、方法及步骤，任何所属技术领域中具有普通知识的技术人员可从本发明公开内容中理解现行或未来所发展出的工艺、机器、制造、物质组成、装置、方法及步骤，只要可以在此处所述实施例中实施大体相同功能或获得大体相同结果皆可使用于本发明中。因此，本发明的保护范围包括上述工艺、机器、制造、物质组成、装置、方法及步骤。

Claims (9)

1.一种半导体装置，包括：
一半导体基底，具有多个沟槽隔离区，一沟槽及位于该沟槽下方的一倒梯型凹口，其中该沟槽形成于所述多个沟槽隔离区之间，该沟槽的侧壁包括所述多个沟槽隔离区且该倒梯型凹口延伸于所述多个沟槽隔离区的下方，该倒梯型凹口的侧壁具有(111)晶面取向，且该倒梯型凹口具有一底部延伸于该倒梯型凹口侧壁的底端之间，该底部与该倒梯型凹口侧壁之间夹有一钝角，该沟槽的深度与该倒梯型凹口的侧壁的长度比率等于或大于0.5，其中该倒梯型凹口自所述多个沟槽隔离区的一底面的上方延伸至所述多个沟槽隔离区的该底面的下方，且该倒梯型凹口的侧壁并未延伸至所述多个沟槽隔离区邻接于该沟槽的一侧面与所述多个沟槽隔离区的该底面的交点；
一三五族缓冲层，形成于该倒梯型凹口内，该三五族缓冲层由一五族的第一成长源及一三族的第一前驱物形成，且该五族的第一成长源和该三族的第一前驱物具有一第一五族/三族(V/III)比率；以及
一三五族外延层，形成于该沟槽及该倒梯型凹口内，且位于该三五族缓冲层上，该三五族外延层由一五族的第二成长源及一三族的第二前驱物形成，且该五族的第二成长源和该三族的第二前驱物具有一第二五族/三族(V/III)比率，其中该第一五族/三族(V/III)比率小于该第二五族/三族(V/III)比率，该三五族外延层是由GaN制成，该三五族外延层具有(1-100)面，且该(1-100)面将穿越差排的延伸方向改变至(1-100)方向。
2.如权利要求1所述的半导体装置，其中该半导体基底具有(111)晶面取向。
3.一种半导体装置，包括：
一半导体基底；
多个第一沟槽，形成于该半导体基底内并填入一第一材料；
一第二沟槽，位于该半导体基底内且形成于所述多个第一沟槽之间；
一凹口，位于该半导体基底内且位于该第二沟槽下方，该凹口的侧壁具有(111)晶面取向且该凹口具有一底部延伸于该凹口侧壁的底端之间，且该底部与该凹口侧壁之间夹有一钝角，该第二沟槽的深度大于或等于该凹口侧壁的长度的一半，其中至少一部分的该凹口延伸至所述多个第一沟槽的一底面下方，且该凹口侧壁并未延伸至所述多个第一沟槽邻接于该第二沟槽的一侧面与所述多个第一沟槽的该底面的交点；
一三五族缓冲层，形成于该凹口内，该三五族缓冲层由一五族的第一成长源及一三族的第一前驱物形成，且该五族的第一成长源和该三族的第一前驱物具有一第一五族/三族(V/III)比率；以及
一三五族外延层，形成于该第二沟槽及该凹口内，且位于该三五族缓冲层上，且该三五族外延层由一五族的第二成长源及一三族的第二前驱物形成，且该五族的第二成长源和该三族的第二前驱物具有一第二五族/三族(V/III)比率，其中该第一五族/三族(V/III)比率小于该第二五族/三族(V/III)比率，该三五族外延层是由GaN制成，该三五族外延层具有(1-100)面，且该(1-100)面将穿越差排的延伸方向改变至(1-100)方向。
4.如权利要求3所述的半导体装置，其中该半导体基底具有(111)晶面取向。
5.一种半导体装置制造方法，包括：
提供一基底；
在基底内形成多个沟槽隔离区；
实施一第一蚀刻，以在该基底内形成具有一第一深度的一沟槽；
实施一第二蚀刻，以在该基底内的该沟槽底部及所述多个沟槽隔离区之间形成一凹口，该第二蚀刻露出该基底的(111)晶面，顺着该基底的(111)晶面的侧壁具有一第二距离且该凹口自所述多个沟槽隔离区的一底面的上方延伸至所述多个沟槽隔离区的该底面的下方，该凹口具有一底部延伸于该凹口侧壁的底端之间，该底部与该凹口侧壁之间夹有一钝角，且该凹口侧壁并未延伸至所述多个沟槽隔离区邻接于该沟槽的一侧面与所述多个沟槽隔离区的该底面的交点，该第一深度为该第二距离的0.5至0.75；
在该凹口上形成一三五族缓冲层，该三五族缓冲层由一五族的第一成长源及一三族的第一前驱物形成，且该五族的第一成长源和该三族的第一前驱物具有一第一五族/三族(V/III)比率；以及
在该凹口内及该三五族缓冲层上外延成长一三五族材料，且该三五族材料由一五族的第二成长源及一三族的第二前驱物形成，且该五族的第二成长源和该三族的第二前驱物具有一第二五族/三族(V/III)比率，其中该第一五族/三族(V/III)比率小于该第二五族/三族(V/III)比率，该三五族外延层是由GaN制成，该三五族外延层具有(1-100)面，且该(1-100)面将穿越差排的延伸方向改变至(1-100)方向。
6.如权利要求5所述的半导体装置制造方法，还包括在实施该第一蚀刻之前，在所述多个隔离区内填入一第一材料，其中该第一蚀刻包括各向同性蚀刻。
7.如权利要求5所述的半导体装置制造方法，还包括在实施该第一蚀刻之前，在所述多个隔离区内填入一第一材料，其中所述多个隔离区的厚度大于该第一深度。
8.如权利要求5所述的半导体装置制造方法，其中该基底包括硅块材且具有(001)表面取向。
9.如权利要求5所述的半导体装置制造方法，其中至少使用氢氧化铵或氢氧化四甲基铵来实施该第二蚀刻。
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US20160064271A1 (en) 2016-03-03
CN105575778A (zh) 2016-05-11
CN102347352A (zh) 2012-02-08
TW201205802A (en) 2012-02-01
US9583379B2 (en) 2017-02-28
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US9184050B2 (en) 2015-11-10
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