TWI440174B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI440174B
TWI440174B TW099145764A TW99145764A TWI440174B TW I440174 B TWI440174 B TW I440174B TW 099145764 A TW099145764 A TW 099145764A TW 99145764 A TW99145764 A TW 99145764A TW I440174 B TWI440174 B TW I440174B
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trench
substrate
semiconductor device
recess
depth
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TW201205802A (en
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Clement Hsingjen Wann
Chih Hsin Ko
Cheng Hsien Wu
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Taiwan Semiconductor Mfg
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Description

半導體裝置及其製造方法
本發明係有關於一種半導體裝置，特別是有關於一種於磊晶成長中使用倒梯形凹口(inverted trapezoidal recess)。
可透過在一半導體基底上磊晶成長其他材料，例如三五(III-V)族材料，而提升半導體裝置的效能。磊晶材料與半導體基底之間晶格結構的差異會在磊晶層內形成應力。磊晶層內的應力可改進積體電路的速度及效能。舉例來說，為了進一步提升電晶體效能，因而使用具有應變的通道區的半導體基底來製造電晶體。當n型通道或p型通道使用應變的通道區時，可增加載子遷移率(carrier mobility)而增加其效能。一般來說，希望能夠在n型通道電晶體的通道區中沿源極至汲極方向產生伸張應變，以增加電子遷移率，而在p型通道電晶體的通道區中沿源極至汲極方向產生壓縮應變，以增加電洞遷移率。
然而，在磊晶成長期間，由於不同材料的晶格結構差異，而在磊晶層與半導體材料之間界面形成差排。這些差排從界面延伸通過磊晶層。在一些情形中，差排可能延伸至磊晶層的表面。在上述情形中，差排延伸至或接近於表面，差排會嚴重影響形成於內的裝置的效能。
在本發明一實施例中，一種半導體裝置，包括：一半導體基底，具有一溝槽及位於溝槽下方的一倒梯型凹口，倒梯型凹口的側壁具有(111)晶面取向，溝槽的深度與倒梯型凹口的側壁的長度比率等於或大於0.5；以及一三五族磊晶層，形成於溝槽及倒梯型凹口內。
本發明另一實施例中，一種半導體裝置，包括：一半導體基底；多個第一溝槽，形成於半導體基底內並填入一第一材料；一第二溝槽，位於半導體基底內且形成於第一溝槽之間；一凹口，位於半導體基底內且位於第二溝槽下方，凹口的側壁具有(111)晶面取向，第二溝槽的深度大於或等於凹口側壁的長度的一半；以及一三五族磊晶層，形成於第二溝槽及凹口內。
本發明又一實施例中，一種半導體裝置之製造方法，包括：提供一基底；實施一第一蝕刻，以在基底內形成具有一第一深度的一溝槽；實施一第二蝕刻，以在基底內形成一凹口，第二蝕刻露出基底的(111)晶面，順著基底的(111)晶面的側壁具有一第二距離，第一深度為第二距離的至少一半；以及在凹口內磊晶成長一三五族材料。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
第1圖係繪示出根據一實施例之一基底102，其內具有溝槽隔離區104。基底102可包括：矽塊材(bulk silicon)、摻雜或未摻雜的絕緣層上覆蓋半導體(semiconductor-on-insulator,SOI)型基底或SOI基底的主動(active)層。一般來說，SOI包括形成於一絕緣層上的一半導體材料層，例如矽。絕緣層可為埋入式氧化(buried oxide,BOX)層或氧化矽層。絕緣層形成於一基底上，通常為矽基底或玻璃基底，然而也可使用其他基底，例如多層或漸變(gradient)式基底。
溝槽隔離區104可透過先形成溝槽，接著在溝槽內填入一介電材料而形成。在一實施例中，利用沉積及微影技術，將一圖案化罩幕(未繪示)形成於基底102上，例如一光阻罩幕及/或一硬式罩幕(hard mask)。之後，實施蝕刻製程，例如反應離子蝕刻(reactive ion etch,RIE)或其他乾蝕刻、非等向性濕蝕刻或任何適當的非等向性蝕刻或圖案化製程，以在基底102內形成溝槽。
形成之後，在溝槽內填入一介電材料而形成溝槽隔離區104，如第1圖所示。舉例來說，介電材料可包括熱氧化物或化學氣相沉積(chemical vapor deposition,CVD)氧化矽等等。也可包括組合的材料，例如氮化矽、氮氧化矽、高介電常數材料、低介電常數材料、CVD多晶矽或其他介電材料。可實施一平坦化製程，例如化學機械研磨(chenical mechanical polish,CMP)或其他回蝕刻步驟，以平坦化介電材料的上表面以及基底102，如第1圖所示。
第2圖係繪示出在溝槽隔離區104之間的基底10內形成一溝槽206。舉例來說，溝槽206可透過等向性乾蝕刻而形成。如第2圖所示，等向性乾蝕刻去除溝槽隔離區104之間的基底10至一深度A。以下第3圖將有更詳細的說明。控制深度A，使深度A與後續形成於基底102內的凹口的側壁表面的長度的比率大於或等於0.5。
第3圖係繪示出根據一實施例之實施一第二蝕刻，以順著溝槽206底部形成一倒梯型凹口310。以下將詳細說明。在基底102內形成凹口310，使基底102順著凹口310側壁具有{111}表面取向(surface orientation)。為了在凹口310側壁形成{111}表面取向，基底102需具有(001)表面取向。因此，透過使用具有(001)晶向(crystal orientation)的基底以及蝕刻而露出基底的(111)面，可控制差排的方向及傳導，以提供表面上具有較少差排的磊晶層。
對溝槽206所實施的第二蝕刻係利用了結晶表面選擇性非等向性濕蝕刻並可使用氫氧化四甲基銨(tetra-methyl ammonium hydroxide,TMAH)溶液，其體積濃度(volume concentration)在1%至10%的範圍，而溫度在15℃至50℃的範圍。在另一實施例中，也可使用其他結晶表面選擇性濕蝕刻溶液，例如氫氧化銨(ammonium hydroxide,NH3 OH)、氫氧化鉀(potassium hydroxide,KOH)或胺基蝕刻溶液。上述選擇性濕蝕刻導致基底102順著溝槽206側壁露出{111}表面。如第3圖所示，上述製程形成了一倒梯型凹口。
第4圖係繪示出在凹口內磊晶成長一三五族材料408。如第3圖所示，穿越差排(threading dislocation)(如圖式中的線410所示)朝垂直於側壁的{111}表面的方向延伸。在一實施例中，三五族磊晶層包括具有六方晶體結構的氮化鎵(GaN)且形成於基底102的(111)表面上，磊晶材料408的穿越差排410朝GaN的(0001)方向延伸。然而，當穿越差排410與(1-100)面相交，穿越差排改變方向至(1-100)方向，其通常平行於凹口側壁的{111}表面。
因此，選擇溝槽206的深度A，以容許穿越差排終止於溝槽隔離區104的側壁，以提供表面實質上不具有穿越差排的磊晶材料。為了得到上述結構，深度A大於或等於凹口310的側壁長度(如第4圖的距離Y)的一半。
第5圖係繪示出根據一實施例之最大深度dmax 的計算(深度A的理論最大值)，其中相同的部間隙使用相同標號。平面A’表示GaN磊晶層的(1-101)面，而平面B’表示GaN磊晶層的(0001)面。兩平面之間的角度已知為62°。因此，最大深度dmax 與距離X的關係取決於以下的方程式：
另外，
X =tan(62°)×0.5×Y 　(方程式2)
因此，結合方程式1及2為：
儘管深度A的理論最大值的計算如上，然而發現到可最佳化成長條件而得到較小的深度A值。舉例來說，發現到透過最佳化蝕刻及成長條件，深度A/Y的值約在0.5至0.75的範圍。因此，在一實施例中，溝槽206具有一深度A，使深度A/Y大於或等於0.5，而穿越差排410終止於溝槽206的側壁。在一實施例中，透過控制乾蝕刻深度(蝕刻時間)及KOH或TMAH非等向性蝕刻深度(蝕刻時間、溶液濃度及溫度)，以控制凹口310的深度至小於200 nm。可在成長GaN之前，在矽溝槽內形成由AlN所構成的緩衝層(成長溫度為1100℃、壓力為100 mbar並使用五族(Group-V)成長源(例如，NH3 )及三族(Group-III)前驅物(precursor)(例如，三甲基鋁(trimethylaluminium))，且維持低的V/III比率(約為650))。接著可在AlN緩衝層上成長GaN(成長溫度為1120℃、壓力為200 mbar並使用五族成長源(例如，NH3 )及三族前驅物(例如，三甲基鎵(trimethylgalium))，且維持相對高的V/III比率(約為1500))。
第6圖係繪示出倒梯型凹口的另一範例。在本範例中，深度A延伸至溝槽隔離區104的整個厚度。如此一來，本實施例容許溝槽206及磊晶材料408延伸至溝槽隔離區104的下方。調整溝槽隔離區104的厚度以維持上述的比率。
可以理解的是凹口側壁的長度Y1決定差排410如何朝磊晶層表面傳導。因此，較大的長度Y1具有較大的溝槽隔離區104的厚度A，以容許有足夠的深度使差排終止於隔離區而非磊晶材料408的上表面。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
102．．．基底
104．．．溝槽隔離區
206．．．溝槽
310．．．倒梯型凹口
408．．．磊晶材料/三五族材料
410．．．穿越差排
A．．．深度
A’、B’．．．平面
dmax ．．．最大深度
X、Y．．．距離
Y1．．．長度
第1至4圖係繪示出根據一實施例之具有倒梯型凹口的半導體裝置製造方法中各個階段的剖面示意圖。
第5圖係繪示出根據一實施例之凹口側壁的表面形貌示意圖。
第6圖係繪示出根據另一實施例之具有倒梯型凹口的半導體裝置。
102．．．基底
104．．．溝槽隔離區
206．．．溝槽
310．．．倒梯型凹口
408．．．磊晶材料/三五族材料
410．．．穿越差排
A．．．深度
Y．．．距離

Claims (10)

  1. 一種半導體裝置，包括：一半導體基底，具有一溝槽及位於該溝槽下方的一倒梯型凹口，該倒梯型凹口的側壁具有(111)晶面取向，該溝槽的深度與該倒梯型凹口的側壁的長度比率等於或大於0.5；以及一三五族磊晶層，形成於該溝槽及該倒梯型凹口內。
  2. 如申請專利範圍第1項所述之半導體裝置，其中該半導體基底包括多個溝槽隔離區，而該溝槽的側壁包括該等溝槽隔離區且該倒梯型凹口延伸於該等溝槽隔離區的下方。
  3. 如申請專利範圍第1項所述之半導體裝置，其中該半導體基底具有(111)晶面取向。
  4. 一種半導體裝置，包括：一半導體基底；多個第一溝槽，形成於該半導體基底內並填入一第一材料；一第二溝槽，位於該半導體基底內且形成於該等第一溝槽之間；一凹口，位於該半導體基底內且位於該第二溝槽下方，該凹口的側壁具有(111)晶面取向，該第二溝槽的深度大於或等於該凹口側壁的長度的一半；以及一三五族磊晶層，形成於該第二溝槽及該凹口內。
  5. 如申請專利範圍第4項所述之半導體裝置，其中該凹口延伸至該等第一溝槽下方且該半導體基底具有(111)晶面取向。
  6. 一種半導體裝置製造方法，包括：提供一基底；實施一第一蝕刻，以在該基底內形成具有一第一深度的一溝槽；實施一第二蝕刻，以在該基底內形成一凹口，該第二蝕刻露出該基底的(111)晶面，順著該基底的(111)晶面的側壁具有一第二距離，該第一深度為該第二距離的至少一半；以及在該凹口內磊晶成長一三五族材料。
  7. 如申請專利範圍第6項所述之半導體裝置製造方法，更包括在實施該第一蝕刻之前，在該基底內形成多個隔離區且在該等隔離區內填入一第一材料，其中該第一蝕刻包括等向性蝕刻。
  8. 如申請專利範圍第6項所述之半導體裝置製造方法，更包括在實施該第一蝕刻之前，在該基底內形成多個隔離區且在該等隔離區內填入一第一材料，其中該等隔離區的厚度大於該第一深度。
  9. 如申請專利範圍第6項所述之半導體裝置製造方法，其中該基底包括矽塊材且具有(001)表面取向。
  10. 如申請專利範圍第6項所述之半導體裝置製造方法，其中至少使用氫氧化銨或氫氧化四甲基銨來實施該第二蝕刻。
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