CN105552180A - Fabrication method of novel high-voltage LED - Google Patents
Fabrication method of novel high-voltage LED Download PDFInfo
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- CN105552180A CN105552180A CN201610074657.1A CN201610074657A CN105552180A CN 105552180 A CN105552180 A CN 105552180A CN 201610074657 A CN201610074657 A CN 201610074657A CN 105552180 A CN105552180 A CN 105552180A
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- 238000000034 method Methods 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 49
- 229910052751 metal Inorganic materials 0.000 claims abstract description 99
- 239000002184 metal Substances 0.000 claims abstract description 99
- 239000000758 substrate Substances 0.000 claims abstract description 67
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 7
- 239000010980 sapphire Substances 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 230000004888 barrier function Effects 0.000 claims description 48
- 239000000463 material Substances 0.000 claims description 22
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 7
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 229910052697 platinum Inorganic materials 0.000 claims description 6
- 229910052719 titanium Inorganic materials 0.000 claims description 6
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 229910052804 chromium Inorganic materials 0.000 claims description 3
- 229910052750 molybdenum Inorganic materials 0.000 claims description 3
- 239000011733 molybdenum Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 230000008021 deposition Effects 0.000 abstract description 3
- 230000017525 heat dissipation Effects 0.000 abstract description 3
- 238000005538 encapsulation Methods 0.000 abstract 1
- 239000003292 glue Substances 0.000 description 10
- 238000005457 optimization Methods 0.000 description 9
- 238000001704 evaporation Methods 0.000 description 8
- 230000008020 evaporation Effects 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 7
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- 239000007769 metal material Substances 0.000 description 4
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910020068 MgAl Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
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- 229910052733 gallium Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
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- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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Abstract
The invention provides a fabrication method of a novel high-voltage LED. The fabrication method comprises the following steps: carrying out epitaxial layer deposition on a growth substrate; forming an isolating groove; etching a mesa platform to form a reflecting metal layer; forming an isolating metal layer; forming a first insulating layer; forming an interconnect metal layer; forming a second insulating layer; forming a bonding metal layer; bonding a heat-conducting substrate; removing a sapphire growth substrate; fabricating a p electrode; and the like. By stripping a low-conductivity growth substrate, a luminous body is transferred to a high-thermal conductivity substrate to improve the heat dissipation capability of a chip. The high-voltage LED fabricated by the method has the characteristics of good heat dissipation performance, easiness for encapsulation and the like, and is suitable for large-scale technological production.
Description
Technical field
The present invention relates to LED manufacture technology field, particularly relate to the manufacture method of a kind of novel high-pressure LED.
Background technology
Light-emitting diode (LightEmittingDiode, be called for short LED) be a kind of light emitting semiconductor device, be made up of the compound of gallium (Ga) with arsenic (As), phosphorus (P), nitrogen (N), indium (In), utilize semiconductor P-N junction electroluminescent principle to make.LED is long with the high and low power consumption of its brightness, life-span, it is fast to start, and power is little, without stroboscopic, be not easy generation and look the advantages such as visual fatigue, becomes light source of new generation first-selection.
Along with the development of industry, the direction that LED chip is chasing more specular removal, more high power, higher reliability strides forward step by step.And in LED application end, main occuping market be still small-power and middle power chip, high-power chip only has fewer companies to set foot in due to yield issues.
Many Novel LED chips appear in the public visual field in recent years, and its mesohigh (Highvoltage) LED, is better than general conventional low LED with its efficiency, receives much concern.Current spread mainly can be opened owing to small area analysis, multiunit design by high-voltage LED efficiency height uniformly, and high-voltage LED can realize direct voltage driving, thus saves the cost of LED driving.Existing high voltage LED chip also exists the problem that power increases, heat radiation is difficult and reliability reduces.
For heat dissipation problem, the structure of industry to high voltage LED chip has gone out further improvement.Such as, number of patent application is that 201510022007.8 employings increase the method for heating column to increase the thermal diffusivity of chip.But it is high that this method technique realizes difficulty, is not easily widely used in large-scale production.
Therefore, the manufacture method of a kind of novel high-pressure LED is provided to be the problem that those skilled in the art need to solve.
Summary of the invention
The shortcoming of prior art in view of the above, the object of the present invention is to provide the manufacture method of a kind of novel high-pressure LED, for solving the problems such as the heat radiation of prior art high-voltage LED difficulty, complex process.
For achieving the above object and other relevant objects, the invention provides the manufacture method of a kind of novel high-pressure LED, described manufacture method at least comprises:
1) growth substrates is provided, at described growth substrates growing epitaxial layers, the P type GaN layer that described epitaxial loayer comprises N-type GaN layer, grows the multiple quantum well layer on described N-type GaN layer surface and grow on described multiple quantum well layer surface;
2) etch described epitaxial loayer, form the isolated groove exposing described growth substrates, make described epitaxial loayer form multiple separate chip;
3) etch the epitaxial loayer of each chip, form the opening exposing described N-type GaN layer;
4) form reflective metal layer on described P type GaN layer surface, described reflective metal layer covers isolating metal layer;
5) at described epitaxial loayer and isolating metal layer surface coverage first insulating barrier, first surface of insulating layer perforate in said opening, expose described N-type GaN layer, simultaneously in described first surface of insulating layer perforate, form the interconnected window exposing described isolating metal layer, wherein isolating metal layer surface not perforate described in first chip;
6) in described first surface of insulating layer, opening and interconnected window, fill interconnect metal, the isolating metal layer of adjacent chips and N-type GaN layer are electrically connected, form cascaded structure;
7) at described first insulating barrier and interconnect metal surface coverage second insulating barrier, wherein, the second insulating barrier of most end chip surface forms N electrode contact hole;
8) in described second insulating barrier and interconnect metal surface and isolated groove, bonding metal layer is covered, by described bonding metal layer by step 7) structure that obtains and thermal conductive substrate bonding;
9) peel off described growth substrates, etch the N-type GaN layer of described first chip, multiple quantum well layer and P type GaN layer from the back side successively, form the P electrode contact hole exposing reflective metal layer;
10) form the 3rd insulating barrier, etch the 3rd insulating barrier in described P electrode contact hole, in described P electrode contact hole, fill the P electrode be electrically connected with the reflective metal layer of first chip.
As the scheme of a kind of optimization of the manufacture method of novel high-pressure LED of the present invention, described step 2) in adopt the method that ICP etching or laser scribing split to form described isolated groove, described isolated groove is inverted trapezoidal structure.
As the scheme of a kind of optimization of the manufacture method of novel high-pressure LED of the present invention, the material of described reflective metal layer is one or more the combination in Ni, A, Ti, Pt or Au, and thickness range is
As the scheme of a kind of optimization of the manufacture method of novel high-pressure LED of the present invention, the material of described interconnect metal is one or more the combination in Cr, Al, Ti, Ni, Pt or Au, and thickness range is
As the scheme of a kind of optimization of the manufacture method of novel high-pressure LED of the present invention, the interconnect metal in described isolated groove and the first insulating barrier form ODR structure, make described isolated groove become reflective trenches.
As the scheme of a kind of optimization of the manufacture method of novel high-pressure LED of the present invention, described first insulating barrier, the second insulating barrier and the 3rd insulating barrier are selected from SiO
2, Si
3the material stack layers that one or more materials in N4 or DBR are formed.
As the scheme of a kind of optimization of the manufacture method of novel high-pressure LED of the present invention, described thermal conductive substrate is metal substrate, silicon substrate or molybdenum substrate, has heat conduction and conductive capability.
As the scheme of a kind of optimization of the manufacture method of novel high-pressure LED of the present invention, described step 9) in adopt the method for laser lift-off or wet etching to peel off described growth substrates.
As the scheme of a kind of optimization of the manufacture method of novel high-pressure LED of the present invention, adopt ICP etching or the method for wet etching to etch the N-type GaN layer of described first chip, multiple quantum well layer and P type GaN layer successively from the back side, form the P electrode contact hole exposing reflective metal layer.
As the scheme of a kind of optimization of the manufacture method of novel high-pressure LED of the present invention, described growth substrates is Sapphire Substrate
As mentioned above, the manufacture method of novel high-pressure LED of the present invention, described manufacture method comprises: in growth substrates, carry out epitaxial deposition; Form isolated groove; Mesa mesa etch, formation reflective metal layer; Form isolating metal layer; Form the first insulating barrier; Form interconnect metal; Form the second insulating barrier; Form bonding metal layer; Bonding thermal conductive substrate; Remove sapphire growth substrate; Make the steps such as p-electrode.The present invention, by peeling off the growth substrates of low conduction, substrate luminous element being transferred to high thermal conductivity improves the heat-sinking capability of chip.The high-voltage LED that the present invention makes has the feature such as good thermal diffusivity and easy packaging effects, is applicable in Large scale processes production.
Accompanying drawing explanation
Fig. 1 is the manufacture method step 1 of novel high-pressure LED of the present invention) in the structural representation that presents.
Fig. 2 is the manufacture method step 2 of novel high-pressure LED of the present invention) in the structural representation that presents.
Fig. 3 is the manufacture method step 3 of novel high-pressure LED of the present invention) in the structural representation that presents.
Fig. 4 ~ Fig. 5 is the manufacture method step 4 of novel high-pressure LED of the present invention) in the structural representation that presents.
Fig. 6 is the manufacture method step 5 of novel high-pressure LED of the present invention) in the structural representation that presents.
Fig. 7 is the manufacture method step 6 of novel high-pressure LED of the present invention) in the structural representation that presents.
Fig. 8 is the manufacture method step 7 of novel high-pressure LED of the present invention) in the structural representation that presents.
Fig. 9 ~ Figure 10 is the manufacture method step 8 of novel high-pressure LED of the present invention) in the structural representation that presents.
Figure 11 ~ Figure 12 is the manufacture method step 9 of novel high-pressure LED of the present invention) in the structural representation that presents.
Figure 13 ~ Figure 14 is the manufacture method step 10 of novel high-pressure LED of the present invention) in the structural representation that presents.
Element numbers explanation
1 growth substrates
2 epitaxial loayers
21N type GaN layer
22 multiple quantum well layers
23P type GaN layer
3 isolated grooves
4 openings
5 reflective metal layers
6 isolating metal layers
7 first insulating barriers
8 interconnected windows
9 interconnect metal
10 second insulating barriers
11N electrode contact hole
12 bonding metal layers
13 thermal conductive substrate
14P electrode contact hole
15 the 3rd insulating barriers
16P electrode
Embodiment
Below by way of specific instantiation, embodiments of the present invention are described, those skilled in the art the content disclosed by this specification can understand other advantages of the present invention and effect easily.The present invention can also be implemented or be applied by embodiments different in addition, and the every details in this specification also can based on different viewpoints and application, carries out various modification or change not deviating under spirit of the present invention.
Refer to accompanying drawing.It should be noted that, the diagram provided in the present embodiment only illustrates basic conception of the present invention in a schematic way, then only the assembly relevant with the present invention is shown in graphic but not component count, shape and size when implementing according to reality is drawn, it is actual when implementing, and the kenel of each assembly, quantity and ratio can be a kind of change arbitrarily, and its assembly layout kenel also may be more complicated.
The invention provides the manufacture method of a kind of novel high-pressure LED, below in conjunction with accompanying drawing 1 ~ Figure 14, the manufacture method of the novel high-pressure LED of the embodiment of the present invention is described.Described method at least comprises following step:
First carry out step one, refer to accompanying drawing 1, growth substrates 1 is provided, at described growth substrates 1 growing epitaxial layers 2, the P type GaN layer 23 that described epitaxial loayer 2 comprises N-type GaN layer 21, grows the multiple quantum well layer 22 on described N-type GaN layer 21 surface and grow on described multiple quantum well layer 22 surface.
Described growth substrates 1 can be the low heat conductivity substrates such as Sapphire Substrate, certainly, according to technique needs, also can be that other are applicable to making the substrate of LED chip, such as spinelle (MgAl
2o
4), SiC, ZnS, ZnO or GaAs substrate etc., do not limit at this.Growth substrates 1 described in the present embodiment is preferably Sapphire Substrate.The technique of epitaxial growth N-type GaN layer 21, multiple quantum well layer 22 and P type GaN layer 23 is common process, and this is no longer going to repeat them.
Next performs step 2, refers to accompanying drawing 2, etches described epitaxial loayer 2, forms the isolated groove 3 exposing described growth substrates 2, makes described epitaxial loayer 2 form multiple separate chip.
In this step, can by adopting the methods such as ICP etch process or laser scribing split to epitaxial loayer 2, epitaxial loayer 2 is formed isolated groove 3, the degree of depth of isolated groove 3 to growth substrates 1 surface, expose growth substrates 1, epitaxial loayer 2 arranges described isolated groove 3, described epitaxial loayer 2 is made to form multiple chip that is mutually independent, can cascaded structure be formed subsequently through the plurality of chip of interconnect metal, these chips comprise first chip in cascaded structure, second chip ..., most end chip.Conveniently illustrate, in accompanying drawing 2, only draw 3 chips, from left to right can represent first chip, intermediate chip and most end chip successively.
It should be noted that, described isolated groove 3 is generally in inverted trapezoidal structure wide at the top and narrow at the bottom.In order to illustrate conveniently, the isolated groove 3 in accompanying drawing 2 ~ Figure 14 is all drawn as the rectangular configuration of sidewalls orthogonal.
Then perform step 3, referring again to accompanying drawing 3, etch the epitaxial loayer 2 of each chip, form the opening 4 exposing described N-type GaN layer 21.
As shown in Figure 3, dry etching or wet-etching technology can be adopted to etch independently each chip, formed at each chip surface and run through P type GaN layer 23, multiple quantum well layer 22 until the opening 4 on N-type GaN layer 21 surface.
In the present embodiment, adopt dry etch process, such as ICP or PIE technique etches, and does not carve and wears described N-type GaN layer 21, forms the opening 4 exposing described N-type GaN layer 21.
Then perform step 4, refer to accompanying drawing 4 ~ Fig. 5, form reflective metal layer 5 on described P type GaN layer 23 surface, described reflective metal layer 5 covers isolating metal layer 6.
Evaporation and negative glue lift-off technology or evaporation and lithographic technique can be adopted to form reflective metal layer 5 on the surface of P type GaN layer 23.In the present embodiment, excellent employing evaporation and negative glue lift-off technology is selected to form reflective metal layer 5 on the surface of P type GaN layer 23.First bear glue in device surface spin coating, and graphical described negative glue, adopt evaporation process deposit reflective metal material afterwards, then by negative glue released part reflective metal material, obtain the reflective metal layer 5 on desired location (i.e. P type GaN layer 23 surface).
The material of described reflective metal layer 5 adopts one or more the combination in Ni, A, Ti, Pt or Au, and thickness range is
in the present embodiment, the material of described reflective metal layer 5 can be preferably Ni/Ag/Ti/Pt/Au, and the sandwich construction of formation, thickness is elected as temporarily
described reflective metal layer 5 adopts multiple layer metal in order to take into account speculum, current spread and thermal louver performance.
Evaporation and negative glue lift-off technology or evaporation and lithographic technique isolating metal layer 6 can be adopted.In the present embodiment, excellent employing evaporation and negative glue lift-off technology is selected to form isolating metal layer 6.First bear glue in device surface spin coating, and graphical described negative glue, adopt evaporation process depositing metal material afterwards, then by negative glue released part metal material, obtain the isolating metal layer 6 of desired location.Formed isolating metal layer 6 by the surface of described reflective metal layer 5 and side all coated, for the protection of reflective metal layer 5.
Then step 5 is performed, please continue to refer to accompanying drawing 6, at described epitaxial loayer 2 and isolating metal layer 6 surface coverage first insulating barrier 7, the surperficial perforate of first insulating barrier 7 in described opening 4, expose described N-type GaN layer 23, simultaneously in the surperficial perforate of described first insulating barrier 7, form the interconnected window 8 exposing described isolating metal layer 6, wherein isolating metal layer 6 surface not perforate described in first chip.
Described first insulating barrier 7 is selected from SiO
2, Si
3the material stack layers that one or more materials in N4 or DBR are formed.In the present embodiment, described first insulating barrier 7 is SiO
2material.
The shape and size of described interconnected window 8 are not limit.Isolating metal layer 6 surface not perforate described in first chip refers to the chip surface not opening of cascaded structure wherein one end.In the present embodiment, accompanying drawing 6 illustrates first left chip surface not opening.
Then perform step 6, referring again to accompanying drawing 7, in described first insulating barrier 7 surface, opening 4 and interconnected window 8, fill interconnect metal 9, the isolating metal layer 6 of adjacent chips is electrically connected with N-type GaN layer 21, forms cascaded structure.
As shown in Figure 7, by interconnect metal 9, the N-type GaN layer of first chip 21 and the isolating metal layer 6 of intermediate chip are electrically connected, the N-type GaN layer 21 of intermediate chip is electrically connected with the isolating metal layer 6 of most end chip.The interconnect metal 9 of every two chips of mutually connecting is mutually independent, and avoids short circuit.
The material of described interconnect metal 9 is one or more the combination in Cr, Al, Ti, Ni, Pt or Au, and thickness range is
in the present embodiment, the material of described interconnect metal 9 can be preferably Cr/Al/Ti/Pt/Au, and the sandwich construction of formation, thickness is elected as temporarily
It should be noted that, after forming described interconnect metal 9, described isolated groove 3 comprises the first insulating barrier 7 and is formed in the interconnect metal 9 on the first insulating barrier 7 surface.Described first insulating barrier 7 and interconnect metal 9 form Omni-directional reflector (OmniDirectionReflection, ODR) structure, make described isolated groove 3 become reflective trenches, have better reflectivity.
Perform step 7 again, as shown in Figure 8, at described first insulating barrier 7 and interconnect metal 9 surface coverage second insulating barrier 10, wherein, the second insulating barrier 10 of most end chip surface forms N electrode contact hole 11.
Described second insulating barrier 10 is selected from SiO
2, Si
3the material stack layers that one or more materials in N4 or DBR are formed.In the present embodiment, described second insulating barrier 10 is SiO
2material.
The shape and size of described N electrode contact hole 11 are not limit.Described N electrode contact hole 11 is electrically drawn for the follow-up N-type GaN layer 21 by most end chip.
Perform step 8 again, as shown in Fig. 9 ~ Figure 10, described second insulating barrier 10 and interconnect metal 9 surface and isolated groove 3 in cover bonding metal layer 12, structure step 7 obtained by described bonding metal layer 12 and thermal conductive substrate 13 bonding.
Described bonding metal layer 12 not only has adhesiveness but also have conductivity, the N-type GaN layer 21 of most end chip is electrically drawn by described bonding metal layer 12 and interconnect metal 9.
Described thermal conductive substrate 13 needs both have high thermal conductivity, also needs electric conductivity, can be metal substrate or nonmetallic substrate.Such as, described thermal conductive substrate 13 can be the conductive and heat-conductive substrates such as metal substrate, silicon substrate or molybdenum substrate, certainly, also can be other suitable backing materials.By described thermal conductive substrate 13, the heat-sinking capability of LED component can be strengthened.
Then perform step 9, as shown in Figure 11 ~ Figure 12, peel off described growth substrates 1, etch the N-type GaN layer 21 of described first chip, multiple quantum well layer 22 and P type GaN layer 23 from the back side successively, form the P electrode contact hole 14 exposing reflective metal layer 5.
The method of laser lift-off or wet etching can be adopted to peel off described growth substrates 1.Another surface of the N-type GaN layer 21 of all chips is exposed after peeling off described growth substrates 1.
ICP can be adopted to etch or the method for wet etching etches the N-type GaN layer 21 of described first chip, multiple quantum well layer 22 and P type GaN layer 23 successively from the back side, form the P electrode contact hole 14 exposing reflective metal layer 5.Described P electrode contact hole 14 for follow-up formation P electrode, the P type GaN layer 23 of first chip is electrically drawn.
Finally perform step 10, as shown in Figure 13 ~ Figure 14, form the 3rd insulating barrier 15, etch the 3rd insulating barrier 15 in described P electrode contact hole 14, in described P electrode contact hole 14, fill the P electrode 16 be electrically connected with the reflective metal layer 5 of first chip.
Described 3rd insulating barrier 15 is selected from SiO
2, Si
3the material stack layers that one or more materials in N4 or DBR are formed.In the present embodiment, described 3rd insulating barrier 15 is SiO
2material.
All chips forms cascaded structure, is electrically drawn by the P type GaN layer 23 of P electrode 16 by first chip, is electrically drawn, thus complete the making of the present embodiment high-voltage LED by thermal conductive substrate 13 and the bonding metal layer 12 N-type GaN layer 21 by most end chip.
In sum, the invention provides the manufacture method of a kind of novel high-pressure LED, described manufacture method comprises: in growth substrates, carry out epitaxial deposition; Form isolated groove; Mesa mesa etch, formation reflective metal layer; Form isolating metal layer; Form the first insulating barrier; Form interconnect metal; Form the second insulating barrier; Form bonding metal layer; Bonding thermal conductive substrate; Remove sapphire growth substrate; Make the steps such as p-electrode.The present invention, by peeling off the growth substrates of low conduction, substrate luminous element being transferred to high thermal conductivity improves the heat-sinking capability of chip.The high-voltage LED that the present invention makes has the feature such as good thermal diffusivity and easy packaging effects, is applicable in Large scale processes production.
So the present invention effectively overcomes various shortcoming of the prior art and tool high industrial utilization.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any person skilled in the art scholar all without prejudice under spirit of the present invention and category, can modify above-described embodiment or changes.Therefore, such as have in art usually know the knowledgeable do not depart from complete under disclosed spirit and technological thought all equivalence modify or change, must be contained by claim of the present invention.
Claims (10)
1. a manufacture method of novel high-pressure LED, is characterized in that, described manufacture method at least comprises:
1) growth substrates is provided, at described growth substrates growing epitaxial layers, the P type GaN layer that described epitaxial loayer comprises N-type GaN layer, grows the multiple quantum well layer on described N-type GaN layer surface and grow on described multiple quantum well layer surface;
2) etch described epitaxial loayer, form the isolated groove exposing described growth substrates, make described epitaxial loayer form multiple separate chip;
3) etch the epitaxial loayer of each chip, form the opening exposing described N-type GaN layer;
4) form reflective metal layer on described P type GaN layer surface, described reflective metal layer covers isolating metal layer;
5) at described epitaxial loayer and isolating metal layer surface coverage first insulating barrier, first surface of insulating layer perforate in said opening, expose described N-type GaN layer, simultaneously in described first surface of insulating layer perforate, form the interconnected window exposing described isolating metal layer, wherein isolating metal layer surface not perforate described in first chip;
6) in described first surface of insulating layer, opening and interconnected window, fill interconnect metal, the isolating metal layer of adjacent chips and N-type GaN layer are electrically connected, form cascaded structure;
7) at described first insulating barrier and interconnect metal surface coverage second insulating barrier, wherein, the second insulating barrier of most end chip surface forms N electrode contact hole;
8) in described second insulating barrier and interconnect metal surface and isolated groove, bonding metal layer is covered, by described bonding metal layer by step 7) structure that obtains and thermal conductive substrate bonding;
9) peel off described growth substrates, etch the N-type GaN layer of described first chip, multiple quantum well layer and P type GaN layer from the back side successively, form the P electrode contact hole exposing reflective metal layer;
10) form the 3rd insulating barrier, etch the 3rd insulating barrier in described P electrode contact hole, in described P electrode contact hole, fill the P electrode be electrically connected with the reflective metal layer of first chip.
2. the manufacture method of novel high-pressure LED according to claim 1, is characterized in that: described step 2) in adopt ICP etching or the method split of laser scribing to form described isolated groove, described isolated groove is inverted trapezoidal structure.
3. the manufacture method of novel high-pressure LED according to claim 1, is characterized in that: the material of described reflective metal layer is one or more the combination in Ni, A, Ti, Pt or Au, and thickness range is
4. the manufacture method of novel high-pressure LED according to claim 1, is characterized in that: the material of described interconnect metal is one or more the combination in Cr, Al, Ti, Ni, Pt or Au, and thickness range is
5. the manufacture method of novel high-pressure LED according to claim 1, is characterized in that: the interconnect metal in described isolated groove and the first insulating barrier form ODR structure, makes described isolated groove become reflective trenches.
6. the manufacture method of novel high-pressure LED according to claim 1, is characterized in that: described first insulating barrier, the second insulating barrier and the 3rd insulating barrier are selected from SiO
2, Si
3the material stack layers that one or more materials in N4 or DBR are formed.
7. the manufacture method of novel high-pressure LED according to claim 1, is characterized in that: described thermal conductive substrate is metal substrate, silicon substrate or molybdenum substrate.
8. the manufacture method of novel high-pressure LED according to claim 1, is characterized in that: described step 9) in adopt the method for laser lift-off or wet etching to peel off described growth substrates.
9. the manufacture method of novel high-pressure LED according to claim 1, it is characterized in that: the method for employing ICP etching or wet etching etches the N-type GaN layer of described first chip, multiple quantum well layer and P type GaN layer successively from the back side, form the P electrode contact hole exposing reflective metal layer.
10. the manufacture method of novel high-pressure LED according to claim 1, is characterized in that: described growth substrates is Sapphire Substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610074657.1A CN105552180B (en) | 2016-02-02 | 2016-02-02 | A kind of production method of novel high-pressure LED |
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| CN106410007A (en) * | 2016-09-22 | 2017-02-15 | 佛山市国星半导体技术有限公司 | Bilayer-electrode LED chip and manufacturing method thereof |
| CN106981497A (en) * | 2017-02-14 | 2017-07-25 | 盐城东紫光电科技有限公司 | A kind of high pressure flip LED chips structure and its manufacture method |
| CN107046228A (en) * | 2017-04-07 | 2017-08-15 | 华南师范大学 | A kind of Electroabsorption Modulated Laser and preparation method thereof |
| CN108305886A (en) * | 2018-03-30 | 2018-07-20 | 映瑞光电科技(上海)有限公司 | A kind of LED chip and its manufacturing method |
| CN108807612A (en) * | 2018-06-26 | 2018-11-13 | 山东浪潮华光光电子股份有限公司 | A kind of light-emitting diodes tube preparation method |
| CN108847438A (en) * | 2018-03-30 | 2018-11-20 | 映瑞光电科技(上海)有限公司 | A kind of LED chip and its manufacturing method |
| CN109979957A (en) * | 2019-03-15 | 2019-07-05 | 广东省半导体产业技术研究院 | Light emitting semiconductor device and preparation method thereof |
| CN110085619A (en) * | 2019-04-30 | 2019-08-02 | 厦门乾照光电股份有限公司 | A kind of vertical high voltage light-emitting diode chip for backlight unit and preparation method thereof |
| CN110190086A (en) * | 2019-06-05 | 2019-08-30 | 广东省半导体产业技术研究院 | High voltage direct current LED or AC LED and its manufacturing method |
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| CN110491981A (en) * | 2019-08-14 | 2019-11-22 | 佛山市国星半导体技术有限公司 | A kind of high-power flip LED chips and preparation method thereof |
| CN111778561A (en) * | 2020-06-22 | 2020-10-16 | 福建晶安光电有限公司 | Sapphire substrate, processing method and preparation method of light-emitting diode |
| US10861834B2 (en) | 2018-03-08 | 2020-12-08 | Kunshan New Flat Panel Display Technology Center Co., Ltd. | Micro-LED chips, display screens and methods of manufacturing the same |
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| CN117637973A (en) * | 2024-01-25 | 2024-03-01 | 江西兆驰半导体有限公司 | LED chip and preparation method thereof |
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| CN106410007A (en) * | 2016-09-22 | 2017-02-15 | 佛山市国星半导体技术有限公司 | Bilayer-electrode LED chip and manufacturing method thereof |
| CN106410007B (en) * | 2016-09-22 | 2019-07-19 | 佛山市国星半导体技术有限公司 | A kind of two-layer electrode LED chip and preparation method thereof |
| CN113921687A (en) * | 2016-12-21 | 2022-01-11 | 首尔伟傲世有限公司 | High-reliability light-emitting diode |
| CN106981497A (en) * | 2017-02-14 | 2017-07-25 | 盐城东紫光电科技有限公司 | A kind of high pressure flip LED chips structure and its manufacture method |
| CN107046228B (en) * | 2017-04-07 | 2019-08-06 | 华南师范大学 | A kind of Electroabsorption Modulated Laser and preparation method thereof |
| CN107046228A (en) * | 2017-04-07 | 2017-08-15 | 华南师范大学 | A kind of Electroabsorption Modulated Laser and preparation method thereof |
| US10861834B2 (en) | 2018-03-08 | 2020-12-08 | Kunshan New Flat Panel Display Technology Center Co., Ltd. | Micro-LED chips, display screens and methods of manufacturing the same |
| CN110246931A (en) * | 2018-03-08 | 2019-09-17 | 昆山工研院新型平板显示技术中心有限公司 | A kind of Micro-LED chip, display screen and preparation method |
| CN108305886A (en) * | 2018-03-30 | 2018-07-20 | 映瑞光电科技(上海)有限公司 | A kind of LED chip and its manufacturing method |
| CN108847438A (en) * | 2018-03-30 | 2018-11-20 | 映瑞光电科技(上海)有限公司 | A kind of LED chip and its manufacturing method |
| CN108807612A (en) * | 2018-06-26 | 2018-11-13 | 山东浪潮华光光电子股份有限公司 | A kind of light-emitting diodes tube preparation method |
| CN109979957B (en) * | 2019-03-15 | 2024-05-17 | 广东省半导体产业技术研究院 | Semiconductor light emitting device and method of manufacturing the same |
| CN109979957A (en) * | 2019-03-15 | 2019-07-05 | 广东省半导体产业技术研究院 | Light emitting semiconductor device and preparation method thereof |
| CN110085619B (en) * | 2019-04-30 | 2021-04-27 | 厦门乾照光电股份有限公司 | Vertical high-voltage light-emitting diode chip and manufacturing method thereof |
| CN110085619A (en) * | 2019-04-30 | 2019-08-02 | 厦门乾照光电股份有限公司 | A kind of vertical high voltage light-emitting diode chip for backlight unit and preparation method thereof |
| CN110190086B (en) * | 2019-06-05 | 2021-07-27 | 广东省半导体产业技术研究院 | High-voltage direct-current LED or alternating-current LED and manufacturing method thereof |
| CN110190086A (en) * | 2019-06-05 | 2019-08-30 | 广东省半导体产业技术研究院 | High voltage direct current LED or AC LED and its manufacturing method |
| CN110491981A (en) * | 2019-08-14 | 2019-11-22 | 佛山市国星半导体技术有限公司 | A kind of high-power flip LED chips and preparation method thereof |
| CN111778561A (en) * | 2020-06-22 | 2020-10-16 | 福建晶安光电有限公司 | Sapphire substrate, processing method and preparation method of light-emitting diode |
| CN111778561B (en) * | 2020-06-22 | 2021-11-02 | 福建晶安光电有限公司 | Sapphire substrate, processing method and preparation method of light-emitting diode |
| CN117637973A (en) * | 2024-01-25 | 2024-03-01 | 江西兆驰半导体有限公司 | LED chip and preparation method thereof |
| CN117637973B (en) * | 2024-01-25 | 2024-04-05 | 江西兆驰半导体有限公司 | LED chip and preparation method thereof |
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