CN105552180B - A kind of production method of novel high-pressure LED - Google Patents
A kind of production method of novel high-pressure LED Download PDFInfo
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- CN105552180B CN105552180B CN201610074657.1A CN201610074657A CN105552180B CN 105552180 B CN105552180 B CN 105552180B CN 201610074657 A CN201610074657 A CN 201610074657A CN 105552180 B CN105552180 B CN 105552180B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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Abstract
The present invention provides a kind of production method of novel high-pressure LED, and the production method includes：Epitaxial deposition is carried out in growth substrates；Form isolated groove；Mesa mesa etch forms reflective metal layer；Form isolating metal layer；Form the first insulating layer；Form interconnection metal；Form second insulating layer；Form bonding metal layer；It is bonded thermal conductive substrate；Remove sapphire growth substrate；Making p-electrode and etc..Illuminator is transferred to the heat-sinking capability that chip is improved on the substrate of high thermal conductivity by the present invention by removing the growth substrates of low conduction.The high-voltage LED that the present invention makes has the characteristics that good thermal diffusivity and easy packaging effects, suitable for Large scale processes production.
Description
Technical field
The present invention relates to LED manufacture technology field, more particularly to a kind of production method of novel high-pressure LED.
Background technology
Light emitting diode (Light Emitting Diode, abbreviation LED) is a kind of light emitting semiconductor device, by gallium (Ga)
It forms with the compound of arsenic (As), phosphorus (P), nitrogen (N), indium (In), is made using semiconductor P-N junction electroluminescent principle.LED with
The high and low power consumption of its brightness, long lifespan start fast, power is small, without stroboscopic, do not allow to be also easy to produce regarding visual fatigue the advantages that, become new
Generation light source is preferred.
With the continuous development of industry, LED chip chase more specular removal, higher power, higher reliability direction one
It walks and strides forward.And in LED application ends, main occuping market is still small-power and middle power chip, high-power chip by
Only have fewer companies to set foot in yield issues.
Many Novel LED chips are appeared in the public visual field in recent years, mesohigh (High voltage) LED, with it
Efficiency is better than general conventional low LED, is concerned.High-voltage LED is efficient to be mainly due to low current, multiunit design energy
Uniformly current spread is opened, and high-voltage LED can realize that direct voltage drives, so as to save the cost of LED drivings.It is existing
High voltage LED chip increase there is power, the problem of heat dissipation is difficult and reliability reduces.
For heat dissipation problem, industry has gone out further improvement to the structure of high voltage LED chip.For example, number of patent application
The thermal diffusivity of chip is increased using the method for increasing heating column for 201510022007.8.But the method technique realizes difficulty
Height is not easy to be widely used in mass producing.
Therefore it provides a kind of production method of novel high-pressure LED, which is those skilled in the art, needs the subject solved.
Invention content
In view of the foregoing deficiencies of prior art, the purpose of the present invention is to provide a kind of making of novel high-pressure LED
Method, the problems such as solving prior art high-voltage LED heat dissipation difficult, complex process.
In order to achieve the above objects and other related objects, the present invention provides a kind of production method of novel high-pressure LED, described
Production method includes at least：
1) growth substrates are provided, in the growth substrates growing epitaxial layers, the epitaxial layer includes N-type GaN layer, growth
The N-type GaN layer surface multiple quantum well layer and be grown in the p-type GaN layer of the multiple quantum wells layer surface；
2) epitaxial layer is etched, the isolated groove of the exposure growth substrates is formed, forms the epitaxial layer multiple
Mutually independent chip；
3) epitaxial layer of each chip is etched, forms the opening of the exposure N-type GaN layer；
4) reflective metal layer is formed on the p-type GaN layer surface, isolating metal layer is covered on the reflective metal layer；
5) the first insulating layer is covered in the epitaxial layer and isolating metal layer surface, in said opening the first insulating layer table
Face trepanning exposes the N-type GaN layer, while in the first surface of insulating layer trepanning, the formation exposure isolating metal layer
Interconnection window, wherein isolating metal layer surface not trepanning described in first chip；
6) interconnection metal is filled in first surface of insulating layer, opening and interconnection window, makes adjacent chips
Isolating metal layer is electrically connected with N-type GaN layer, forms cascaded structure；
7) in first insulating layer and interconnection metal surface covering second insulating layer, wherein, in most end chip list
N electrode contact hole is formed in the second insulating layer in face；
8) bonding metal layer is covered in the second insulating layer and interconnection metal surface and isolated groove, passes through institute
Bonding metal layer is stated to be bonded the structure that step 7) obtains with thermal conductive substrate；
9) growth substrates are removed, N-type GaN layer, the multiple quantum well layer of first chip are sequentially etched from the back side
And p-type GaN layer, form the P electrode contact hole for exposing reflective metal layer；
10) third insulating layer is formed, the third insulating layer in the P electrode contact hole is etched, in the P electrode contact hole
The P electrode that the reflective metal layer of middle filling and first chip is electrically connected.
A kind of scheme of optimization of production method as novel high-pressure LED of the present invention, the step 2) is middle to be carved using ICP
The method that erosion or laser scribing are split forms the isolated groove, and the isolated groove is in inverted trapezoidal structure.
A kind of scheme of optimization of production method as novel high-pressure LED of the present invention, the material of the reflective metal layer
For one or more combinations in Ni, A, Ti, Pt or Au, thickness range is
A kind of scheme of optimization of production method as novel high-pressure LED of the present invention, the material of the interconnection metal
For one or more combinations in Cr, Al, Ti, Ni, Pt or Au, thickness range is
A kind of scheme of optimization of production method as novel high-pressure LED of the present invention, the interconnection in the isolated groove
Metal layer and the first insulating layer form ODR structures, and the isolated groove is made to become reflective trenches.
A kind of scheme of optimization of production method as novel high-pressure LED of the present invention, first insulating layer, second are absolutely
Edge layer and third insulating layer are selected from SiO2、Si3The material stack layers that one or more materials in N4 or DBR are formed.
A kind of scheme of optimization of production method as novel high-pressure LED of the present invention, the thermal conductive substrate are metal liner
Bottom, silicon substrate or molybdenum substrate have heat conduction and conductive capability.
A kind of scheme of optimization of production method as novel high-pressure LED of the present invention uses laser in the step 9)
The method of stripping or wet etching removes the growth substrates.
A kind of scheme of optimization of production method as novel high-pressure LED of the present invention, it is rotten using ICP etchings or wet method
The method of erosion is sequentially etched N-type GaN layer, multiple quantum well layer and the p-type GaN layer of first chip from the back side, is formed sudden and violent
Reveal the P electrode contact hole of reflective metal layer.
A kind of scheme of optimization of production method as novel high-pressure LED of the present invention, the growth substrates are sapphire
Substrate
As described above, the production method of the novel high-pressure LED of the present invention, the production method include：In growth substrates
Carry out epitaxial deposition；Form isolated groove；Mesa mesa etch forms reflective metal layer；Form isolating metal layer；Form the
One insulating layer；Form interconnection metal；Form second insulating layer；Form bonding metal layer；It is bonded thermal conductive substrate；Remove sapphire
Growth substrates；Making p-electrode and etc..Illuminator is transferred to high heat conduction by the present invention by removing the growth substrates of low conduction
The heat-sinking capability of chip is improved on the substrate of rate.The high-voltage LED that the present invention makes has good thermal diffusivity and easily encapsulation
Property the features such as, suitable for Large scale processes production.
Description of the drawings
The structure diagram presented in the production method step 1) that Fig. 1 is novel high-pressure LED of the present invention.
The structure diagram presented in the production method step 2) that Fig. 2 is novel high-pressure LED of the present invention.
The structure diagram presented in the production method step 3) that Fig. 3 is novel high-pressure LED of the present invention.
The structure diagram presented in the production method step 4) that Fig. 4~Fig. 5 is novel high-pressure LED of the present invention.
The structure diagram presented in the production method step 5) that Fig. 6 is novel high-pressure LED of the present invention.
The structure diagram presented in the production method step 6) that Fig. 7 is novel high-pressure LED of the present invention.
The structure diagram presented in the production method step 7) that Fig. 8 is novel high-pressure LED of the present invention.
The structure diagram presented in the production method step 8) that Fig. 9~Figure 10 is novel high-pressure LED of the present invention.
The structure diagram presented in the production method step 9) that Figure 11~Figure 12 is novel high-pressure LED of the present invention.
The structure diagram presented in the production method step 10) that Figure 13~Figure 14 is novel high-pressure LED of the present invention.
Component label instructions
1 growth substrates
2 epitaxial layers
21 N-type GaN layers
22 multiple quantum well layers
23 p-type GaN layers
3 isolated grooves
4 openings
5 reflective metal layers
6 isolating metal layers
7 first insulating layers
8 interconnection windows
9 interconnection metals
10 second insulating layers
11 N electrode contact holes
12 bonding metal layers
13 thermal conductive substrates
14 P electrode contact holes
15 third insulating layers
16 P electrodes
Specific embodiment
Illustrate embodiments of the present invention below by way of specific specific example, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the present invention easily.The present invention can also pass through in addition different specific realities
The mode of applying is embodied or practiced, the various details in this specification can also be based on different viewpoints with application, without departing from
Various modifications or alterations are carried out under the spirit of the present invention.
Please refer to attached drawing.It should be noted that the diagram provided in the present embodiment only illustrates the present invention in a schematic way
Basic conception, component count, shape when only display is with related component in the present invention rather than according to actual implementation in schema then
Shape and size are drawn, and kenel, quantity and the ratio of each component can be a kind of random change during actual implementation, and its component cloth
Office's kenel may also be increasingly complex.
The present invention provides a kind of production method of novel high-pressure LED, below in conjunction with the accompanying drawings 1~Figure 14, and the present invention is implemented
The production method of the novel high-pressure LED of example illustrates.The method includes at least following steps：
Step 1 is carried out first, please refers to attached drawing 1, growth substrates 1 are provided, in 1 growing epitaxial layers of growth substrates
2, the epitaxial layer 2 includes N-type GaN layer 21, is grown in the multiple quantum well layer 22 on 21 surface of N-type GaN layer and is grown in
The p-type GaN layer 23 on 22 surface of multiple quantum well layer.
The growth substrates 1 can be the low heat conductivities substrate such as Sapphire Substrate, certainly, can also according to technique needs
It is the substrate that other are suitble to make LED chip, such as spinelle (MgAl2O4), SiC, ZnS, ZnO or GaAs substrate etc., herein
It is unlimited.Growth substrates 1 described in the present embodiment are preferably Sapphire Substrate.Epitaxial growth N-type GaN layer 21, multiple quantum well layer 22
And the technique of p-type GaN layer 23 is common process, this is no longer going to repeat them.
Secondly perform step 2, please refer to attached drawing 2, etch the epitaxial layer 2, formed the exposure growth substrates 2 every
From groove 3, the epitaxial layer 2 is made to form multiple mutually independent chips.
In this step, can be by being split to epitaxial layer 2 using ICP etch process or laser scribing the methods of, in epitaxial layer 2
Upper formation isolated groove 3, the depth of isolated groove 3 are set to 1 surface of growth substrates, exposing growth substrates 1 on epitaxial layer 2
The isolated groove 3 makes the epitaxial layer 2 form multiple chips that are mutually independent, multiple subsequently through interconnection metal
Chip can form cascaded structure, these chips include cascaded structure in first chip, second chip ..., most end
Tail chip.3 chips are only drawn in order to facilitate diagram, in attached drawing 2, can from left to right represent first chip, centre successively
Chip and most end chip.
It should be noted that the general inverted trapezoidal structure with a narrow upper and lower width of the isolated groove 3.It is attached in order to illustrate conveniently
Isolated groove 3 in Fig. 2~Figure 14 is drawn as the vertical rectangular configuration of side wall.
Then step 3 is performed, referring again to attached drawing 3, etches the epitaxial layer 2 of each chip, forms the exposure N-type GaN
The opening 4 of layer 21.
Each independent chip is performed etching as shown in figure 3, dry etching or wet-etching technology may be used,
It is formed in each chip surface through p-type GaN layer 23, multiple quantum well layer 22 until the opening 4 on 21 surface of N-type GaN layer.
It in the present embodiment, is performed etching using dry etch process, such as ICP PIE techniques, etching does not cut through described
N-type GaN layer 21 forms the opening 4 of the exposure N-type GaN layer 21.
Then step 4 is performed, please refers to 4~Fig. 5 of attached drawing, reflective metal layer 5 is formed on 23 surface of p-type GaN layer,
Isolating metal layer 6 is covered on the reflective metal layer 5.
Vapor deposition and negtive photoresist lift-off technology or vapor deposition may be used and lithographic technique is formed instead on the surface of p-type GaN layer 23
Penetrate metal layer 5.In the present embodiment, excellent use is selected to be deposited with negtive photoresist lift-off technology in the surface of p-type GaN layer 23 formation reflective metals
Layer 5.First in device surface spin coating negtive photoresist, and the graphical negtive photoresist, reflective metal material is deposited using evaporation process later, then
By negtive photoresist released part reflective metal material, the reflective metal layer 5 on position needed for acquisition (i.e. 23 surface of p-type GaN layer).
The material of the reflective metal layer 5 uses one or more combinations in Ni, A, Ti, Pt or Au, thickness model
Enclose forIn the present embodiment, the material of the reflective metal layer 5 can be preferably Ni/Ag/Ti/Pt/Au, be formed
Multilayered structure, thickness is temporarily selected asThe reflective metal layer 5 uses multiple layer metal to take into account speculum, electric current expansion
Dissipate and radiate lamp behaviour.
Vapor deposition and negtive photoresist lift-off technology or vapor deposition and lithographic technique isolating metal layer 6 may be used.In the present embodiment, choosing
It is excellent that isolating metal layer 6 is formed using vapor deposition and negtive photoresist lift-off technology.First in device surface spin coating negtive photoresist, and it is graphical described negative
Glue deposits metal material, then by negtive photoresist released part metal material using evaporation process later, the isolation of position needed for acquisition
Metal layer 6.The isolating metal layer 6 of formation all coats on the surface of the reflective metal layer 5 and side, for protecting reflection gold
Belong to layer 5.
Then step 5 is performed, please continue to refer to attached drawing 6, in the epitaxial layer 2 and 6 surface of isolating metal layer covering first
Insulating layer 7, first insulating layer, the 7 surface trepanning in the opening 4, exposes the N-type GaN layer 23, while described first
7 surface trepanning of insulating layer forms the interconnection window 8 of the exposure isolating metal layer 6, wherein gold is isolated described in first chip
Belong to 6 surface not trepanning of layer.
First insulating layer 7 is selected from SiO2、Si3The material stack layers that one or more materials in N4 or DBR are formed.This
In embodiment, first insulating layer 7 is SiO2Material.
The shape and size of the interconnection window 8 are unlimited.6 surface not trepanning of isolating metal layer described in first chip refers to
The chip surface of cascaded structure wherein one end is not open.In the present embodiment, attached drawing 6 illustrates first left chip surface and does not open
Mouthful.
Then step 6 is performed, referring again to attached drawing 7, in 7 surface of the first insulating layer, opening 4 and interconnection window 8
Middle filling interconnection metal 9, the isolating metal layer 6 and N-type GaN layer 21 for making adjacent chips are electrically connected, and form cascaded structure.
As shown in fig. 7, by interconnection metal 9, the N-type GaN layer 21 of first chip and the isolating metal of intermediate chip
Layer 6 is electrically connected, the N-type GaN layer 21 of intermediate chip and the isolating metal layer 6 of most end chip are electrically connected.The core that each two is serially connected
The interconnection metal 9 of piece is mutually independent, and avoids short circuit.
The material of the interconnection metal 9 be Cr, Al, Ti, Ni, Pt or Au in one or more combinations, thickness
Ranging fromIn the present embodiment, the material of the interconnection metal 9 can be preferably Cr/Al/Ti/Pt/Au,
The multilayered structure of formation, thickness are temporarily selected as
It should be noted that being formed after the interconnection metal 9, the isolated groove 3 includes 7 He of the first insulating layer
It is formed in the interconnection metal 9 on 7 surface of the first insulating layer.First insulating layer 7 and interconnection metal 9 form comprehensive reflection
Mirror (Omni Direction Reflection, ODR) structure makes the isolated groove 3 become reflective trenches, has better
Reflectivity.
Step 7 is performed again, as shown in figure 8, in the second insulation of first insulating layer 7 and the covering of 9 surface of interconnection metal
Layer 10, wherein, N electrode contact hole 11 is formed in the second insulating layer 10 of most end chip surface.
The second insulating layer 10 is selected from SiO2、Si3The material stack layers that one or more materials in N4 or DBR are formed.This
In embodiment, the second insulating layer 10 is SiO2Material.
The shape and size of the N electrode contact hole 11 are unlimited.The N electrode contact hole 11 is used for subsequently by most end core
The N-type GaN layer 21 of piece is electrically drawn.
Perform step 8 again, as shown in Fig. 9~Figure 10, the second insulating layer 10 and 9 surface of interconnection metal and every
From bonding metal layer 12 is covered in groove 3, pass through the structure that the bonding metal layer 12 obtains step 7 and thermal conductive substrate 13
Bonding.
The bonding metal layer 12 had not only had adhesiveness again conductive, passes through the bonding metal layer 12 and interconnection is golden
Belong to layer 9 electrically to draw the N-type GaN layer 21 of most end chip.
The thermal conductive substrate 13 need both have high thermal conductivity, it is also necessary to have conductivity, can be metal substrate or
Nonmetallic substrate.For example, the thermal conductive substrate 13 can be the conductive and heat-conductives substrates such as metal substrate, silicon substrate or molybdenum substrate,
It is of course also possible to it is other suitable substrate materials.By the thermal conductive substrate 13, the heat-sinking capability of LED component can be enhanced.
Then step 9 is performed, as shown in Figure 11~Figure 12, removes the growth substrates 1, is sequentially etched from the back side described
N-type GaN layer 21, multiple quantum well layer 22 and the p-type GaN layer 23 of first chip form the P electrode of exposure reflective metal layer 5
Contact hole 14.
The method that laser lift-off or wet etching may be used removes the growth substrates 1.Remove the growth substrates 1
Expose another surface of the N-type GaN layer 21 of all chips afterwards.
The method that ICP etchings or wet etching may be used is sequentially etched the N-type GaN of first chip from the back side
Layer 21, multiple quantum well layer 22 and p-type GaN layer 23 form the P electrode contact hole 14 of exposure reflective metal layer 5.The P electrode
Contact hole 14 is for being subsequently formed P electrode, so that the p-type GaN layer 23 of first chip is electrically drawn.
Step 10 is finally performed, as shown in Figure 13~Figure 14, third insulating layer 15 is formed, etches the P electrode contact hole
Third insulating layer 15 in 14, the P that the reflective metal layer 5 of filling and first chip is electrically connected in the P electrode contact hole 14
Electrode 16.
The third insulating layer 15 is selected from SiO2、Si3The material stack layers that one or more materials in N4 or DBR are formed.This
In embodiment, the third insulating layer 15 is SiO2Material.
All chips form cascaded structure, electrically draw the p-type GaN layer 23 of first chip by P electrode 16, pass through
Thermal conductive substrate 13 and bonding metal layer 12 electrically draw the N-type GaN layer 21 of most end chip, so as to complete the present embodiment high pressure
The making of LED.
In conclusion the present invention provides a kind of production method of novel high-pressure LED, the production method includes：It is growing
Epitaxial deposition is carried out on substrate；Form isolated groove；Mesa mesa etch forms reflective metal layer；Form isolating metal layer；
Form the first insulating layer；Form interconnection metal；Form second insulating layer；Form bonding metal layer；It is bonded thermal conductive substrate；It removes
Sapphire growth substrate；Making p-electrode and etc..Illuminator is transferred to by the present invention by removing the growth substrates of low conduction
The heat-sinking capability of chip is improved on the substrate of high thermal conductivity.The high-voltage LED that the present invention makes have good thermal diffusivity and
The features such as easy packaging effects, suitable for Large scale processes production.
So the present invention effectively overcomes various shortcoming of the prior art and has high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all can carry out modifications and changes under the spirit and scope without prejudice to the present invention to above-described embodiment.Cause
This, those of ordinary skill in the art is complete without departing from disclosed spirit and institute under technological thought such as
Into all equivalent modifications or change, should by the present invention claim be covered.
Claims (10)
1. a kind of production method of novel high-pressure LED, which is characterized in that the production method includes at least：
1) growth substrates are provided, in the growth substrates growing epitaxial layers, the epitaxial layer includes N-type GaN layer, is grown in institute
It states the multiple quantum well layer on N-type GaN layer surface and is grown in the p-type GaN layer of the multiple quantum wells layer surface；
2) epitaxial layer is etched, forms the isolated groove of the exposure growth substrates, forms the epitaxial layer multiple mutual
Independent chip；
3) epitaxial layer of each chip is etched, forms the opening of the exposure N-type GaN layer；
4) reflective metal layer is formed on the p-type GaN layer surface, isolating metal layer is covered on the reflective metal layer；
5) the first insulating layer is covered in the epitaxial layer and isolating metal layer surface, the first surface of insulating layer is opened in said opening
Hole exposes the N-type GaN layer, while in the first surface of insulating layer trepanning, and formation exposes the mutual of the isolating metal layer
Join window, wherein isolating metal layer surface not trepanning described in first chip；
6) interconnection metal is filled in first surface of insulating layer, opening and interconnection window, makes the isolation of adjacent chips
Metal layer is electrically connected with N-type GaN layer, forms cascaded structure；
7) in first insulating layer and interconnection metal surface covering second insulating layer, wherein, in most end chip surface
N electrode contact hole is formed in second insulating layer；
8) bonding metal layer is covered in the second insulating layer and interconnection metal surface and isolated groove, passes through the key
The structure that step 7) obtains is bonded by metal layer with thermal conductive substrate；
9) growth substrates are removed, N-type GaN layer, multiple quantum well layer and the P of first chip are sequentially etched from the back side
Type GaN layer forms the P electrode contact hole of exposure reflective metal layer；
10) third insulating layer is formed, the third insulating layer in the P electrode contact hole is etched, is filled out in the P electrode contact hole
Fill the P electrode being electrically connected with the reflective metal layer of first chip.
2. the production method of novel high-pressure LED according to claim 1, it is characterised in that：ICP is used in the step 2)
The method that etching or laser scribing are split forms the isolated groove, and the isolated groove is in inverted trapezoidal structure.
3. the production method of novel high-pressure LED according to claim 1, it is characterised in that：The material of the reflective metal layer
Expect for one or more combinations in Ni, Ti, Pt or Au, thickness range is
4. the production method of novel high-pressure LED according to claim 1, it is characterised in that：The material of the interconnection metal
Expect for one or more combinations in Cr, Al, Ti, Ni, Pt or Au, thickness range is
5. the production method of novel high-pressure LED according to claim 1, it is characterised in that：It is mutual in the isolated groove
Join metal layer and the first insulating layer forms ODR structures, the isolated groove is made to become reflective trenches.
6. the production method of novel high-pressure LED according to claim 1, it is characterised in that：First insulating layer, second
Insulating layer and third insulating layer are selected from SiO2、Si3N4Or the material stack layers that one or more materials in DBR are formed.
7. the production method of novel high-pressure LED according to claim 1, it is characterised in that：The thermal conductive substrate is metal
Substrate or silicon substrate.
8. the production method of novel high-pressure LED according to claim 1, it is characterised in that：Using sharp in the step 9)
The method of photospallation or wet etching removes the growth substrates.
9. the production method of novel high-pressure LED according to claim 1, it is characterised in that：Using ICP etchings or wet method
The method of corrosion is sequentially etched N-type GaN layer, multiple quantum well layer and the p-type GaN layer of first chip from the back side, is formed
The P electrode contact hole of exposure reflective metal layer.
10. the production method of novel high-pressure LED according to claim 1, it is characterised in that：The growth substrates are blue precious
Stone lining bottom.
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| DE112017006432T5 (en) * | 2016-12-21 | 2019-09-05 | Seoul Viosys Co., Ltd | HIGHLY RELIABLE LUMINESCENT DIODE |
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| CN108847438A (en) * | 2018-03-30 | 2018-11-20 | 映瑞光电科技(上海)有限公司 | A kind of LED chip and its manufacturing method |
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| CN108807612A (en) * | 2018-06-26 | 2018-11-13 | 山东浪潮华光光电子股份有限公司 | A kind of light-emitting diodes tube preparation method |
| CN109979957B (en) * | 2019-03-15 | 2024-05-17 | 广东省半导体产业技术研究院 | Semiconductor light emitting device and method of manufacturing the same |
| CN110085619B (en) * | 2019-04-30 | 2021-04-27 | 厦门乾照光电股份有限公司 | Vertical high-voltage light-emitting diode chip and manufacturing method thereof |
| CN110190086B (en) * | 2019-06-05 | 2021-07-27 | 广东省半导体产业技术研究院 | High-voltage direct-current LED or alternating-current LED and manufacturing method thereof |
| CN110491981A (en) * | 2019-08-14 | 2019-11-22 | 佛山市国星半导体技术有限公司 | A kind of high-power flip LED chips and preparation method thereof |
| CN111778561B (en) * | 2020-06-22 | 2021-11-02 | 福建晶安光电有限公司 | Sapphire substrate, processing method and preparation method of light-emitting diode |
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