CN104900766A - High-voltage LED chip preparation method - Google Patents
High-voltage LED chip preparation method Download PDFInfo
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- CN104900766A CN104900766A CN201410082227.5A CN201410082227A CN104900766A CN 104900766 A CN104900766 A CN 104900766A CN 201410082227 A CN201410082227 A CN 201410082227A CN 104900766 A CN104900766 A CN 104900766A
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Abstract
The invention provides a high-voltage LED chip preparation method. The method comprises the following steps: forming a plurality of first grooves and first trenches in a part of regions of a reflection metal layer; forming a plurality of second trenches in a part of regions of a first insulating layer on the reflection metal layer; forming a plurality of third trenches in a part of regions of a current diffusion metal layer; forming a plurality of second grooves in a part of regions of a second insulating layer; and forming a plurality of fourth trenches in an N-type GaN layer. Through conductive communication of the grooves and trenches, a high-voltage chip is formed. The high-voltage LED chip obtained through the method can be driven by a high voltage directly, is free of current crowding, and is excellent in heat dissipation performance.
Description
Technical field
The invention belongs to semiconductor applications, particularly relate to a kind of preparation method of high voltage LED chip.
Background technology
Current LED(light-emitting diode) general illumination market uses traditional DC LED(direct-current LED) chip, DC LED chip generally works under big current low-voltage, for booster tension also meets the luminous flux required for illumination, general employing COB(integration packaging) structure, i.e. multiple chips connection in series-parallel.The HV LED(high-voltage LED occurred subsequently) connection in series-parallel of micromeritics is then just achieved in chip-scale, chip-scale connection in series-parallel has following advantage: one is the consistency problem that HV LED avoids COB structure medium wavelength, voltage, brightness span are brought; Two is HV LED because self operating voltage is high, easily realizes encapsulation finished product operating voltage close to civil power, improves the conversion efficiency of driving power, and because operating current is low, its line loss in finished product application also will be starkly lower than traditional DC LED chip; Three die bond and the bonding quantity being the reduction of chip, are conducive to the cost reducing encapsulation.Therefore HV LED has wide prospect of the application in illumination market.
But, each LED unit in existing high-voltage semiconductor light-emitting diode has transversary, the shortcoming of transversary LED unit to adopt that large driven current density, luminous efficiency are low, electric current is congested (currentcrowding), thermal resistance is large, therefore a kind of high-voltage semiconductor light-emitting diode is needed, can large driven current density be adopted, and improve luminous efficiency further and improve heat radiation.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of preparation method of high-voltage semi-conductor light-emitting diode, and the high-voltage chip utilizing the method to prepare can adopt large driven current density, and improves luminous efficiency, improvement heat radiation.
In order to solve technical problem of the present invention, the invention provides
oneplant the preparation method of high voltage LED chip, the method comprises on the first substrate grown buffer layer successively, N-type GaN layer, multiple quantum well layer, P type GaN layer and reflective metal layer, the subregion of described reflective metal layer is formed multiple first groove and the first groove, the degree of depth of described first groove is to N-type GaN layer, the degree of depth of described first groove is to P type GaN layer, the method is also included on described reflective metal layer and deposits one deck first insulating barrier, described first insulating barrier covers the sidewall of the first groove and described first groove, multiple second groove is formed in the subregion of described the first insulating barrier covered on reflective metal layer, the degree of depth of described second groove is to reflective metal layer, described first insulating barrier deposits one deck current spread metal level, described current spread metal level covers described first groove and the second groove, multiple 3rd groove is formed in the subregion of described current spread metal level, the degree of depth to the first insulating barrier of described 3rd groove, the method is also included on described current spread metal level and deposits first insulating layer, described second insulating barrier covers the 3rd groove, thus be communicated with the first insulating barrier, multiple second groove is formed in the subregion of described second insulating barrier, the degree of depth of described second groove is to current spread metal level, described second insulating barrier deposits one deck bonding metal layer, described bonding metal layer covers described second groove, the mode of wafer bonding is adopted to be combined with the second substrate, peel off the first substrate and resilient coating makes N-type GaN layer expose, multiple 4th groove is formed in described N-type GaN layer, the position of described 4th groove is corresponding with the first groove, the degree of depth is to reflective metal layer.
Preferably, the back side of described second substrate also deposits one deck metal layer on back.
Preferably, the material of described reflective metal layer be following in one: Ag, Al, Ni, Ni-Ag alloy, Ag-Ni alloy, Ag-Ni-Al alloy.
Preferably, the material of described first insulating barrier and the second insulating barrier be following in one or more: SiO
2, SiN, Al
2o
3.
Preferably, described method also comprises and carries out surface coarsening process to N-type GaN layer.
Preferably, the number of described first groove is at least 1.
Preferably, the number of described first groove is at least 1.
Preferably, the number of described second groove is at least 1.
Beneficial effect of the present invention:
The invention provides a kind of preparation method of high-voltage LED chip, this chip directly can adopt higher voltage drives, therefore, in the control circuit of light fixture, saves transformer, reduces costs, do not have electric current congested, by big current, excellent heat radiation performance.
Accompanying drawing explanation
Fig. 1 to Figure 10 is the schematic diagram of the preparation process of one embodiment of the invention.
Identifier declaration in figure:
1 is the first substrate, and 2 is resilient coating, and 3 is N-type GaN layer, and 4 is multiple quantum well layer, 5 is P type GaN layer, and 6 is reflective metal layer, and 7 is the first groove, 8 is the first groove, and 9 is the first insulating barrier, and 10 is the second groove, 11 is current spread metal level, and 12 is the 3rd groove, and 13 is the second insulating barrier, 14 is the second groove, and 15 is bonding metal layer, and 16 is the second substrate, 17 is metal layer on back, and 18 is the 4th groove, and 19 is P electrode.
Embodiment
As shown in Fig. 1 to Figure 10, the invention provides a kind of preparation method of high voltage LED chip.
Grown buffer layer 2, N-type GaN layer 3, multiple quantum well layer 4, P type GaN layer 5 and reflective metal layer 6 successively on the first substrate 1 as shown in Figure 1.
As shown in Figure 2, form multiple first groove 7 and the first groove 8 in the subregion of described reflective metal layer 6, the degree of depth of described first groove 7 is to N-type GaN layer 3, and the degree of depth of described first groove 8 is to P type GaN layer 5, in the present embodiment, the number of the first groove 8 is the number of the 3, first groove 7 is 4.
As shown in Figure 3, reflective metal layer 6 deposits one deck first insulating barrier 9, first insulating barrier 9 covers sidewall and first groove 8 of the first groove 7, form multiple second groove 10 in the subregion of described the first insulating barrier 9 covered on reflective metal layer 6, the degree of depth of described second groove 10 is to reflective metal layer 6.
As shown in Figure 4, first insulating barrier 9 deposits one deck current spread metal level 11, described current spread metal level 11 covers the first groove 7 and the second groove 10, multiple 3rd groove 12 is formed, the degree of depth to the first insulating barrier 9 of described 3rd groove 12 in the subregion of described current spread metal level 11.
As shown in Figure 5, current spread metal level 11 deposits first insulating layer 13, second insulating barrier 13 covers the 3rd groove 12 thus is communicated with the first insulating barrier 9, form second groove 14 in the subregion of the second insulating barrier 13, the degree of depth of described second groove 14 is to current spread metal level 11.
As shown in Figure 6, described second insulating barrier 13 deposits one deck bonding metal layer 15, and described bonding metal layer 15 covers the second groove 14.
As shown in Figure 7, the mode of wafer bonding is adopted to be combined with the second substrate 16, at second substrate 16 backside deposition one deck metal layer on back 17.Peel off the first substrate 1 and resilient coating 2 makes N-type GaN layer 3 expose, as shown in Figure 8.Form the reflective metal layer 6 of multiple 4th groove 18 exposed edge in described N-type GaN layer 3, the position of described 4th groove 18 is corresponding with the first groove 8, the 4th groove 18 degree of depth to reflective metal layer 6, as shown in Figure 9.The edge reflections metal level 6 exposed forms a P electrode 19, as shown in Figure 10.
The above; be only the embodiment in the present invention; but protection scope of the present invention is not limited thereto, any people being familiar with this technology is in the technical scope disclosed by the present invention, and the conversion that can expect easily or replace all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claims.
Claims (8)
1. a preparation method for high voltage LED chip, comprising:
Grown buffer layer, N-type GaN layer, multiple quantum well layer, P type GaN layer and reflective metal layer successively on the first substrate;
It is characterized in that, the subregion of described reflective metal layer is formed multiple first groove and the first groove, the degree of depth of described first groove is to N-type GaN layer, and the degree of depth of described first groove is to P type GaN layer;
Described reflective metal layer deposits one deck first insulating barrier, and described first insulating barrier covers the sidewall of the first groove and described first groove;
Form multiple second groove in the subregion of described the first insulating barrier covered on reflective metal layer, the degree of depth of described second groove is to reflective metal layer;
Described first insulating barrier deposits one deck current spread metal level, and described current spread metal level covers described first groove and the second groove;
Multiple 3rd groove is formed, the degree of depth to the first insulating barrier of described 3rd groove in the subregion of described current spread metal level;
Described current spread metal level deposits first insulating layer, and described second insulating barrier covers described 3rd groove and is communicated with the first insulating barrier;
Form multiple second groove in the subregion of described second insulating barrier, the degree of depth of described second groove is to current spread metal level;
Described second insulating barrier deposits one deck bonding metal layer, and described bonding metal layer covers described second groove;
The mode of wafer bonding is adopted to be combined with the second substrate;
Peel off the first substrate and resilient coating makes N-type GaN layer expose;
Form multiple 4th groove in described N-type GaN layer, the position of described 4th groove is corresponding with the first groove, and the degree of depth is to reflective metal layer.
2. the preparation method of a kind of high voltage LED chip according to claim 1, is characterized in that the back side of described second substrate also deposits one deck metal layer on back.
3. the preparation method of a kind of high voltage LED chip according to claim 1, it is characterized in that the material of described reflective metal layer be following in one: Ag, Al, Ni, Ni-Ag alloy, Ag-Ni alloy, Ag-Ni-Al alloy.
4. the preparation method of a kind of high voltage LED chip according to claim 1, it is characterized in that the material of described first insulating barrier and the second insulating barrier be following in one or more: SiO
2, SiN, Al
2o
3.
5. the preparation method of a kind of high voltage LED chip according to claim 1, is characterized in that described method also comprises and carries out surface coarsening process to N-type GaN layer.
6. the preparation method of a kind of high voltage LED chip according to claim 1, is characterized in that the number of described first groove is at least 1.
7. the preparation method of a kind of high voltage LED chip according to claim 1, is characterized in that the number of described first groove is at least 1.
8. the preparation method of a kind of high voltage LED chip according to claim 1, is characterized in that the number of described second groove is at least 1.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410082227.5A CN104900766B (en) | 2014-03-07 | 2014-03-07 | A kind of preparation method of high voltage LED chip |
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| CN201410082227.5A CN104900766B (en) | 2014-03-07 | 2014-03-07 | A kind of preparation method of high voltage LED chip |
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| CN104900766B CN104900766B (en) | 2018-03-27 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105552180A (en) * | 2016-02-02 | 2016-05-04 | 映瑞光电科技(上海)有限公司 | Fabrication method of novel high-voltage LED |
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| CN102339913A (en) * | 2011-09-30 | 2012-02-01 | 映瑞光电科技(上海)有限公司 | High-voltage LED (Light Emitting Diode) device and manufacturing method thereof |
| US20120074441A1 (en) * | 2010-09-24 | 2012-03-29 | Seoul Semiconductor Co., Ltd. | Wafer-level light emitting diode package and method of fabricating the same |
| WO2012153370A1 (en) * | 2011-05-12 | 2012-11-15 | ウェーブスクエア，インコーポレイテッド | Group iii nitride semiconductor vertical configuration led chip and method of manufacturing same |
| US20130334539A1 (en) * | 2011-03-15 | 2013-12-19 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device and method for manufacturing same |
| CN203456495U (en) * | 2013-08-12 | 2014-02-26 | 刘艳 | Led chip |
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2014
- 2014-03-07 CN CN201410082227.5A patent/CN104900766B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20120074441A1 (en) * | 2010-09-24 | 2012-03-29 | Seoul Semiconductor Co., Ltd. | Wafer-level light emitting diode package and method of fabricating the same |
| US20130334539A1 (en) * | 2011-03-15 | 2013-12-19 | Kabushiki Kaisha Toshiba | Semiconductor light emitting device and method for manufacturing same |
| WO2012153370A1 (en) * | 2011-05-12 | 2012-11-15 | ウェーブスクエア，インコーポレイテッド | Group iii nitride semiconductor vertical configuration led chip and method of manufacturing same |
| CN102339913A (en) * | 2011-09-30 | 2012-02-01 | 映瑞光电科技(上海)有限公司 | High-voltage LED (Light Emitting Diode) device and manufacturing method thereof |
| CN203456495U (en) * | 2013-08-12 | 2014-02-26 | 刘艳 | Led chip |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105552180A (en) * | 2016-02-02 | 2016-05-04 | 映瑞光电科技(上海)有限公司 | Fabrication method of novel high-voltage LED |
| CN105552180B (en) * | 2016-02-02 | 2018-06-26 | 映瑞光电科技(上海)有限公司 | A kind of production method of novel high-pressure LED |
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| CN104900766B (en) | 2018-03-27 |
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Effective date of registration: 20220127 Address after: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Patentee after: LATTICE POWER (JIANGXI) Corp. Address before: 213146 No. 7, Fengxiang Road, Wujin high tech Industrial Development Zone, Changzhou City, Jiangsu Province Patentee before: LATTICE POWER (CHANGZHOU) Corp. |
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Address after: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Patentee after: Jingneng optoelectronics Co.,Ltd. Address before: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Patentee before: LATTICE POWER (JIANGXI) Corp. |