CN104900766B - A kind of preparation method of high voltage LED chip - Google Patents
A kind of preparation method of high voltage LED chip Download PDFInfo
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- CN104900766B CN104900766B CN201410082227.5A CN201410082227A CN104900766B CN 104900766 B CN104900766 B CN 104900766B CN 201410082227 A CN201410082227 A CN 201410082227A CN 104900766 B CN104900766 B CN 104900766B
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Abstract
The present invention provides a kind of preparation method of high voltage LED chip, this method, which is included on the subregion of reflective metal layer, forms multiple first grooves and first groove, the subregion of the first insulating barrier on reflective metal layer forms multiple second grooves, multiple 3rd grooves are formed in the subregion of current spread metal level, multiple second grooves are formed in the subregion of the second insulating barrier, multiple 4th grooves are formed in N-type GaN layer.By these grooves and groove conductive communication, high-voltage chip is formed.High voltage LED chip obtained by this method can directly use higher voltage drives, not have electric current congestion, excellent heat radiation performance.
Description
Technical field
The invention belongs to semiconductor applications, more particularly to a kind of preparation method of high voltage LED chip.
Background technology
LED at present（Light emitting diode）Traditional DC LED are used on general illumination market（Direct-current LED）Chip, DC
LED chip typically works under high current low-voltage, for booster tension and meets to illuminate required luminous flux, general to use
COB（Integration packaging）Structure, i.e. multiple chips connection in series-parallel.And subsequent occurrences of HV LED（High-voltage LED）It is then just real in chip-scale
The connection in series-parallel of micromeritics is showed, chip-scale connection in series-parallel has following advantage：First, HV LED avoid COB structures medium wavelength, electricity
The consistency problem that pressure, brightness span are brought；Second, HV LED because itself operating voltage is high, easily realize encapsulation finished product work
Make voltage close to civil power, improve the conversion efficiency of driving power, because operating current is low, its circuit in finished product application damages
Consumption will also be significantly lower than traditional DC LED chips；Three are the reduction of the die bond of chip and bonding quantity, advantageously reduce encapsulation
Cost.Therefore HV LED have wide prospect of the application in illumination market.
But each LED unit in existing high-voltage semiconductor light emitting diode has transversary, lateral junction
The shortcomings that structure LED unit is can not to use low large driven current density, luminous efficiency, electric current congestion (currentcrowding), thermal resistance
It is big etc., it is therefore desirable to a kind of high-voltage semiconductor light emitting diode, large driven current density can be used, and further improved luminous
Efficiency and improvement are radiated.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of preparation method of high-voltage semi-conductor light emitting diode, utilize
High-voltage chip prepared by this method can use large driven current density, and improve luminous efficiency, improve radiating.
In order to solve the technical problem of the present invention, the present invention provides a kind of preparation method of high voltage LED chip, this method bag
Grown buffer layer, N-type GaN layer, multiple quantum well layer, p-type GaN layer and reflective metal layer successively on the first substrate are included, described
Form multiple first grooves and first groove on the subregion of reflective metal layer, the depth of first groove to N-type GaN
Layer, for the depth of the first groove to p-type GaN layer, it is exhausted that this method also includes one layer first of the deposition on the reflective metal layer
Edge layer, first insulating barrier cover the side wall of the first groove and the first groove, and reflective metal layer is covered in described
On the subregion of the first insulating barrier form multiple second grooves, the depth of the second groove is to reflective metal layer, in institute
State on the first insulating barrier one layer of current spread metal level of deposition, the current spread metal level covers first groove and the
Two grooves, form multiple 3rd grooves in the subregion of the current spread metal level, the depth of the 3rd groove to
One insulating barrier, this method also include depositing first insulating layer, second insulating barrier on the current spread metal level
The 3rd groove is covered, so as to be connected with the first insulating barrier, it is recessed to form multiple second in the subregion of second insulating barrier
Groove, the depth of second groove deposit one layer of bonding metal layer, institute to current spread metal level on second insulating barrier
State bonding metal layer and cover second groove, combined by the way of wafer bonding with the second substrate, peel off the first substrate
N-type GaN layer is exposed with cushion, multiple 4th grooves are formed in the N-type GaN layer, the position of the 4th groove and the
One groove is corresponding, depth to reflective metal layer.
Preferably, the back side of second substrate has also deposited one layer of metal layer on back.
Preferably, the material of the reflective metal layer is one of the following：Ag, Al, Ni, Ni-Ag alloy, Ag-Ni are closed
Gold, Ag-Ni-Al alloys.
Preferably, the material of first insulating barrier and the second insulating barrier is one of the following or a variety of：SiO2、SiN、
Al2O3。
Preferably, methods described also includes carrying out surface coarsening processing to N-type GaN layer.
Preferably, the number of the first groove is at least 1.
Preferably, the number of first groove is at least 1.
Preferably, the number of second groove is at least 1.
Beneficial effects of the present invention：
The present invention provides a kind of preparation method of high-voltage LED chip, and the chip can directly use higher voltage drives,
Therefore, in the control circuit of light fixture, save transformer, reduce cost, do not have electric current congestion, can by high current, radiating
It is excellent.
Brief description of the drawings
Fig. 1 to Figure 10 is the schematic diagram of the preparation process of one embodiment of the invention.
Identifier declaration in figure：
1 is the first substrate, and 2 be cushion, and 3 be N-type GaN layer, and 4 be multiple quantum well layer, and 5 be p-type GaN layer, and 6 be reflection gold
Belong to layer, 7 be the first groove, and 8 be first groove, and 9 be the first insulating barrier, and 10 be second groove, and 11 be current spread metal level, 12
It is the second insulating barrier for the 3rd groove, 13,14 be the second groove, and 15 be bonding metal layer, and 16 be the second substrate, and 17 be back-side gold
Belong to layer, 18 be the 4th groove, and 19 be P electrode.
Embodiment
As shown in Fig. 1 to Figure 10, the present invention provides a kind of preparation method of high voltage LED chip.
Grown buffer layer 2, N-type GaN layer 3, multiple quantum well layer 4, p-type GaN layer 5 successively on the first substrate 1 as shown in Figure 1
With reflective metal layer 6.
As shown in Fig. 2 form multiple first grooves 7 and first groove 8, institute in the subregion of the reflective metal layer 6
The depth of the first groove 7 is stated to N-type GaN layer 3, the depth of the first groove 8 to p-type GaN layer 5, the first ditch in the present embodiment
The number of groove 8 is 3, and the number of the first groove 7 is 4.
As shown in figure 3, depositing one layer of first insulating barrier 9 on reflective metal layer 6, it is recessed that the first insulating barrier 9 covers first
The side wall and first groove 8 of groove 7, formed in the subregion of first insulating barrier 9 being covered on reflective metal layer 6 multiple
Second groove 10, the depth of the second groove 10 to reflective metal layer 6.
As shown in figure 4, one layer of current spread metal level 11, the current spread metal level are deposited on the first insulating barrier 9
11 cover the first groove 7 and second groove 10, and multiple 3rd ditches are formed in the subregion of the current spread metal level 11
Groove 12, the depth of the 3rd groove 12 to the first insulating barrier 9.
As shown in figure 5, depositing first insulating layer 13 on current spread metal level 11, the second insulating barrier 13 covers
3rd groove 12 forms second groove 14, institute so as to be connected with the first insulating barrier 9, in the subregion of the second insulating barrier 13
The depth of the second groove 14 is stated to current spread metal level 11.
As shown in fig. 6, depositing one layer of bonding metal layer 15 on second insulating barrier 13, the bonding metal layer 15 covers
The second groove 14 is covered.
As shown in fig. 7, combined by the way of wafer bonding with the second substrate 16, in one layer of 16 backside deposition of the second substrate
Metal layer on back 17.Peeling off the first substrate 1 and cushion 2 exposes N-type GaN layer 3, as shown in Figure 8.In the N-type GaN layer 3
Form multiple 4th grooves 18 and the reflective metal layer 6 of exposed edge, the position of the 4th groove 18 are relative with first groove 8
Should, the depth of the 4th groove 18 to reflective metal layer 6, as shown in Figure 9.A P electricity is formed on exposed edge reflections metal level 6
Pole 19, as shown in Figure 10.
It is described above, it is only the embodiment in the present invention, but protection scope of the present invention is not limited thereto, and is appointed
What be familiar with the people of the technology disclosed herein technical scope in, the conversion that can readily occur in or replace should all cover
Within the protection domain of invention.Therefore, protection scope of the present invention should be defined by the protection domain of claims.
Claims (5)
1. a kind of preparation method of high voltage LED chip, including：
Grown buffer layer, N-type GaN layer, multiple quantum well layer, p-type GaN layer and reflective metal layer successively on the first substrate；
Characterized in that, multiple first grooves and multiple first grooves, institute are formed on the subregion of the reflective metal layer
The depth of the first groove is stated to N-type GaN layer, the depth of the first groove to p-type GaN layer；
On the reflective metal layer deposit one layer of first insulating barrier, first insulating barrier cover the first groove side wall and
The first groove；
The subregion of the first insulating barrier on reflective metal layer is covered in forms multiple second grooves, the second groove
Depth is to reflective metal layer；
One layer of current spread metal level is deposited on first insulating barrier, the current spread metal level covers described first
Groove and second groove；
Form multiple 3rd grooves in the subregion of the current spread metal level, the depth of the 3rd groove is to first exhausted
Edge layer；
First insulating layer is deposited on the current spread metal level, second insulating barrier covers the 3rd groove
Connected with the first insulating barrier；
Multiple second grooves are formed in the subregion of second insulating barrier, the depth of second groove is golden to current spread
Belong to layer；
One layer of bonding metal layer is deposited on second insulating barrier, the bonding metal layer covers second groove；
Combined by the way of wafer bonding with the second substrate；
Peeling off the first substrate and cushion exposes N-type GaN layer；
Multiple 4th grooves are formed in the N-type GaN layer, the position of the 4th groove is corresponding with first groove, and depth is extremely
Reflective metal layer.
A kind of 2. preparation method of high voltage LED chip according to claim 1, it is characterised in that the back of the body of second substrate
Face has also deposited one layer of metal layer on back.
3. the preparation method of a kind of high voltage LED chip according to claim 1, it is characterised in that the reflective metal layer
Material is one of the following：Ag, Al, Ni, Ni-Ag alloy, Ag-Ni-Al alloys.
A kind of 4. preparation method of high voltage LED chip according to claim 1, it is characterised in that first insulating barrier and
The material of second insulating barrier is one of the following or a variety of：SiO2、SiN、Al2O3。
A kind of 5. preparation method of high voltage LED chip according to claim 1, it is characterised in that methods described also include pair
N-type GaN layer carries out surface coarsening processing.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410082227.5A CN104900766B (en) | 2014-03-07 | 2014-03-07 | A kind of preparation method of high voltage LED chip |
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| CN201410082227.5A CN104900766B (en) | 2014-03-07 | 2014-03-07 | A kind of preparation method of high voltage LED chip |
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| CN104900766A CN104900766A (en) | 2015-09-09 |
| CN104900766B true CN104900766B (en) | 2018-03-27 |
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| CN105552180B (en) * | 2016-02-02 | 2018-06-26 | 映瑞光电科技(上海)有限公司 | A kind of production method of novel high-pressure LED |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339913A (en) * | 2011-09-30 | 2012-02-01 | 映瑞光电科技(上海)有限公司 | High-voltage LED (Light Emitting Diode) device and manufacturing method thereof |
| CN203456495U (en) * | 2013-08-12 | 2014-02-26 | 刘艳 | Led chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9070851B2 (en) * | 2010-09-24 | 2015-06-30 | Seoul Semiconductor Co., Ltd. | Wafer-level light emitting diode package and method of fabricating the same |
| JP5603813B2 (en) * | 2011-03-15 | 2014-10-08 | 株式会社東芝 | Semiconductor light emitting device and light emitting device |
| US9502603B2 (en) * | 2011-05-12 | 2016-11-22 | Wavesquare Inc. | Vertically structured group III nitride semiconductor LED chip and method for manufacturing the same |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102339913A (en) * | 2011-09-30 | 2012-02-01 | 映瑞光电科技(上海)有限公司 | High-voltage LED (Light Emitting Diode) device and manufacturing method thereof |
| CN203456495U (en) * | 2013-08-12 | 2014-02-26 | 刘艳 | Led chip |
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Effective date of registration: 20220127 Address after: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Patentee after: LATTICE POWER (JIANGXI) Corp. Address before: 213146 No. 7, Fengxiang Road, Wujin high tech Industrial Development Zone, Changzhou City, Jiangsu Province Patentee before: LATTICE POWER (CHANGZHOU) Corp. |
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Address after: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Patentee after: Jingneng optoelectronics Co.,Ltd. Address before: 330096 No. 699, Aixi Hubei Road, Nanchang High-tech Development Zone, Jiangxi Province Patentee before: LATTICE POWER (JIANGXI) Corp. |