CN108305886A - A kind of LED chip and its manufacturing method - Google Patents
A kind of LED chip and its manufacturing method Download PDFInfo
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- CN108305886A CN108305886A CN201810276826.9A CN201810276826A CN108305886A CN 108305886 A CN108305886 A CN 108305886A CN 201810276826 A CN201810276826 A CN 201810276826A CN 108305886 A CN108305886 A CN 108305886A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0093—Wafer bonding; Removal of the growth substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Abstract
The present invention provides a kind of LED chip and its manufacturing method in, it includes N-type epitaxy layer to provide one first, the epitaxial structure of quantum well layer and p-type epitaxial layer, it etches the epitaxial structure and forms the die unit being isolated by multiple isolated grooves, the part p-type epitaxial layer and quantum well layer of the etching close to the isolated groove, until exposing N-type epitaxy layer, then functional layer is formed, first insulating layer, metal connecting layer, in different directions by metal connecting layer, N-type epitaxy layer is connected with functional layer, realize the exchange design of chip unit, form the LED chip with vertical structure.The present invention realizes that exchange is integrated by forming metal interconnecting layer, in chip stage, is conducive to the operation of back segment packaging technology, while improving the heat-sinking capability and luminous efficiency of chip.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of AC-LED chips and its system based on vertical structure
Make method.
Background technology
Light emitting diode (Light Emitting Diode, abbreviation LED) is a kind of light emitting semiconductor device, by gallium (Ga)
It forms with the compound of arsenic (As), phosphorus (P), nitrogen (N), indium (In), is made using semiconductor P-N junction electroluminescent principle.LED with
The high and low power consumption of its brightness, long lifespan start fast, power is small, without stroboscopic, do not allow to be also easy to produce regarding visual fatigue the advantages that, become new
Generation light source is preferred.
Compared to traditional positive assembling structures of GaN base LED, vertical structure has good heat dissipation, can carry high current, shines strong
The advantages that degree is high, and power consumption is small, long lifespan, is widely used in general illumination, Landscape Lighting, special lighting, automotive lighting etc.
Field becomes the solution of generation high-power GaN-based LED great potential, is just more and more paid close attention to and studies by industry.
With the continuous development of industry, LED chip is chasing more high effect, higher power, higher reliability direction one
It walks and strides forward.And in LED application ends, main occuping market is still small-power and middle power chip, high-power chip by
Only have fewer companies to set foot in yield issues.
Existing packing forms are usually that single LED is done integrated processing, then increase fairing and make DC driven
LED component meets civilian alternating current, and of high cost, process is complicated.
Invention content
It is a primary object of the present invention to provide a kind of LED chip and its manufacturing method, using light emitting diode (LED) chip with vertical structure
Design concept is completed the exchange to die unit in chip section and is designed so that chip can be applied under alternating current, improve simultaneously
Chip cooling ability.
In order to solve the above technical problems, the present invention provides a kind of manufacturing methods of LED chip, including：
Epitaxial structure is provided, the epitaxial structure includes the first substrate and epitaxial layer, and the epitaxial layer includes from bottom to top
N-type epitaxy layer, quantum well layer and the p-type epitaxial layer being sequentially formed on first substrate；
The epitaxial layer is etched, until exposing first substrate, isolated groove is formed, to isolate multiple crystal grain lists
Member；
The part p-type epitaxial layer and quantum well layer of the close isolated groove of etching, until exposing N-type extension
Layer；
Functional layer is formed on the remaining p-type epitaxial layer；
The first insulating layer is formed, first insulating layer covers the functional layer, the N-type epitaxy layer and the isolation
The side wall of groove and bottom, and first insulating layer is etched, expose part N-type epitaxy layer and partial function layer；
It forms metal connecting layer, is exposed in the adjacent die unit on metal connecting layer connection first direction
N-type epitaxy layer and functional layer, to form multiple crystal grain series connection groups, and the not isomorphous in metal connecting layer connection second direction
The N-type epitaxy layer and functional layer that any two die unit exposes in grain series connection group, to form crystal grain parallel connection group.
Preferably, after forming the crystal grain parallel connection group, the manufacturing method of the LED chip further includes：
Sequentially form second insulating layer and bonding metal layer；
Second substrate is provided, second substrate is bonded with the bonding metal layer and removes first lining
Bottom；
Protective layer and N-type liner are formed in the N-type epitaxy layer.
Preferably, the N-type liner is formed on the crystal grain of the crystal grain series connection group either end.
Preferably, the functional layer includes the metal contact layer being sequentially located at from bottom to top on institute's p-type epitaxial layer, reflecting layer
And metallic spacer.
Preferably, after forming the second insulating layer, before forming the metal bonding layer, the LED chip
Manufacturing method further include：It is sequentially etched the first insulation for padding the opposite other end in the crystal grain series connection group with the N-type
Layer and second insulating layer, until exposing part metals separation layer.
Preferably, after forming the functional layer, before forming first insulating layer, the system of the LED chip
The method of making further includes：The functional layer is performed etching, the edge of the p-type epitaxial layer is exposed.
Preferably, after removing first substrate, the manufacturing method of the LED chip further includes：To the N-type extension
Layer carries out surface roughening treatment.
Preferably, the epitaxial layer further includes undoped epitaxial layer, and the undoped epitaxial layer is located at first substrate
Between the N-type epitaxy layer.
Preferably, after removing first substrate, before carrying out surface roughening treatment to the N-type epitaxy layer, institute
The manufacturing method for stating LED chip further includes：Remove the undoped epitaxial layer.
Preferably, the material of the undoped epitaxial layer, N-type epitaxy layer and p-type epitaxial layer is gallium nitride.
Further, the present invention provides a kind of LED chip structure, is made using the manufacturing method of above-mentioned LED chip.
In conclusion in a kind of LED chip provided by the invention and its manufacturing method, it includes N-type extension to provide one first
The epitaxial structure of layer, quantum well layer and p-type epitaxial layer etches the epitaxial structure and forms the crystal grain being isolated by multiple isolated grooves
Unit etches the part p-type epitaxial layer and quantum well layer close to the isolated groove, until exposing N-type epitaxy layer, so
Functional layer, the first insulating layer, metal connecting layer are formed afterwards, in different directions by metal connecting layer, by N-type epitaxy layer and work(
Ergosphere connects, and realizes the exchange design of chip unit, forms the LED chip with vertical structure.The present invention is by forming metal
Interconnection layer realizes that exchange is integrated in chip stage, is conducive to the operation of back segment packaging technology, while improving the heat radiation energy of chip
Power and luminous efficiency.
Description of the drawings
Fig. 1 is the flow chart of the manufacturing method of LED chip in the embodiment of the present invention；
Fig. 2 is the diagrammatic cross-section of step S01 epitaxial structures in the manufacturing method of LED chip in the embodiment of the present invention
(along the directions X1)；
Fig. 3 a are that etching epitaxial layer forms crystal grain list in step S02 in the manufacturing method of LED chip in the embodiment of the present invention
Vertical view after member；
Fig. 3 b are that etching epitaxial layer forms crystal grain list in step S02 in the manufacturing method of LED chip in the embodiment of the present invention
Cross-sectional schematic after member (along the directions X1)；
Fig. 4 a are etched portions p-type epitaxial layer and amount in step S03 in the manufacturing method of LED chip in the embodiment of the present invention
Vertical view after sub- well layer；
Fig. 4 b are etched portions p-type epitaxial layer and amount in step S03 in the manufacturing method of LED chip in the embodiment of the present invention
Cross-sectional schematic after sub- well layer (along the directions X1)；
Fig. 5 a are to form the vertical view after functional layer in the embodiment of the present invention in the manufacturing method of LED chip in step S04；
Fig. 5 b are that the section after forming functional layer in the embodiment of the present invention in the manufacturing method of LED chip in step S04 shows
Scheme in (along the directions X1)；
Fig. 6 a are bowing after forming the first insulating layer in the embodiment of the present invention in the manufacturing method of LED chip in step S05
View；
Fig. 6 b are cuing open after forming the first insulating layer in the embodiment of the present invention in the manufacturing method of LED chip in step S05
Face diagram (along the directions X1)；
Fig. 7 a are bowing after forming metal connecting layer in the embodiment of the present invention in the manufacturing method of LED chip in step S06
View；
Fig. 7 b are cuing open after forming metal connecting layer in the embodiment of the present invention in the manufacturing method of LED chip in step S06
Face diagram (along the directions X1)；
Fig. 7 c are cuing open after forming metal connecting layer in the embodiment of the present invention in the manufacturing method of LED chip in step S06
Face diagram (along the directions X2)；
Fig. 7 d are cuing open after forming metal connecting layer in the embodiment of the present invention in the manufacturing method of LED chip in step S06
Face diagram (along the directions Y1)；
Fig. 7 e are cuing open after forming metal connecting layer in the embodiment of the present invention in the manufacturing method of LED chip in step S06
Face diagram (along the directions Y2)；
Fig. 8 is to form the section after second insulating layer in the embodiment of the present invention in the manufacturing method of LED chip in step S06
Diagram (along the directions X1)；
Fig. 9 is to form the section after bonding metal layer in the embodiment of the present invention in the manufacturing method of LED chip in step S06
Diagram (along the directions X1)；
Figure 10 is to be bonded the section after the second substrate in step S06 in the manufacturing method of LED chip in the embodiment of the present invention
Diagram (along the directions X1)；
Figure 11 is to remove the section after the first substrate in step S06 in the manufacturing method of LED chip in the embodiment of the present invention
Diagram (along the directions X1)；
Figure 12 is after removing undoped epitaxial layer in step S06 in the manufacturing method of LED chip in the embodiment of the present invention
Cross-sectional schematic (along the directions X1)；
Figure 13 is after forming protective layer and N-type liner in the embodiment of the present invention in the manufacturing method of LED chip in step S06
Cross-sectional schematic (along the directions X1).
Specific implementation mode
The LED chip and its manufacturing method of the present invention are described in more detail below in conjunction with schematic diagram, wherein table
Showing the preferred embodiment of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and still
Realize the advantageous effects of the present invention.Therefore, following description should be understood as the widely known of those skilled in the art, and
It is not intended as limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail well known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to related system or related business
Limitation, another embodiment is changed by one embodiment.Additionally, it should think that this development may be complicated and expend
Time, but it is only to those skilled in the art routine work.
The present invention is more specifically described by way of example with reference to attached drawing in the following passage.It is wanted according to following explanation and right
Ask book, advantages and features of the invention that will become apparent from.It should be noted that attached drawing is all made of very simplified form and uses non-
Accurately ratio, only for the purpose of facilitating and clarifying the purpose of the embodiments of the invention.
Core of the invention thought is, provides a kind of manufacturing method of the LED chip based on vertical structure, including：
Step S01：Epitaxial structure is provided, the epitaxial structure includes the first substrate and epitaxial layer, and the epitaxial layer includes
N-type epitaxy layer, quantum well layer and the p-type epitaxial layer being sequentially formed in from bottom to top on first substrate；
Step S02：The epitaxial layer is etched, until exposing first substrate, forms isolated groove, it is more to isolate
A die unit；
Step S03：The part p-type epitaxial layer and quantum well layer of the close isolated groove of etching, until exposing N
Type epitaxial layer；
Step S04：Functional layer is formed on the remaining p-type epitaxial layer；
Step S05：Form the first insulating layer, first insulating layer cover the functional layer, the N-type epitaxy layer and
The side wall of the isolated groove and bottom, and first insulating layer is etched, expose part N-type epitaxy layer and partial function
Layer；
Step S06：Metal connecting layer is formed, the metal connecting layer connects on first direction in the adjacent die unit
The N-type epitaxy layer and functional layer exposed, to form multiple crystal grain series connection groups, and the metal connecting layer connects second direction
The N-type epitaxy layer and functional layer that any two die unit exposes in upper difference crystal grain series connection group, to form crystal grain parallel connection group.
It is exemplified below the preferred embodiment of the LED chip and its manufacturing method, clearly to illustrate present disclosure, is answered
When it is clear that, present disclosure is not restricted to following embodiment, other pass through the routine of those of ordinary skill in the art
The improvement of technological means is also within the thought range of the present invention.
Fig. 1 is the flow chart of the manufacturing method of LED chip in the embodiment of the present invention；Fig. 2 to Figure 13 is the embodiment of the present invention
In the manufacturing method based on LED chip correlation step corresponding to vertical view or sectional view.Below in conjunction with the accompanying drawings, it is described in detail
A kind of manufacturing method of LED chip proposed by the present invention.
In step S01, epitaxial structure is provided, the epitaxial structure includes the first substrate 100 and epitaxial layer 101, described
Epitaxial layer 101 includes N-type epitaxy layer 120, quantum well layer 130 and the P being sequentially formed in from bottom to top on first substrate 100
Type epitaxial layer 140.The epitaxial layer 101 further includes a undoped epitaxial layer 110, is located at first substrate 100 and the N-type
Between epitaxial layer 120, the undoped epitaxial layer 110 is as between first substrate 100 and the N-type epitaxy layer 120
Buffer layer.First substrate 100 can be Sapphire Substrate, the undoped epitaxial layer 110, N-type epitaxy layer 120 and p-type
The material of epitaxial layer 140 is both preferably gallium nitride, i.e., the epitaxial layer 101 includes：Undoped gallium nitride layer (U-GaN), N-type
Gallium nitride layer (N-GaN), quantum well layer (MQW) and p-type gallium nitride layer (P-GaN), as shown in Figure 2.The system of the epitaxial structure
It is standby to belong to common knowledge, herein without being described in detail.
In step S02, the epitaxial layer 101 is etched, until exposing the first substrate 100, forms isolated groove 101a,
Multiple die units are isolated, the die unit can exist in a variety of forms, preferably, the present embodiment die unit is in
Array arranges, as shown in Figure 3a and Figure 3b shows.Wet etching or inductively coupled plasma may be used in the epitaxial layer etching
(ICP) it etches.
In step S03, the part p-type epitaxial layer 140 and quantum well layer close to the isolated groove 101a are etched
130, until exposing N-type epitaxy layer 120, forms Mesa platforms 120a, the Mesa platforms 120a and surround the remaining p-type
Epitaxial layer 140 and quantum well layer 130.As shown in figures 4 a and 4b.Wet etching or inductively coupled plasma may be used
(ICP) it etches, forms Mesa platforms 120a.
In step S04, functional layer 102 is formed on the remaining p-type epitaxial layer 140, as shown in figure 5 a and 5b.
Preferably, the functional layer 102 include be sequentially located at from bottom to top metal contact layer on institute's p-type epitaxial layer 140, reflecting layer and
Metallic spacer (not shown).First, metal contact layer is formed on the p-type epitaxial layer 140, the metal contact layer
Material can be the oxidation of the low resistances, high transparency such as tin indium oxide (ITO), zinc oxide (ZnO) or Al-Doped ZnO (AZO)
Object can be formed by sputtering (Sputter) mode or plasma assisted deposition (RPD) mode.Later, continue in the gold
Belonging to and forms reflecting layer on contact layer, the material in the reflecting layer includes the high-reflectivity metals such as silver (Ag), aluminium (Al) or rhodium (Rh),
The distributed Bouguer that is selected as that vapor deposition formation or reflecting layer may be used draws speculum (DBR).The size root in the reflecting layer
Depending on done chip size.Finally, metallic spacer is formed on reflecting layer, the material of the metallic spacer can be
Titanium-platinum (Ti-Pt) alloy or titanium-tungsten-platinum (TiW-Pt) alloy.
In the present embodiment, the LED core piece making method further includes：The functional layer 102 is performed etching, is exposed
The edge 140a of the p-type epitaxial layer 140.
In step S05, the first insulating layer 103 is formed, first insulating layer 103 covers the functional layer 102, described
The edge 140a of p-type epitaxial layer 140, the side wall of the N-type epitaxy layer (Mesa platform 120a) and the isolated groove 101a
And bottom, and first insulating layer 103 is etched, expose part N-type epitaxy layer 120b (on Mesa platforms) and partial function
Layer 102a (uses the first insulating layer 103 of shadow representation) as shown in figures 6 a and 6b in Fig. 6 a.First insulating layer 103
Material can be silica (SiO2), aluminium oxide (Al2O3), silicon nitride (Si3N4) or distributed Bouguer drawing speculum (DBR),
It can be the stack layer of one or more kinds of materials of the above material.It can be deposited by CVD techniques, then pass through photoetching
First insulating layer 103 with required figure is obtained after etching technics.
After first insulating layer 103 described in chemical wet etching, part N-type epitaxy layer 120b and partial function layer (metal are exposed
Separation layer) 102a, it is contemplated that die unit series/parallel in the subsequent process, where can designing the two according to actual needs
Position.
In step S06, it is initially formed metal connecting layer 104, the metal connecting layer 104 connects the part N exposed
Type epitaxial layer 120b and partial function layer 102a.The part N-type that the metal connecting layer will can expose in different directions
Epitaxial layer 120b is connected with partial function layer 102a, preferably, metal connecting layer 104 is from first direction (X in the present embodiment
Axis) and second direction (Y-axis) the part N-type epitaxy layer 120b that exposes of connection and partial function layer 102a, the first direction
Can be in any angle with second direction, for convenience of illustrating, the present embodiment using first direction and the rectangular design of second party,
I.e. angle is in 90 degree of X-axis and Y-axis.
Fig. 7 a are the vertical view after the die unit forms metal connecting layer in the present embodiment, Fig. 7 b and Fig. 7 c difference
For the section in the present embodiment after the die unit forms metal connecting layer along the first direction directions (X-axis) X1 and the directions X2
Structural schematic diagram, as shown in Fig. 7 a, 7b, 7c, the metal connecting layer 104 cover the part N-type epitaxy layer 120b that exposes and
Partial function layer 102a and the first insulating layer 103 between the two will be isolated the die unit series connection of groove 101a isolation
Get up, forms crystal grain series connection group.Fig. 7 d and Fig. 7 e be respectively in the present embodiment the die unit formed metal connecting layer after
The cross-sectional view in the directions (Y-axis) Y1 and the directions Y2 in a second direction passes through metal connecting layer as shown in Fig. 7 a, 7d, 7e
The part N-type epitaxy layer 120b and partial function layer 102a that neighboring die in the crystal grain series connection group exposes are connected, it will be described
Crystal grain series connection group is together in parallel.The crystal grain cross-linked structure (serial/parallel structure) can be designed according to actual needs, no
It is confined to structure shown in the present embodiment.The material of the metal connecting layer 104 can be the conductive metals such as copper (Cu), aluminium (Al),
Thickness is generally 1um-1.5um.
In step S06, after forming metal connecting layer 104, second insulating layer 105 and bonding metal layer are sequentially formed
106.It is initially formed second insulating layer 105, the second insulating layer 105 covers the first insulating layer 103 and metal connecting layer 104,
Then second insulating layer 105 and the first insulating layer 103 are sequentially etched by lithographic etch process, expose partial function layer
102b exposes the top-level metallic separation layer of functional layer 102, as shown in Figure 8.The partial function layer 102b exposed with
The N-type liner being subsequently formed is located on the crystal grain at crystal grain series connection group head and the tail both ends, can also be set according to actual needs
Count the position where the two.Then bonding metal layer 106 is formed on two insulating layer 105, the bonding metal layer 106 covers
Lid second insulating layer 105 and the partial function layer 102b exposed, as shown in Figure 9.The bonding metal layer 106 can be single layer
Or multilayered structure, material can be nickel (Ni), golden (Au), tin (Sn), titanium (Ti), platinum (Pt), chromium (Cr) it is one or more, it is excellent
Choosing is using golden (Au), tin (Sn) or golden tin (AuSn) alloy.
In step S06, after sequentially forming second insulating layer 105 and bonding metal layer 160, the second substrate 200 is provided, it will
Second substrate 200 is bonded with the bonding metal layer 106 and removes first substrate 100, as shown in Figure 10.Institute
The material for stating the second substrate 200 can be silicon (Si), copper (Cu), tungsten (W) or molybdenum (Mo) etc., to have preferable heat conduction and
Electric conductivity.Second substrate 200 is bonded together by metal bonding layer 106 and the epitaxial structure, may then pass through
Laser lift-off or wet-etching technology remove the first substrate 100, as shown in figure 11.
In step S06, after etching removes first substrate 100, protective layer is formed in the N-type epitaxy layer 120
107 and N-type liner 108.First, after removing first substrate 100, etching removes the undoped epitaxial layer 110,
Until exposing N-type epitaxy layer 120, as shown in figure 12, wherein etching removes the undoped epitaxial layer 110 and further includes：It carves
Lose the first insulating layer 103 in the isolated groove 101a of part, the specific thickness for etching degree and regarding the undoped epitaxial layer 110
Depending on degree.Then, surface roughening treatment (not shown), the roughing in surface are carried out to the N-type epitaxy layer 120 exposed
Potassium hydroxide (KOH) solution, sulfuric acid (H for example may be used in processing2SO4) solution etc. carries out wet etching, rough surface is obtained,
To improve light emission rate.Finally, protective layer 107 and N-type liner 108 are formed in the N-type epitaxy layer 120, as shown in figure 13.Shape
After N-type liner 108, the N-type of the different crystal grain series connection groups can be padded 108 and connected.The protection
The material of layer 107 for example can be silica (SiO2).N-type liner 108, the N-type liner can be formed by evaporation coating method
108 may be used nickel (Ni)/gold (Au), aluminium (Al)/titanium (Ti)/platinum (Pt)/gold (Au), chromium (Cr)/platinum (Pt)/gold (Au) etc. again
Close structure.
Further, the present invention provides a kind of LED chip structure, is made using the manufacturing method of above-mentioned LED chip.
In conclusion in a kind of LED chip provided by the invention and its manufacturing method, it includes N-type extension to provide one first
The epitaxial structure of layer, quantum well layer and p-type epitaxial layer etches the epitaxial structure and forms the crystal grain being isolated by multiple isolated grooves
Unit etches the part p-type epitaxial layer and quantum well layer close to the isolated groove, until exposing N-type epitaxy layer, so
Functional layer, the first insulating layer, metal connecting layer are formed afterwards, in different directions by metal connecting layer, by N-type epitaxy layer and work(
Ergosphere connects, and realizes the exchange design of chip unit, forms the LED chip with vertical structure.The present invention is by forming metal
Interconnection layer realizes that exchange is integrated in chip stage, is conducive to the operation of back segment packaging technology, while improving the heat radiation energy of chip
Power and luminous efficiency.
Claims (11)
1. a kind of LED core piece making method, which is characterized in that including：
Epitaxial structure is provided, the epitaxial structure includes the first substrate and epitaxial layer, and the epitaxial layer includes from bottom to top successively
N-type epitaxy layer, quantum well layer and the p-type epitaxial layer being formed on first substrate；
The epitaxial layer is etched, until exposing first substrate, isolated groove is formed, to isolate multiple die units；
The part p-type epitaxial layer and quantum well layer of the close isolated groove of etching, until exposing N-type epitaxy layer；
Functional layer is formed on the remaining p-type epitaxial layer；
The first insulating layer is formed, first insulating layer covers the functional layer, the N-type epitaxy layer and the isolated groove
Side wall and bottom, and etch first insulating layer, expose part N-type epitaxy layer and partial function layer；
Metal connecting layer is formed, the metal connecting layer connects the N-type exposed in the adjacent die unit on first direction
Epitaxial layer and functional layer, to form multiple crystal grain series connection groups, and different crystal grain in metal connecting layer connection second direction
The N-type epitaxy layer and functional layer that any two die unit exposes in series connection group, to form crystal grain parallel connection group.
2. the manufacturing method of LED chip according to claim 1, which is characterized in that after forming the crystal grain parallel connection group,
The manufacturing method of the LED chip further includes：
Sequentially form second insulating layer and bonding metal layer；
Second substrate is provided, second substrate is bonded with the bonding metal layer and removes first substrate；
Protective layer and N-type liner are formed in the N-type epitaxy layer.
3. the manufacturing method of LED chip according to claim 2, which is characterized in that in the crystal grain series connection group either end
Crystal grain on form N-type liner.
4. the manufacturing method of LED chip according to claim 3, which is characterized in that the functional layer includes from bottom to top
Metal contact layer, reflecting layer and the metallic spacer being sequentially located on institute's p-type epitaxial layer.
5. the manufacturing method of LED chip according to claim 4, which is characterized in that formed the second insulating layer it
Afterwards, before forming the metal bonding layer, the manufacturing method of the LED chip further includes：It is sequentially etched the crystal grain series connection
The first insulating layer and second insulating layer of the opposite other end are padded in group with the N-type, until exposing part metals isolation
Layer.
6. the manufacturing method of LED chip according to claim 5, which is characterized in that after forming the functional layer,
It is formed before first insulating layer, the manufacturing method of the LED chip further includes：The functional layer is performed etching, exposure
Go out the edge of the p-type epitaxial layer.
7. the manufacturing method of LED chip according to claim 6, which is characterized in that after removal first substrate, institute
The manufacturing method for stating LED chip further includes：Surface roughening treatment is carried out to the N-type epitaxy layer.
8. the manufacturing method of LED chip according to claim 7, which is characterized in that the epitaxial layer further includes undoped
Epitaxial layer, the undoped epitaxial layer is between first substrate and the N-type epitaxy layer.
9. the manufacturing method of LED chip according to claim 8, which is characterized in that after removing first substrate,
Before carrying out surface roughening treatment to the N-type epitaxy layer, the manufacturing method of the LED chip further includes：Remove described non-mix
Miscellaneous epitaxial layer.
10. the manufacturing method of LED chip according to claim 9, which is characterized in that outside the undoped epitaxial layer, N-type
The material for prolonging layer and p-type epitaxial layer is gallium nitride.
11. a kind of LED chip structure, which is characterized in that using by a kind of LED core described in any one of claim 1-10
The manufacturing method of piece is made.
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| CN201810276826.9A CN108305886A (en) | 2018-03-30 | 2018-03-30 | A kind of LED chip and its manufacturing method |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102881707A (en) * | 2012-09-14 | 2013-01-16 | 金木子 | High-voltage direct current or alternating current chip with front fixing structure |
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