TWI704687B - Light-emitting diode - Google Patents

Light-emitting diode Download PDF

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TWI704687B
TWI704687B TW107118536A TW107118536A TWI704687B TW I704687 B TWI704687 B TW I704687B TW 107118536 A TW107118536 A TW 107118536A TW 107118536 A TW107118536 A TW 107118536A TW I704687 B TWI704687 B TW I704687B
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layer
region
light
item
area
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TW107118536A
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TW201832356A (en
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楊宗憲
巫漢敏
王誌賢
陳怡名
徐子傑
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晶元光電股份有限公司
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Abstract

The application provides a light-emitting diode comprising a first light-emitting structure, comprising: a first area comprising a sidewall; a second area; and a first isolation path having an electrode isolation layer between the first area and the second area. The light-emitting diode further comprises an electrode contact layer covering the first area; an electrical connecting structure covering the second area; and an electrical contact layer under the electrical connecting structure, wherein the electrical contact layer directly contacts the electrical connecting structure; wherein each of the first area and the second area sequentially comprises a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, and the electrode contact layer covers the sidewall of the first area.

Description

發光二極體Light-emitting diode

本發明關於一種發光二極體結構及其製造方法,特別是關於一種利用電極絕緣層來改善漏電現象的結構及其製造方法。 The present invention relates to a light-emitting diode structure and a manufacturing method thereof, in particular to a structure using an electrode insulating layer to improve leakage phenomenon and a manufacturing method thereof.

發光二極體是半導體元件中一種被廣泛使用的光源。相較於傳統的白熾燈泡或螢光燈管,發光二極體具有省電及使用壽命較長的特性,因此逐漸取代傳統光源而應用於各種領域,如交通號誌、背光模組、路燈照明、醫療設備等產業。 Light-emitting diodes are a widely used light source in semiconductor components. Compared with traditional incandescent bulbs or fluorescent tubes, light-emitting diodes have the characteristics of power saving and longer service life, so they are gradually replacing traditional light sources and used in various fields, such as traffic signs, backlight modules, and street lighting. , Medical equipment and other industries.

隨著發光二極體光源的應用與發展對於亮度的需求越來越高,如何增加其發光效率以提高其亮度,便成為產業界所共同努力的重要方向。 With the application and development of light-emitting diode light sources, there is an increasing demand for brightness. How to increase its luminous efficiency to improve its brightness has become an important direction for the joint efforts of the industry.

第14圖描述了現有技術中用於半導體發光元件的LED封裝體300:包括由封裝結構1封裝的半導體LED晶片2,其中半導體LED晶片2具有一p-n接面3,封裝結構1通常是熱固性材料,例如環氧樹脂(epoxy)或者熱塑膠材料。半導體LED晶片2透過一焊線(wire)4與兩導電支架5、6連接。因為環氧樹脂(epoxy)在高溫中會有劣化(degrading)現象,因此只能在低溫環境運作。此外,環氧樹脂(epoxy)具很高的熱阻(thermal resistance),使得第14圖的結構只提供了半導體LED晶片2高阻值的熱散逸途徑,而限制了LED封裝體1的低功耗應用。 Figure 14 depicts an LED package 300 for semiconductor light-emitting elements in the prior art: including a semiconductor LED chip 2 packaged by a package structure 1, wherein the semiconductor LED chip 2 has a pn junction 3, and the package structure 1 is usually made of thermosetting material , Such as epoxy or thermoplastic materials. The semiconductor LED chip 2 is connected to the two conductive supports 5 and 6 through a wire 4. Because epoxy resins are degraded at high temperatures, they can only operate in low temperature environments. In addition, epoxy has a high thermal resistance, so that the structure of Figure 14 only provides a high-resistance heat dissipation path for the semiconductor LED chip 2, which limits the low power of the LED package 1. Consuming applications.

本發明提供一發光二極體,包含:一第一發光二極體,包含:一第一區域,其包含一側壁;一第二區域;及一第一隔絕道,其包含一介於第一區域以及第二區域之間的電極絕緣層。發光二極體更包含一電極連接層覆蓋第一區域;一電性連接結構覆蓋第二區域;及一位於電性連接結構下的電性連接層,且電性連接層直接接觸電性連接結構,其中第一區域及第二區域各依序包含:一第一導電型半導體層、一活性層及一第二導電型半導體層,且電極連接層覆蓋第一區域的側壁。 The present invention provides a light emitting diode, including: a first light emitting diode, including: a first region including a sidewall; a second region; and a first isolation channel including an intervening first region And the electrode insulating layer between the second area. The light emitting diode further includes an electrode connection layer covering the first area; an electrical connection structure covering the second area; and an electrical connection layer located under the electrical connection structure, and the electrical connection layer directly contacts the electrical connection structure , Wherein the first region and the second region each sequentially include: a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor layer, and the electrode connection layer covers the sidewall of the first region.

1:封裝結構 1: Package structure

2:發光二極體晶片 2: LED chip

3:p-n接面 3: p-n junction

4:焊線 4: wire bonding

5,6:導電支架 5, 6: Conductive bracket

10:成長基板 10: Growth substrate

11:第一導電型接觸層 11: The first conductivity type contact layer

12:第一導電型半導體層 12: First conductivity type semiconductor layer

12a:下平面 12a: lower plane

13:活性層 13: active layer

14:第二導電型半導體層 14: Second conductivity type semiconductor layer

14a:上平面 14a: upper plane

15b:第二電性電極 15b: second electrical electrode

15c:第二電性延伸電極 15c: second electrical extension electrode

16:暫時基板 16: Temporary substrate

17:電性連接層 17: Electrical connection layer

18:永久基板 18: Permanent substrate

19:接合層 19: Bonding layer

20:第一隔絕道 20: The first isolation

21:第二隔絕道 21: The second isolation

22:電極絕緣層 22: Electrode insulation layer

23:絕緣結構 23: Insulation structure

24:電性連接結構 24: Electrical connection structure

25:第二電性焊接墊 25: The second electrical soldering pad

26:電極連接層 26: Electrode connection layer

30:基板 30: substrate

30a:第一表面 30a: first surface

40:導電配線結構 40: Conductive wiring structure

50,60:電性焊接墊 50, 60: Electrical soldering pad

50A:第一區域 50A: First area

50B:第二區域 50B: second area

70:隔絕道 70: Isolate Road

80:電極絕緣層 80: Electrode insulation layer

100:第一發光二極體 100: the first light-emitting diode

200:第二發光二極體 200: second light-emitting diode

300:發光二極體封裝體 300: LED package

1000,2000:發光二極體陣列 1000, 2000: LED array

第1-12圖係本發明第一實施例之發光二極體陣列之結構剖面示意圖。 Figures 1-12 are schematic cross-sectional views of the structure of the light-emitting diode array of the first embodiment of the present invention.

第13圖係本發明第二實施例之發光二極體陣列上視圖。 Fig. 13 is a top view of a light emitting diode array according to the second embodiment of the present invention.

第14圖係習知之發光元件結構圖。 Figure 14 is a structural diagram of a conventional light-emitting device.

本發明之實施例會被詳細地描述,並且繪製於圖式中,相同或類似的部分會以相同的號碼在各圖式以及說明出現。 The embodiments of the present invention will be described in detail and drawn in the drawings, and the same or similar parts will appear with the same numbers in the drawings and descriptions.

為了使本發明之敘述更加詳盡與完備,請參照下列描述並配合第1圖至第13圖之圖式。依據本發明第一實施例之發光二極體陣列1000之結構及製造步驟如下:如第1圖所示,提供一成長基板10,例如砷化鎵基板;複數個發光二極體直接磊晶成長於此基板上。本實施例中發光二極體單元為100、200二個,但並不以此數目為限。其中,每一個發光二極體包含一第一導電型接觸層11、第一導電型半導體層12、一活性層13、以及一第二導電型半導體層14,如第2圖所 示。其中,第一導電型接觸層11可為n型砷化鎵(n-GaAs);第一導電型半導體層12、一活性層13、以及一第二導電型半導體層14其材料包含一種或一種以上之元素選自鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)以及矽(Si)所構成群組;例如可為磷化鎵(GaP)或磷化鋁鎵銦(AlGaInP)。 In order to make the description of the present invention more detailed and complete, please refer to the following description in conjunction with the drawings in Figures 1 to 13. The structure and manufacturing steps of the light-emitting diode array 1000 according to the first embodiment of the present invention are as follows: as shown in Figure 1, a growth substrate 10, such as a gallium arsenide substrate, is provided; a plurality of light-emitting diodes are directly epitaxially grown On this substrate. In this embodiment, there are two light-emitting diode units 100 and 200, but the number is not limited. Wherein, each light emitting diode includes a first conductivity type contact layer 11, a first conductivity type semiconductor layer 12, an active layer 13, and a second conductivity type semiconductor layer 14, as shown in FIG. Show. The first conductive type contact layer 11 may be n-type gallium arsenide (n-GaAs); the first conductive type semiconductor layer 12, an active layer 13, and a second conductive type semiconductor layer 14 are made of one or one material The above elements are selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N) and silicon (Si); for example, it may be gallium phosphide (GaP) or aluminum gallium indium phosphide (AlGaInP).

於第二導電型半導體層14之上利用蒸鍍方式分別於選擇性區域形成電極結構,例如:至少一第二電性電極15b及複數個第二電性延伸電極15c。再於此些電極之上接合一暫時基板16後,移除成長基板10,如第3、4圖所示;其中暫時基板16可為玻璃。利用微影蝕刻製程將第一導電型接觸層11部份移除以形成複數個點狀結構並露出部分第一導電型半導體層12之下表面12a,再分別於部分下表面12a及複數個第一導電型接觸層11點狀結構之下形成一電性連接層17,如第5圖所示。上述第二電性電極15b及複數個第二電性延伸電極15c之材料可選自:鉻(Cr)、鈦(Ti)、鎳(Ni)、鉑(Pt)、銅(Cu)、金(Au)、鋁(Al)、鎢(W)、錫(Sn)、或銀(Ag)等金屬材料。電性連接層17之材料可為鍺/金。 Electrode structures, such as at least one second electrical type electrode 15b and a plurality of second electrical type extension electrodes 15c, are respectively formed on the second conductive semiconductor layer 14 in selective regions by vapor deposition. After joining a temporary substrate 16 on these electrodes, the growth substrate 10 is removed, as shown in FIGS. 3 and 4; the temporary substrate 16 may be glass. The first conductive type contact layer 11 is partially removed by a photolithography process to form a plurality of dot-like structures and a part of the lower surface 12a of the first conductive type semiconductor layer 12 is exposed, and then a part of the lower surface 12a and the plurality of second An electrical connection layer 17 is formed under the dot structure of a conductive contact layer 11, as shown in FIG. The material of the second electrical type electrode 15b and the plurality of second electrical type extension electrodes 15c can be selected from: chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold ( Metal materials such as Au), aluminum (Al), tungsten (W), tin (Sn), or silver (Ag). The material of the electrical connection layer 17 can be germanium/gold.

利用濕式蝕刻法將第一導電型半導體層12之下表面12a蝕刻成一粗糙平面,如第6圖所示。另外提供一永久基板18,例如氧化鋁基板;並於此基板之上形成一接合層19,以形成如第7圖之結構;或於第一導電型半導體層12之下表面12a形成一接合層19(圖未示),再以接合層19將永久基板18接合於第一導電型半導體層12之下表面12a之下,使第6、7圖結構二者接合為一體,並使複數個第一導電型接觸層點狀結構11及電性連接層17介於第一導電型半導體層12之下表面12a與接合層19之間,如第8圖所示。將暫時基板16移除,以裸露出第二電性電極15b、複數個第二電性延伸電極15c及部分第二導電型半導體層14之上表面14a,如第9圖所示。以感應耦合電漿離子蝕刻系統(Inductively Coupled Plasma Reactive Ion Etching System)由上向下乾式蝕刻第二導電型半導體層14、活性層13至裸露出第一導電型半導體層12之部分表面以形成一第一隔絕道20及一第二隔絕道21;其中第一隔絕道20將第一發光二極體100分隔為一第一區域50A及一第二區域50B,且此二區域之距離不小於25μm。第二隔絕道21則位於第一發光二極體100與第三區域之間,第三區域後續形成一第二發光二極體200。再利用乾式蝕刻或濕式蝕刻方法將第二導電型半導體層14之上表面14a蝕刻成一粗糙平面,如第10圖所示。再次以感應耦合電漿離子蝕刻系統將第二隔絕道21中的部份第一導電型半導體層12蝕刻並移除。因前後二次乾式蝕刻速率不同,造成第二隔絕道21中的第二導電型半導體層14、活性層13及第一導電型半導體層12之側壁形成一階梯狀,如第11圖所示。 The lower surface 12a of the first conductive semiconductor layer 12 is etched into a rough surface by a wet etching method, as shown in FIG. 6. In addition, a permanent substrate 18, such as an alumina substrate, is provided; and a bonding layer 19 is formed on the substrate to form the structure shown in Fig. 7; or a bonding layer is formed on the lower surface 12a of the first conductive semiconductor layer 12 19 (not shown), the permanent substrate 18 is bonded under the lower surface 12a of the first conductive type semiconductor layer 12 with the bonding layer 19, so that the structures of FIGS. 6 and 7 are bonded together, and a plurality of A conductive contact layer point structure 11 and an electrical connection layer 17 are interposed between the lower surface 12a of the first conductive semiconductor layer 12 and the bonding layer 19, as shown in FIG. The temporary substrate 16 is removed to expose the second electrical type electrode 15b, the plurality of second electrical type extension electrodes 15c, and part of the upper surface 14a of the second conductivity type semiconductor layer 14, as shown in FIG. Inductively Coupled Plasma Ion Etching System (Inductively Coupled Plasma Reactive Ion Etching System) Dry etching the second conductive semiconductor layer 14 and the active layer 13 from top to bottom to expose part of the surface of the first conductive semiconductor layer 12 to form a first isolation channel 20 and a second isolation channel 21 ; Wherein the first isolation channel 20 separates the first light emitting diode 100 into a first area 50A and a second area 50B, and the distance between these two areas is not less than 25 μm. The second isolation channel 21 is located between the first light-emitting diode 100 and the third area, and a second light-emitting diode 200 is subsequently formed in the third area. Then, dry etching or wet etching is used to etch the upper surface 14a of the second conductive semiconductor layer 14 into a rough surface, as shown in FIG. 10. The inductively coupled plasma ion etching system is used to etch and remove part of the first conductivity type semiconductor layer 12 in the second isolation channel 21 again. Due to the different dry etching rates before and after the secondary dry etching, the sidewalls of the second conductive semiconductor layer 14, the active layer 13, and the first conductive semiconductor layer 12 in the second isolation channel 21 form a step shape, as shown in FIG.

於第一隔絕道20中,沿著第二區域50B的側壁以蒸鍍方法形成一電極絕緣層22,且此電極絕緣層22的高度大於第二區域50B的側壁高度。於第二隔絕道21中,沿著第二區域50B的部份上表面及側壁以蒸鍍方法形成一絕緣結構23及沿著第二發光二極體200的部份上表面及側壁以蒸鍍方法形成另一絕緣結構23,其中電極絕緣層22和絕緣結構23的材料可為氧化矽,氮化矽,氧化鋁,氧化鋯,或氧化鈦等介電材料。再形成一電極連接層26包覆第一區域50A之側壁及上表面,其中電極連接層26材料可為鈦-金。因電極連接層26與第一發光二極體100之第一導電型半導體層12、活性層13及第二導電型半導體層14之間無法形成電性歐姆接觸,需藉由電性連接層17才能與第一導電型半導體層12形成電性歐姆接觸。在第二隔絕道21中,於第二區域50B的絕緣結構23之上方、側壁及第二隔絕道21底部形成一電性連接結構24;其中第一發光二極體100之第二導電型半導體層14藉由此電性連接結構24及電性連接層17與第二發光二極體200之第一導電型 半導體層12形成串聯之電性連接。再於第二電性電極15b之上形成一第二電性焊接墊25。另外,電極連接層26可作為第一電性焊接墊之用,當電極連接層26和第二電性焊接墊25外接電源形成電性連接(圖未示)時,外接電源提供的電流可從電極連接層26經由電性連接層17流經發光二極體100之第一導電型半導體層12、活性層13、第二導電型半導體層14,並藉由電性連接結構24流至發光二極體200。其中電極連接層26及電性連接結構24可與此第二電性焊接墊25同時以蒸鍍方式形成,且組成材料可以相同。經由上述製程步驟後形成一具有二個發光二極體100,200串聯而成之發光二極體陣列1000。發光二極體100被第一隔絕道20分隔成一第一區域50A及一第二區域50B;其中第一區域50A被一電極連接層26所包覆。第二電性焊接墊25位於第二發光二極體200之部份上表面14a上,且電極連接層26之上表面與第二電性焊接墊25之上表面可位於相同的水平高度。 In the first isolation channel 20, an electrode insulating layer 22 is formed along the sidewall of the second region 50B by an evaporation method, and the height of the electrode insulating layer 22 is greater than the height of the sidewall of the second region 50B. In the second isolation channel 21, an insulating structure 23 is formed by evaporation along a part of the upper surface and sidewalls of the second region 50B, and an insulating structure 23 is formed along part of the upper surface and the sidewalls of the second light emitting diode 200 by evaporation The method forms another insulating structure 23, wherein the material of the electrode insulating layer 22 and the insulating structure 23 can be dielectric materials such as silicon oxide, silicon nitride, aluminum oxide, zirconium oxide, or titanium oxide. An electrode connection layer 26 is formed to cover the sidewall and upper surface of the first region 50A, wherein the electrode connection layer 26 can be made of titanium-gold. Since the electrode connection layer 26 and the first conductivity type semiconductor layer 12, the active layer 13 and the second conductivity type semiconductor layer 14 of the first light emitting diode 100 cannot form electrical ohmic contacts, the electrical connection layer 17 is required. In order to form an electrical ohmic contact with the first conductive semiconductor layer 12. In the second isolation channel 21, an electrical connection structure 24 is formed above the insulating structure 23 of the second region 50B, the sidewalls, and the bottom of the second isolation channel 21; wherein the second conductivity type semiconductor of the first light emitting diode 100 The layer 14 electrically connects the structure 24 and the electrically connected layer 17 with the first conductivity type of the second light-emitting diode 200 by this The semiconductor layer 12 forms an electrical connection in series. A second electrical type bonding pad 25 is formed on the second electrical type electrode 15b. In addition, the electrode connecting layer 26 can be used as the first electrical soldering pad. When the electrode connecting layer 26 and the second electrical soldering pad 25 are connected to an external power source (not shown), the current provided by the external power source can be The electrode connection layer 26 flows through the first conductivity type semiconductor layer 12, the active layer 13, and the second conductivity type semiconductor layer 14 of the light emitting diode 100 through the electrical connection layer 17, and flows to the light emitting diode through the electrical connection structure 24. Polar body 200. The electrode connection layer 26 and the electrical connection structure 24 can be formed simultaneously with the second electrical bonding pad 25 by vapor deposition, and the constituent materials can be the same. After the above process steps, a light-emitting diode array 1000 with two light-emitting diodes 100 and 200 connected in series is formed. The light emitting diode 100 is separated by the first isolation channel 20 into a first area 50A and a second area 50B; wherein the first area 50A is covered by an electrode connection layer 26. The second electrical type bonding pad 25 is located on a part of the upper surface 14a of the second light emitting diode 200, and the upper surface of the electrode connection layer 26 and the upper surface of the second electrical type bonding pad 25 may be at the same level.

第13圖為本發明第二實施例之發光二極體陣列2000上視圖,其為包含第一發光二極體100及第二發光二極體200等共10個發光二極體且彼此電性串聯之發光二極體陣列。如第13圖所示,發光二極體陣列2000包含一基板30,具有一第一表面30a;10個發光二極體位於此第一表面上,包含第一發光二極體100及第二發光二極體200;複數個導電配線結構40配置在第一表面上,電性連接此些發光二極體;二電性焊接墊50,60位於第一表面上,且二電性焊接墊與一外接電源電性連接(圖未示);一隔絕道70位於任一電性焊接墊(例如:焊接墊50)與任一發光二極體(例如:發光二極體100)之間;其中此電性焊接墊與發光二極體之距離不小於25μm。當此電性焊接墊與發光二極體之距離過小時,在發光二極體蝕刻步驟時易有半導體物質殘留於發光二極體側壁上,造成漏電現象。此時於隔絕 道70中於發光二極體的側壁形成一電極絕緣層80,可改善此現象。其中基板30係為一承載基礎,可包含導電基板或不導電基板、透光基板或不透光基板。 Figure 13 is a top view of a light-emitting diode array 2000 according to a second embodiment of the present invention. It shows a total of 10 light-emitting diodes including a first light-emitting diode 100 and a second light-emitting diode 200, which are electrically connected to each other. Light-emitting diode array in series. As shown in FIG. 13, the light-emitting diode array 2000 includes a substrate 30 with a first surface 30a; 10 light-emitting diodes are located on the first surface, including a first light-emitting diode 100 and a second light-emitting diode. The diode 200; a plurality of conductive wiring structures 40 are arranged on the first surface and are electrically connected to the light-emitting diodes; the two electrical solder pads 50, 60 are located on the first surface, and the two electrical solder pads and one An external power supply is electrically connected (not shown); an isolation channel 70 is located between any electrical soldering pad (for example: soldering pad 50) and any light-emitting diode (for example: light-emitting diode 100); The distance between the electrical bonding pad and the light emitting diode is not less than 25μm. When the distance between the electrical bonding pad and the light-emitting diode is too small, the semiconductor material is likely to remain on the sidewall of the light-emitting diode during the etching step of the light-emitting diode, causing current leakage. In isolation An electrode insulating layer 80 is formed on the sidewall of the light emitting diode in the channel 70 to improve this phenomenon. The substrate 30 is a supporting base, and may include a conductive substrate or a non-conductive substrate, a light-transmitting substrate or a light-impermeable substrate.

上述第一導電型半導體層12及第二導電型半導體層14係彼此中至少二個部分之電性、極性或摻雜物相異、或者係分別用以提供電子與電洞之半導體材料單層或多層(「多層」係指二層或二層以上,以下同),其電性選擇可以為p型、n型、及i型中至少任意二者之組合。活性層13係位於第一導電型半導體層12及第二導電型半導體層14之間,為電能與光能可能發生轉換或被誘發轉換之區域。 The first conductive type semiconductor layer 12 and the second conductive type semiconductor layer 14 are at least two parts of which are different in electrical properties, polarities or dopants, or are a single layer of semiconductor material used to provide electrons and holes, respectively Or multi-layer ("multi-layer" refers to two or more layers, the same hereinafter), and its electrical selection can be a combination of at least any two of p-type, n-type, and i-type. The active layer 13 is located between the first conductivity type semiconductor layer 12 and the second conductivity type semiconductor layer 14, and is a region where electrical energy and light energy may be converted or induced to convert.

依據本發明之實施例中所述之發光二極體其發光頻譜可以藉由改變半導體單層或多層之物理或化學要素進行調整。常用之材料係如磷化鋁鎵銦(AlGaInP)系列、氮化鋁鎵銦(AlGaInN)系列、氧化鋅(ZnO)系列等。活性層(未顯示)之結構係如:單異質結構(single heterostructure;SH)、雙異質結構(double heterostructure;DH)、雙側雙異質結構(double-side double heterostructure;DDH)、或多層量子井(multi-quantum well;MQW)。再者,調整量子井之對數亦可以改變發光波長。 According to the light-emitting diode described in the embodiment of the present invention, the light-emitting spectrum of the light-emitting diode can be adjusted by changing the physical or chemical elements of the semiconductor single layer or multilayer. Commonly used materials include aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, zinc oxide (ZnO) series, etc. The structure of the active layer (not shown) is such as: single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), or multilayer quantum well (multi-quantum well; MQW). Furthermore, adjusting the logarithm of the quantum well can also change the emission wavelength.

於本發明之一實施例中,第一導電型接觸層11與成長基板10間尚包含一緩衝層(圖未示)。此緩衝層係介於二種材料系統之間,使基板之材料系統”過渡”至半導體系統之材料系統。對發光二極體之結構而言,一方面,緩衝層係用以降低二種材料間晶格不匹配之材料層。另一方面,緩衝層亦可以是用以結合二種材料或二個分離結構之單層、多層或結構,其可選用之材料係如:有機材料、無機材料、金屬、及半導體等;其可選用之結構係如:反射層、導熱層、導電層、、抗形變層、應力釋放(stress release)層、應力調整(stress adjustment) 層、接合(bonding)層、波長轉換層、及機械固定構造等。在一實施例中,此緩衝層之材料可為AlN、GaN、GaInP、InP、GaAs、AlAs,且形成方法可為濺鍍(Sputter)或原子層沉積(Atomic Layer Deposition,ALD)。 In an embodiment of the present invention, a buffer layer (not shown) is further included between the first conductive type contact layer 11 and the growth substrate 10. The buffer layer is between the two material systems, so that the material system of the substrate "transitions" to the material system of the semiconductor system. For the structure of the light-emitting diode, on the one hand, the buffer layer is a material layer used to reduce the lattice mismatch between the two materials. On the other hand, the buffer layer can also be a single layer, multilayer or structure used to combine two materials or two separate structures. The materials that can be used include organic materials, inorganic materials, metals, and semiconductors; The selected structure is such as: reflective layer, thermal conductive layer, conductive layer, anti-deformation layer, stress release layer, stress adjustment Layers, bonding layers, wavelength conversion layers, and mechanical fixing structures. In one embodiment, the material of the buffer layer can be AlN, GaN, GaInP, InP, GaAs, AlAs, and the formation method can be Sputter or Atomic Layer Deposition (ALD).

第二導電型半導體層14上更可選擇性地形成一第二導電型接觸層(未顯示)。接觸層係設置於第二導電型半導體層遠離活性層13之一側。具體而言,第二導電型接觸層可以為光學層、電學層、或其二者之組合。光學層係可以改變來自於或進入活性層(未顯示)的電磁輻射或光線。在此所稱之「改變」係指改變電磁輻射或光之至少一種光學特性,前述特性係包含但不限於頻率、波長、強度、通量、效率、色溫、演色性(rendering index)、光場(light field)、及可視角(angle of view)。電學層係可以使得第二導電型接觸層之任一組相對側間之電壓、電阻、電流、電容中至少其一之數值、密度、分布發生變化或有發生變化之趨勢。第二導電型接觸層之構成材料係包含氧化物、導電氧化物、透明氧化物、具有50%或以上穿透率之氧化物、金屬、相對透光金屬、具有50%或以上穿透率之金屬、有機質、無機質、螢光物、磷光物、陶瓷、半導體、摻雜之半導體、及無摻雜之半導體中至少其一。於某些應用中,第二導電型接觸層之材料係為氧化銦錫、氧化鎘錫、氧化銻錫、氧化銦鋅、氧化鋅鋁、與氧化鋅錫中至少其一。若為相對透光金屬,其厚度係約為0.005μm~0.6μm。 A second conductivity type contact layer (not shown) can be further selectively formed on the second conductivity type semiconductor layer 14. The contact layer is disposed on a side of the second conductivity type semiconductor layer away from the active layer 13. Specifically, the second conductive type contact layer may be an optical layer, an electrical layer, or a combination of the two. The optical layer system can change the electromagnetic radiation or light from or entering the active layer (not shown). "Change" as used herein refers to changing at least one optical characteristic of electromagnetic radiation or light. The aforementioned characteristics include, but are not limited to, frequency, wavelength, intensity, flux, efficiency, color temperature, rendering index, and light field. (light field), and angle of view. The electrical layer can make the value, density, and distribution of at least one of the voltage, resistance, current, and capacitance between any set of opposite sides of the second conductive contact layer change or have a tendency to change. The constituent materials of the second conductive type contact layer include oxides, conductive oxides, transparent oxides, oxides with a transmittance of 50% or more, metals, relatively light-transmitting metals, and those with a transmittance of 50% or more. At least one of metal, organic, inorganic, phosphor, phosphor, ceramic, semiconductor, doped semiconductor, and undoped semiconductor. In some applications, the material of the second conductive type contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. If it is a relatively transparent metal, its thickness is about 0.005μm~0.6μm.

以上各圖式與說明雖僅分別對應特定實施例,然而,各個實施例中所說明或揭露之元件、實施方式、設計準則、及技術原理除在彼此顯相衝突、矛盾、或難以共同實施之外,吾人當可依其所需任意參照、交換、搭配、協調、或合併。 Although the above drawings and descriptions only correspond to specific embodiments respectively, however, the elements, implementations, design criteria, and technical principles described or disclosed in the various embodiments are in conflict, contradictory, or difficult to implement together. In addition, we can refer to, exchange, match, coordinate, or merge as needed.

雖然本發明已說明如上,然其並非用以限制本發明之範圍、實施順序、或使用之材料與製程方法。對於本發明所作之各種修飾與變更,皆不脫本發明之精神與範圍。 Although the present invention has been described above, it is not intended to limit the scope of the present invention, the order of implementation, or the materials and manufacturing methods used. Various modifications and changes made to the present invention do not depart from the spirit and scope of the present invention.

11‧‧‧第一導電型接觸層 11‧‧‧First conductivity type contact layer

12‧‧‧第一導電型半導體層 12‧‧‧First conductivity type semiconductor layer

12a‧‧‧下平面 12a‧‧‧lower plane

13‧‧‧活性層 13‧‧‧Active layer

14‧‧‧第二導電型半導體層 14‧‧‧Second conductivity type semiconductor layer

14a‧‧‧上平面 14a‧‧‧Upper plane

15b‧‧‧第二電性電極 15b‧‧‧Second electrical electrode

15c‧‧‧第二電性延伸電極 15c‧‧‧Second electrical extension electrode

17‧‧‧電性連接層 17‧‧‧Electrical connection layer

18‧‧‧永久基板 18‧‧‧Permanent substrate

19‧‧‧接合層 19‧‧‧Joint layer

20‧‧‧第一隔絕道 20‧‧‧The First Path of Seclusion

21‧‧‧第二隔絕道 21‧‧‧Second Path of Seclusion

22‧‧‧電極絕緣層 22‧‧‧Electrode insulation layer

23‧‧‧絕緣結構 23‧‧‧Insulation structure

24‧‧‧電性連接結構 24‧‧‧Electrical connection structure

25‧‧‧第二電性焊接墊 25‧‧‧Second electrical soldering pad

26‧‧‧電極連接層 26‧‧‧Electrode connection layer

100‧‧‧第一發光二極體 100‧‧‧First LED

50A‧‧‧第一區域 50A‧‧‧First area

50B‧‧‧第二區域 50B‧‧‧Second area

200‧‧‧第二發光二極體 200‧‧‧Second LED

1000‧‧‧發光二極體陣列 1000‧‧‧Light Emitting Diode Array

Claims (10)

一種半導體元件,用以發出一光,該半導體元件包含:一第一半導體疊層,包含一第一區域和一第二區域,該第一區域具有一第一側壁,該第二區域具有一第二側壁;一第二半導體疊層;一第一隔絕道,形成於該第一區域和該第二區域之間;一第二隔絕道,形成於該第一半導體疊層和該第二半導體疊層之間;一絕緣層,形成於該第一隔絕道內並覆蓋該第二側壁,一電性連接層,包含一部分位於該第一半導體疊層之下;以及一電極連接層,直接接觸該電性連接層且覆蓋該第一側壁;其中,該第二區域透過該電性連接層與該電極連接層電連接。 A semiconductor element for emitting a light. The semiconductor element includes: a first semiconductor stack, including a first region and a second region, the first region having a first sidewall, and the second region having a first Two sidewalls; a second semiconductor stack; a first isolation channel formed between the first region and the second region; a second isolation channel formed between the first semiconductor stack and the second semiconductor stack Between the layers; an insulating layer formed in the first isolation channel and covering the second sidewall, an electrical connection layer, including a part located under the first semiconductor stack; and an electrode connection layer, directly contacting the The electrical connection layer covers the first sidewall; wherein, the second area is electrically connected to the electrode connection layer through the electrical connection layer. 如申請專利範圍第1項所述之半導體元件,其中,該電性連接層之該部分於一方向上與該第一區域重疊而不與該第二區域重疊。 The semiconductor device described in claim 1, wherein the portion of the electrical connection layer overlaps with the first area in one direction but does not overlap with the second area. 如申請專利範圍第1項或第2項所述之半導體元件,其中,該第一區域更包含一上表面,該電極連接層覆蓋該上表面。 According to the semiconductor device described in item 1 or item 2 of the scope of the patent application, the first region further includes an upper surface, and the electrode connection layer covers the upper surface. 如申請專利範圍第1項或第2項所述之半導體元件,其中,該第一區域及該第二區域分別依序包含一第一導電型半導體層、一活性層及一第二導電型半導體層,且該第一區域及該第二區域的該第二導電型半導體層彼此相連。 The semiconductor device described in item 1 or item 2 of the scope of patent application, wherein the first region and the second region respectively include a first conductivity type semiconductor layer, an active layer and a second conductivity type semiconductor Layer, and the second conductivity type semiconductor layer of the first region and the second region are connected to each other. 如申請專利範圍第1項或第2項所述之半導體元件,其中,該電性連接層之該部分位於該第一區域之下。 The semiconductor device described in item 1 or item 2 of the scope of patent application, wherein the part of the electrical connection layer is located under the first area. 如申請專利範圍第1項或第2項所述之半導體元件,其中,該第二區域更具有一第三側壁,該絕緣層覆蓋該第三側壁。 According to the semiconductor device described in item 1 or item 2 of the scope of patent application, the second region further has a third side wall, and the insulating layer covers the third side wall. 如申請專利範圍第1項或第2項所述之半導體元件,其中,該第二區域位於該第一區域和該第二半導體疊層之間。 The semiconductor device described in item 1 or item 2 of the scope of patent application, wherein the second region is located between the first region and the second semiconductor stack. 如申請專利範圍第1項或第2項所述之半導體元件,更包含一基板位於該第一半導體疊層之下。 The semiconductor device described in item 1 or item 2 of the scope of the patent application further includes a substrate under the first semiconductor stack. 如申請專利範圍第8項所述之半導體元件,更包含一接合層接合該基板與該第一半導體疊層。 The semiconductor device described in item 8 of the scope of the patent application further includes a bonding layer bonding the substrate and the first semiconductor stack. 如申請專利範圍第8項所述之半導體元件,其中該基板包含氧化鋁。The semiconductor device described in item 8 of the scope of patent application, wherein the substrate comprises alumina.
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US20110089444A1 (en) * 2002-07-15 2011-04-21 Epistar Corporation Light-emitting element
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