TWI721501B - Optoelectronic device and method for manufacturing the same - Google Patents

Abstract

An optoelectronic device, comprising a semiconductor stack having a first conductivity type semiconductor layer, a second conductivity type semiconductor layer formed on the first conductivity type semiconductor layer, and an active layer formed between the second conductivity type semiconductor layer and the first conductivity type semiconductor layer, and a first electrode formed on the second conductivity type semiconductor layer, wherein the first electrode comprises a reflective layer; and an insulating layer formed on the second conductivity type semiconductor layer and having a gap with the first electrode.

Description

Photoelectric element and its manufacturing method

The present invention relates to a photoelectric element, especially to the electrode design of a photoelectric element.

The light-emitting principle of light-emitting diode (LED) is to use the energy difference between electrons moving between n-type semiconductor and p-type semiconductor to release energy in the form of light. This light-emitting principle is different from that of incandescent lamps. The light-emitting principle of heating, so the light-emitting diode is called a cold light source. In addition, light-emitting diodes have the advantages of high durability, long life, light weight, and low power consumption. Therefore, the current lighting market has high expectations for light-emitting diodes and regards them as a new generation of lighting tools, which have gradually replaced the traditional Light source, and used in various fields, such as traffic signs, backlight modules, street lighting, medical equipment, etc.

FIG. 1A is a schematic diagram of the structure of a conventional light-emitting device. As shown in FIG. 1A, the conventional light-emitting device 100 includes a transparent substrate 10, a semiconductor stack 12 on the transparent substrate 10, and at least one electrode 14 on the semiconductor On the stack 12, the above-mentioned semiconductor stack 12 includes at least a first conductivity type semiconductor layer 120, an active layer 122, and a second conductivity type semiconductor layer 124 from top to bottom.

Figure 1B is a schematic diagram of the electrode structure of a conventional light-emitting element. As shown in Figure 1B, the conventional light-emitting element 100' includes a transparent substrate 10, a semiconductor stack 12 on the transparent substrate 10, and at least one electrode 14 on On the semiconductor stack 12 described above, the electrode 14 may include a reflective electrode 141 and a diffusion barrier layer 142. However, because the diffusion barrier layer 142 may not transmit light, the light-emitting efficiency of the light-emitting element 100 is reduced.

In addition, the above-mentioned light-emitting element 100 can be further combined with other elements to form a light-emitting apparatus. FIG. 2 is a schematic diagram of the structure of a conventional light-emitting device. As shown in FIG. 2, a light-emitting device 200 includes a sub-mount 20 having at least one circuit 202; at least one solder (solder) 22 is located on the sub-mount. 20, the above-mentioned light-emitting element 100 is bonded and fixed on the sub-carrier 20 by the solder 22, and the substrate 10 of the light-emitting element 100 and the circuit 202 on the sub-carrier 20 are electrically connected; and, an electrical connection structure 24 to Electrically connect the electrode 14 of the light-emitting element 100 and the circuit 202 on the sub-carrier 20; wherein, the above-mentioned sub-carrier 20 can be a lead frame or a large-size mounting substrate to facilitate the circuit of the light-emitting device 200 Plan and improve its heat dissipation effect.

An optoelectronic device includes: a semiconductor stack, wherein the semiconductor stack includes a first semiconductor layer, a light emitting layer is located on the first semiconductor layer, and a second semiconductor layer is located on the light emitting layer; a first electrode is located On the second semiconductor layer, the first electrode further includes a reflective layer; and an insulating layer is formed on the second semiconductor layer, and the first electrode and the insulating layer have a distance.

The present invention discloses a light-emitting element and its manufacturing method. In order to make the description of the present invention more detailed and complete, please refer to the following description in conjunction with the illustrations in FIGS. 3A to 6.

Figures 3A to 3E are schematic diagrams of the manufacturing process structure of an embodiment of the present invention. As shown in Figure 3A, a substrate 30 is provided, and then a semiconductor epitaxial stack 32 is formed on the substrate 30, wherein the semiconductor epitaxial stack The layer 32 includes a first conductivity type semiconductor layer 321, an active layer 322, and a second conductivity type semiconductor layer 323 from bottom to top.

Next, an insulating layer 34 is formed on the semiconductor epitaxial stack 32 and is in direct contact with the first surface 3211 of the first conductive type semiconductor layer 321 and the first surface 3231 of the second conductive type semiconductor layer 323. After that, a patterned photoresist layer 36 is formed on the first surface 34S of the insulating layer 34, and a part of the first surface 34S of the insulating layer is exposed.

As shown in FIG. 3B, an etching process is performed on the insulating layer 34 by the patterned photoresist layer 36, part of the insulating layer 34 is removed, and a part of the first surface of the first conductive semiconductor layer 321 is exposed. 3211 and a portion of the first surface 3231 of the second conductive type semiconductor layer 323 to form a first insulating layer 341 on a portion of the first surface 3211 of the first conductive type semiconductor layer 321, and a second insulating layer 342 on the second surface 3211. On a portion of the first surface 3231 of the conductive semiconductor layer 323, and a third insulating layer 343 on a portion of the first surface 3231 of the second conductive semiconductor layer 323 and a portion of the first surface of the first conductive semiconductor layer 321 Above 3211.

In one embodiment, the insulating layer 34 may be etched on one side by the patterned photoresist layer 36, so that part of the insulating layer 34 under the patterned photoresist layer 36 is also etched, even if part of the first The insulating layer 341 and the second insulating layer 342 have an undercut shape relative to the patterned photoresist layer 36. Therefore, the edge of the patterned photoresist layer 36 projected on the surface of the semiconductor epitaxial stack 32 has a gap G from the edge of the first insulating layer 341 and the second insulating layer 342 projected on the surface of the semiconductor epitaxial stack 32. In an embodiment, the aforementioned spacing G may be less than 3 μm. In one embodiment, the side etching may be a wet etching.

Then, as shown in FIG. 3C, a first metal layer 382, a second metal layer 381, and a temporary metal layer 383 are simultaneously formed by physical vapor deposition. The first metal layer 382 is formed on the exposed portion of the first surface 3231 of the second conductive semiconductor layer 323; the second metal layer 381 is formed on the exposed portion of the first surface 3211 of the first conductive semiconductor layer 321 And a temporary metal layer 383 is formed on the patterned photoresist layer 36 and covers the upper surface of the patterned photoresist layer 36. In one embodiment, the above-mentioned physical vapor deposition may be vacuum evaporation, sputtering, electron beam evaporation, or ion plating.

In one embodiment, because the patterned photoresist layer 36 has an undercut shape, the sidewalls of the first metal layer 382 will not directly contact the sidewalls of the third insulating layer 343 and the second insulating layer 342. In addition, the sidewalls of the second metal layer 381 will not directly contact the sidewalls of the first insulating layer 341 and the third insulating layer 343 described above.

In one embodiment, the first metal layer 382 may be a plurality of stacked layers, and may include a reflective layer, and the material of the reflective layer may be selected from materials with a reflectance greater than 90%. In one embodiment, the material of the reflective layer in the first metal layer can be selected from chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum ( Metal materials such as Al), tungsten (W), tin (Sn), or silver (Ag).

Then, as shown in FIG. 3D, the patterned photoresist layer 36 and the temporary metal layer 383 thereon are removed. In one embodiment, as shown in FIG. 3D, the first surface 3211 from the second metal layer 381 to the first conductive semiconductor layer 321 may have a height h1, and the first insulating layer 341 to the first conductive semiconductor layer The first surface 3211 of the 321 can have a height h2. Through the above-mentioned process of the present invention, the second metal layer 381 and the first insulating layer 341 can have similar heights or the height difference between the second metal layer 381 and the first insulating layer 341 Less than 1μm. In an embodiment, the second metal layer 381 and the first insulating layer 341 may have a distance d1, and the distance d1 is less than 3 μm, and/or the second metal layer 381 and the third insulating layer 343 may have a distance d2, And the distance d2 is less than 3 μm. In an embodiment, d1 and d2 may have the same value.

In another embodiment, the first surface 3231 of the first metal layer 382 to the second conductivity type semiconductor layer 323 may have a height h3, and the second insulating layer 342 to the first surface 3231 of the second conductivity type semiconductor layer 323 It can have a height h4. According to the process disclosed in the above-mentioned embodiment, the first metal layer 382 and the second insulating layer 342 can have similar heights or the height difference between the first metal layer 382 and the second insulating layer 342 is less than 1 μm. In an embodiment, the first metal layer 382 and the second insulating layer 342 can have a distance d3, and the distance d3 is less than 3 μm, and/or the first metal layer 382 and the third insulating layer 343 can have a distance d4, And the distance d4 is less than 3 μm. In an embodiment, d3 and d4 may have the same value. In another embodiment, d1, d2, d3, and d4 may have the same value.

Finally, as shown in FIG. 3E, a third metal layer 42 is formed on the first metal layer 382, and a fourth metal layer 40 is formed on the second metal layer 381 to complete the photovoltaic device 300 of the present invention. In one embodiment, part of the fourth metal layer 40 directly contacts the first surface 3211 of the first conductivity type semiconductor layer 321, or part of the third metal layer 42 directly contacts the first surface 3231 of the second conductivity type semiconductor layer 323 . In one embodiment, there is almost no second insulating layer 342 under the third metal layer 42. In another example, the top of the third metal layer 42 and the second surface 3212 of the first semiconductor layer 321 have a shortest distance d6, and the top of the fourth metal layer 40 and the second surface 3212 of the first semiconductor layer 321 have the shortest distance d6. A shortest distance d5, and the difference between d6 and d5 is less than 1μm. In one embodiment, the projections of the third metal layer 42 and the fourth metal layer 40 in the direction perpendicular to the normal line of the substrate 30 may have similar areas.

In one embodiment, following the above-mentioned 3D diagram or 3E diagram, the substrate 30 may be removed and a portion of the second surface 3212 of the first conductive type semiconductor layer 321 may be exposed to form a thin-film flip chip (thin-film flip chip). flip chip). In one embodiment, following the above-mentioned 3D or 3E, the first metal layer 382 and the second metal layer 381 or the third metal layer 42 and the fourth metal layer 40 can combine the photoelectric device 300 of the present invention Connect to a carrier board (not shown) to form a flip chip package. In an embodiment, the material of the first metal layer 382, the second metal layer 381, the third metal layer 42, or the fourth metal layer 40 includes but is not limited to copper (Cu), aluminum (Al), indium (In), tin (Sn), gold (Au), platinum (Pt), zinc (Zn), silver (Ag), titanium (Ti), nickel (Ni), lead (Pb), palladium (Pd), germanium (Ge), chromium (Cr), cadmium (Cd), cobalt (Co), manganese (Mn), antimony (Sb), bismuth (Bi), gallium (Ga), thallium (Tl), polonium (Po), iridium (Ir), rhenium (Re), rhodium (Rh), osmium (Os), tungsten (W), lithium (Li), sodium (Na), potassium (K), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zirconium (Zr), molybdenum (Mo), sodium (La), silver-titanium (Ag-Ti), copper-tin (Cu-Sn), copper-zinc (Cu-Zn) , Copper-cadmium (Cu-Cd), tin-lead-antimony (Sn-Pb-Sb), tin-lead-zinc (Sn-Pb-Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni -Co), gold alloy (Au alloy), or germanium-gold-nickel (Ge-Au-Ni) and other metal materials.

Figures 4A to 4C are schematic diagrams showing a light-emitting module. Figure 4A shows an external perspective view of a light-emitting module. A light-emitting module 500 may include a carrier 502, a plurality of lenses 504, 506, 508, and 510, and two power supply terminals 512 and 514.

Figures 4B-4C show a cross-sectional view of a light-emitting module, and Figure 4C is an enlarged view of area E in Figure 4B. The carrier 502 may include an upper carrier 503 and a download body 501, wherein a surface of the download body 501 can be in contact with the upper carrier 503. The lenses 504 and 508 are formed on the upper carrier 503. The upper carrier 503 may form at least one through hole 515, and the light emitting diode device 300 formed according to the embodiment of the present invention may be formed in the through hole 515 and contact the download body 501 and be surrounded by the glue 521. There is a lens 508 on the glue 521.

As shown in FIG. 4C, in one embodiment, a reflective layer 519 may be formed on the two sidewalls of the through hole 515 to increase light extraction efficiency; a metal layer 517 may be formed on the lower surface of the download body 501 to improve heat dissipation efficiency.

Figures 5A-5B illustrate a schematic diagram 600 of a light source generating device 600. A light source generating device 600 may include a light emitting module 500, a housing 540, a power supply system (not shown) to supply the light source generating device 600 with a current, And a control element (not shown) for controlling the power supply system (not shown). The light source generating device 600 may be a lighting device, such as a street lamp, a car lamp, or an indoor lighting source, or a traffic sign or a backlight source of a backlight module in a flat-panel display.

Figure 6 shows a schematic diagram of a light bulb. The bulb 700 includes a housing 921, a lens 922, an illumination module 924, a bracket 925, a heat sink 926, a serial connection portion 927 and an electrical serial connector 928. The lighting module 924 includes a carrier 923, and at least one light-emitting diode element 300 in the above-mentioned embodiment is included on the carrier 923.

Specifically, the optoelectronic element 300 includes a light emitting diode (LED), a photodiode, a photoresistor, a laser, an infrared emitter, and an organic light emitting diode. At least one of (organic light-emitting diode) and solar cell (solar cell). The substrate 30 is a growth and/or supporting foundation. Candidate materials may include conductive or non-conductive substrates, light-transmitting substrates or non-light-transmitting substrates. One of the conductive substrate materials can be germanium (Ge), gallium arsenide (GaAs), indium phosphorus (InP), silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO) ), gallium nitride (GaN), aluminum nitride (AlN), metal. One of the transparent substrate materials can be sapphire (Sapphire), lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, and diamond-like carbon (Diamond-Like Carbon; DLC), spinel (spinel, MgAl ₂ O ₄ ), alumina (Al ₂ O ₃ ), silicon _{oxide (SiO X} ) and lithium gallate (LiGaO ₂ ).

The first conductive type semiconductor layer 321 and the second conductive type semiconductor layer 323 are different in electrical properties, polarity or dopants, and are used to provide electrons and holes, respectively, in a single-layer or multilayer structure of semiconductor materials ("multi-layer" refers to For two or more layers, the same applies below.) The electrical selection can be a combination of at least any two of p-type, n-type, and i-type. The active layer 322 is located between the above-mentioned two parts with different electrical properties, polarities or dopants, or between the semiconductor materials used to provide electrons and holes, respectively. It is a possible conversion or induced conversion between electrical energy and light energy. area. Those that convert or induce light energy are light-emitting diodes, liquid crystal displays, and organic light-emitting diodes; those that convert light energy or induce light energy are such as solar cells and photodiodes. The material of the semiconductor epitaxial stack 32 includes one or more elements selected from gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), and silicon ( Si) constitute a group. Commonly used materials include group III nitrides such as aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, and zinc oxide (ZnO) series. The structure of the active layer 322 is such as: single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), or multilayer quantum well (multi- quantum well; MQW) structure. When the optoelectronic device 300 is a light-emitting diode, its light-emitting spectrum can be adjusted by changing the physical or chemical elements of the semiconductor single layer or multiple layers. Furthermore, adjusting the logarithm of the quantum well can also change the emission wavelength.

In an embodiment of the present invention, a buffer layer (not shown) may optionally be included between the semiconductor epitaxial stack 32 and the substrate 30. The buffer layer is between the two material systems, so that the material system of the substrate "transitions" to the material system of the semiconductor system. For the structure of the light-emitting diode, on the one hand, the buffer layer is a material layer used to reduce the lattice mismatch between the two materials. On the other hand, the buffer layer can also be a single layer, multi-layer or structure used to combine two materials or two separate structures. The materials that can be used include organic materials, inorganic materials, metals, and semiconductors; The selected structure is such as: reflective layer, thermal conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment layer, bonding layer, wavelength Conversion layer, and mechanical fixing structure, etc.

A contact layer (not shown) can be formed on the semiconductor epitaxial stack 32 more selectively. The contact layer is disposed on a side of the semiconductor epitaxial stack 32 away from the substrate 30. Specifically, the contact layer may be an optical layer, an electrical layer, or a combination of the two. The optical layer system can change the electromagnetic radiation or light coming from or entering the active layer. "Change" as used herein refers to changing at least one optical characteristic of electromagnetic radiation or light. The aforementioned characteristics include, but are not limited to, frequency, wavelength, intensity, flux, efficiency, color temperature, rendering index, and light field. (Light field), and angle of view. The electrical layer can make the value, density, and distribution of at least one of the voltage, resistance, current, and capacitance between any set of opposite sides of the contact layer change or have a tendency to change. The constituent materials of the contact layer include oxides, conductive oxides, transparent oxides, oxides with a transmittance of 50% or more, metals, relatively light-transmitting metals, metals with a transmittance of 50% or more, organic substances, At least one of inorganic substances, phosphors, phosphors, ceramics, semiconductors, doped semiconductors, and undoped semiconductors. In some applications, the material of the contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. If it is a relatively light-transmitting metal, its thickness is preferably about 0.005 μm to 0.6 μm. In one embodiment, since the contact layer has a better lateral current diffusion rate, it can be used to facilitate the uniform diffusion of current into the semiconductor epitaxial stack 32. Generally speaking, it varies according to the impurity doped in the contact layer and the manufacturing process, and the energy gap width can be between 0.5 eV and 5 eV.

Although the above drawings and descriptions only correspond to specific embodiments respectively, however, the elements, implementations, design criteria, and technical principles described or disclosed in the various embodiments are in conflict with each other, contradictory, or difficult to implement together. In addition, we should be free to refer to, exchange, match, coordinate, or merge as needed. Although the present invention has been described above, it is not intended to limit the scope of the present invention, the order of implementation, or the materials and manufacturing methods used. Various modifications and changes made to the present invention do not depart from the spirit and scope of the present invention.

100，100’‧‧‧Light-emitting element

200‧‧‧Lighting device

202‧‧‧Circuit

20‧‧‧Sub-mount

22‧‧‧Solder

24‧‧‧Electrical connection structure

10‧‧‧Transparent substrate

12‧‧‧Semiconductor stack

14‧‧‧Electrode

141‧‧‧Reflective electrode

142‧‧‧Diffusion barrier

120, 321‧‧‧The first conductivity type semiconductor layer

122,322‧‧‧active layer

124, 323‧‧‧Second conductivity type semiconductor layer

300‧‧‧Light-Emitting Diode Components

30‧‧‧Substrate

32‧‧‧Semiconductor epitaxial stack

34‧‧‧Insulation layer

341‧‧‧First insulation layer

342‧‧‧Second insulating layer

343‧‧‧Third insulation layer

3211‧‧‧The first surface of the first conductivity type semiconductor layer

3231‧‧‧The first surface of the second conductivity type semiconductor layer

36‧‧‧Patterned photoresist layer

34S‧‧‧First surface

G‧‧‧Pitch

382‧‧‧First metal layer

381‧‧‧Second metal layer

383‧‧‧Temporary metal layer

42‧‧‧The third metal layer

40‧‧‧The fourth metal layer

500‧‧‧Lighting Module

502‧‧‧Carrier

504, 506, 508, 510‧‧‧ lens

512, 514‧‧‧Power supply terminal

503‧‧‧Upper carrier

501‧‧‧Download

515‧‧‧Through hole

517‧‧‧Metal layer

519‧‧‧Reflective layer

600‧‧‧Schematic diagram of light source generating device

700‧‧‧Bulb

921‧‧‧Shell

922‧‧‧lens

923‧‧‧Carrier

924‧‧‧Lighting Module

925‧‧‧bracket

926‧‧‧Radiator

927‧‧‧Tandem section

928‧‧‧Electric Serial Connector

Figures 1A-1B are a structural diagram showing a side view structural diagram of a conventional array light-emitting diode element;

Figure 2 is a schematic diagram showing the structure of a conventional light-emitting device;

Figures 3A-3E are schematic diagrams of the manufacturing process structure of an embodiment of the present invention;

4A to 4C are schematic diagrams showing a light-emitting module;

Figures 5A-5B illustrate a schematic diagram of a light source generating device; and

Figure 6 shows a schematic diagram of a light bulb.

30‧‧‧Substrate

32‧‧‧Epitaxial stack

3211、3231‧‧‧First surface

3212‧‧‧Second surface

341‧‧‧First insulation layer

342‧‧‧Second insulating layer

343‧‧‧Third insulation layer

382‧‧‧First metal layer

381‧‧‧Second metal layer

d5、d6‧‧‧spacing

42‧‧‧The third metal layer

40‧‧‧The fourth metal layer

300‧‧‧Optical Components

Claims (10)

A photoelectric element, comprising: a substrate; a semiconductor stack, wherein the semiconductor stack includes a first semiconductor layer, a light emitting layer is located on the first semiconductor layer, and a second semiconductor layer is located on the light emitting layer An insulating layer, including a top portion directly contacting the first semiconductor layer and another portion directly contacting the second semiconductor layer; a first metal layer located on the second semiconductor layer; a second A metal layer located on the first semiconductor layer and directly contacting the first semiconductor layer; a third metal layer located on the first metal layer and the second semiconductor layer; and a fourth metal layer directly contacting The second metal layer is located on the first semiconductor layer and the second semiconductor layer, wherein the top of the third metal layer and a second surface of the first semiconductor layer have a shortest distance d6, the fourth metal The top of the layer and the second surface of the first semiconductor layer have a shortest distance d5, and the difference between d6 and d5 is less than 1 μm, and the third metal layer and the fourth metal layer directly contact the insulating layer; the first The top of the two metal layers and a first surface of the first semiconductor layer have a height h1, and the top of the portion of the insulating layer and the first surface of the first semiconductor layer have a height h2, and h1 and The difference in h2 is less than 1μm. According to the optoelectronic device described in claim 1, wherein the projections of the third metal layer and the fourth metal layer in a direction perpendicular to a normal line of the substrate have similar areas. The optoelectronic device according to claim 1, wherein the top of the first metal layer to the top of the second semiconductor layer has a height h3, and the top of the other part of the insulating layer is to the second semiconductor layer The top of the layer has a height h4, and the height h3 is similar to the height h4 or the difference between the height h3 and the height h4 is less than 1 μm. The optoelectronic device according to claim 1, wherein the second metal layer is formed between the first semiconductor layer and the fourth metal layer, and there is a gap between the second metal layer and the insulating layer . The optoelectronic device according to claim 1, wherein the insulating layer includes a first insulating layer located on the first surface of the first semiconductor layer, and a second insulating layer located on the first surface of the second semiconductor layer. A surface and a third insulating layer are located on the first surface of the second semiconductor layer and on the first surface of the first semiconductor layer. . According to the photoelectric element described in claim 1, wherein the first metal layer and the insulating layer have a distance. For the optoelectronic element described in item 4 or item 6 of the scope of patent application, the pitch is less than 3 μm. The optoelectronic element according to the first item of the patent application, wherein the materials of the first semiconductor layer, the light-emitting layer and the second semiconductor layer include aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) Series and other III nitride or zinc oxide (ZnO) series. According to the photoelectric element described in claim 1, wherein the materials of the first metal layer, the second metal layer, the third metal layer and the fourth metal layer can be selected from chromium (Cr), titanium (Ti) ), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), tungsten (W), tin (Sn), or silver (Ag) and other metal materials. A light-emitting module includes the photoelectric element described in item 1 of the scope of patent application; and a carrier board; wherein the carrier board is electrically connected to the third metal layer and the fourth metal layer.

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