TW201941456A - Optoelectronic device and method for manufacturing the same - Google Patents

Abstract

An optoelectronic device, comprising a semiconductor stack having a first conductivity type semiconductor layer, a second conductivity type semiconductor layer formed on the first conductivity type semiconductor layer, and an active layer formed between the second conductivity type semiconductor layer and the first conductivity type semiconductor layer, and a first electrode formed on the second conductivity type semiconductor layer, wherein the first electrode comprises a reflective layer; and an insulating layer formed on the second conductivity type semiconductor layer and having a gap with the first electrode.

Description

Photoelectric element and manufacturing method thereof

The invention relates to a photovoltaic element, in particular to an electrode design of a photovoltaic element.

The light emitting principle of a light-emitting diode (LED) is to use the energy difference between electrons moving between an n-type semiconductor and a p-type semiconductor to release energy in the form of light. Such a light-emitting principle is different from an incandescent lamp The light emitting principle of heat generation, so the light emitting diode is called a cold light source. In addition, light-emitting diodes have the advantages of high durability, long life, light weight, and low power consumption. Therefore, the current lighting market has high hopes for light-emitting diodes and regards them as a new generation of lighting tools. Light source, and is used in various fields, such as traffic signs, backlight modules, street lighting, medical equipment, etc.

FIG. 1A is a schematic view of a conventional light-emitting element structure. As shown in FIG. 1A, the conventional light-emitting element 100 includes a transparent substrate 10, a semiconductor stack 12 on the transparent substrate 10, and at least one electrode 14 on the semiconductor. On the stack 12, the above-mentioned semiconductor stack 12 includes at least a first conductive type semiconductor layer 120, an active layer 122, and a second conductive type semiconductor layer 124 from top to bottom.

FIG. 1B is a schematic diagram of a conventional light-emitting element electrode structure. As shown in FIG. 1B, the conventional light-emitting element 100 ′ includes a transparent substrate 10, a semiconductor stack 12 on the transparent substrate 10, and at least one electrode 14 on On the semiconductor stack 12, the electrode 14 may include a reflective electrode 141 and a diffusion barrier layer 142. However, because the diffusion barrier layer 142 may be unable to transmit light, the light emitting efficiency of the light emitting device 100 is reduced.

In addition, the above-mentioned light-emitting element 100 can be further combined with other elements to form a light-emitting apparatus. FIG. 2 is a schematic structural diagram of a conventional light emitting device. As shown in FIG. 2, a light emitting device 200 includes a sub-mount 20 having at least one circuit 202; at least one solder 22 is located on the sub-carrier. 20, the above-mentioned light-emitting element 100 is adhered and fixed on the sub-carrier 20 by the solder 22, and the substrate 10 of the light-emitting element 100 is electrically connected to the circuit 202 on the sub-carrier 20; and an electrical connection structure 24 The electrode 14 of the light-emitting element 100 is electrically connected to the circuit 202 on the sub-carrier 20. The above-mentioned sub-carrier 20 may be a lead frame or a large-sized mounting substrate to facilitate the circuit of the light-emitting device 200 Plan and improve its cooling effect.

A photovoltaic element includes: a semiconductor stack, wherein the semiconductor stack includes a first semiconductor layer, a light emitting layer is located on the first semiconductor layer, and a second semiconductor layer is located on the light emitting layer; a first electrode is located on On the second semiconductor layer, the first electrode further includes a reflective layer; and an insulating layer is formed on the second semiconductor layer, and the first electrode and the insulating layer have a gap.

The present invention discloses a light emitting element and a manufacturing method thereof. In order to make the description of the present invention more detailed and complete, please refer to the following description and cooperate with the diagrams of FIGS. 3A to 6.

3A to 3E are schematic diagrams showing the manufacturing process structure according to an embodiment of the present invention. As shown in FIG. 3A, a substrate 30 is provided, and then a semiconductor epitaxial stack 32 is formed on the substrate 30. The semiconductor epitaxial stack The layer 32 includes a first conductive type semiconductor layer 321, an active layer 322, and a second conductive type semiconductor layer 323 from bottom to top.

Next, an insulating layer 34 is formed on the semiconductor epitaxial stack 32 and is in direct contact with the first surface 3211 of the first conductive type semiconductor layer 321 and the first surface 3231 of the second conductive type semiconductor layer 323. After that, a patterned photoresist layer 36 is formed on the first surface 34S of the insulating layer 34, and a part of the first surface 34S of the insulating layer is exposed.

As shown in FIG. 3B, an etching process is performed on the insulating layer 34 by using the patterned photoresist layer 36, a part of the insulating layer 34 is removed, and a part of the first surface of the first conductive semiconductor layer 321 is exposed. 3211 and a portion of the first surface 3231 of the second conductive type semiconductor layer 323 to form a first insulating layer 341 on a portion of the first surface 3211 of the first conductive type semiconductor layer 321 and a second insulating layer 342 on the second A portion of the first surface 3231 of the conductive semiconductor layer 323 and a third insulating layer 343 on a portion of the first surface 3231 of the second conductive semiconductor layer 323 and a portion of the first surface of the first conductive semiconductor layer 321 Above 3211.

In one embodiment, the insulating layer 34 can be etched on one side by the patterned photoresist layer 36, so that part of the insulating layer 34 below the patterned photoresist layer 36 is also etched, even if part of the first The insulating layer 341 and the second insulating layer 342 have an undercut shape with respect to the patterned photoresist layer 36. Therefore, the edge of the patterned photoresist layer 36 projected on the surface of the semiconductor epitaxial stack 32 will have a gap G from the edge of the first insulating layer 341 and the second insulating layer 342 projected on the surface of the semiconductor epitaxial stack 32. In one embodiment, the pitch G may be less than 3 μm. In one embodiment, the above-mentioned side etching may be a wet etching.

Next, as shown in FIG. 3C, a first metal layer 382, a second metal layer 381, and a temporary metal layer 383 are simultaneously formed by physical vapor deposition. The first metal layer 382 is formed on a portion of the first surface 3231 where the second conductive type semiconductor layer 323 is exposed. The second metal layer 381 is formed on the portion of the first surface 3211 where the first conductive type semiconductor layer 321 is exposed. ; And the temporary metal layer 383 is formed on the patterned photoresist layer 36 and covers the upper surface of the patterned photoresist layer 36. In one embodiment, the physical vapor deposition may be vacuum evaporation, sputtering, electron beam evaporation, or ion plating.

In one embodiment, because the patterned photoresist layer 36 has an undercut shape, the sidewall of the first metal layer 382 does not directly contact the sidewalls of the third insulating layer 343 and the second insulating layer 342. In addition, the sidewall of the second metal layer 381 does not directly contact the sidewalls of the first insulating layer 341 and the third insulating layer 343.

In one embodiment, the first metal layer 382 may be a plurality of stacked layers and may include a reflective layer. The material of the reflective layer may be selected from materials with a reflectance greater than 90%. In an embodiment, the material of the reflective layer in the first metal layer may be selected from chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), hafnium (Au), aluminum ( Al), tungsten (W), tin (Sn), or silver (Ag) is a metal material.

Next, as shown in FIG. 3D, the patterned photoresist layer 36 and the temporary metal layer 383 thereon are removed. In an embodiment, as shown in FIG. 3D, the first surface 3211 of the second metal layer 381 to the first conductive type semiconductor layer 321 may have a height h1, and the first insulating layer 341 to the first conductive type semiconductor layer The first surface 3211 of 321 may have a height h2. Through the above process of the present invention, the second metal layer 381 and the first insulating layer 341 may have similar heights or the height difference between the second metal layer 381 and the first insulating layer 341. Less than 1 μm. In one embodiment, the second metal layer 381 and the first insulation layer 341 may have a distance d1, and the distance d1 is less than 3 μm, and / or the second metal layer 381 and the third insulation layer 343 may have a distance d2, And this distance d2 is less than 3 μm. In an embodiment, d1 and d2 may have the same value.

In another embodiment, the first surface 3231 of the first metal layer 382 to the second conductive type semiconductor layer 323 may have a height h3, and the second insulating layer 342 to the first surface 3231 of the second conductive type semiconductor layer 323 It may have a height h4. According to the process disclosed in the above embodiment, the first metal layer 382 and the second insulating layer 342 may have similar heights or the height difference between the first metal layer 382 and the second insulating layer 342 is less than 1 μm. In an embodiment, the first metal layer 382 and the second insulation layer 342 may have a distance d3, and the distance d3 is less than 3 μm, and / or the first metal layer 382 and the third insulation layer 343 may have a distance d4, And this distance d4 is less than 3 μm. In an embodiment, d3 and d4 may have the same value. In another embodiment, d1, d2, d3, and d4 may have the same value.

Finally, as shown in FIG. 3E, a third metal layer 42 is formed on the first metal layer 382, and a fourth metal layer 40 is formed on the second metal layer 381 to complete the photovoltaic device 300 of the present invention. In one embodiment, part of the fourth metal layer 40 is in direct contact with the first surface 3211 of the first conductive type semiconductor layer 321, or part of the third metal layer 42 is in direct contact with the first surface 3231 of the second conductive type semiconductor layer 323. . In one embodiment, there is almost no second insulating layer 342 under the third metal layer 42. In another example, the top of the third metal layer 42 and the second surface 3212 of the first semiconductor layer 321 have a shortest distance d6, and the top of the fourth metal layer 40 and the second surface 3212 of the first semiconductor layer 321 have a shortest distance d6. A shortest distance d5, and the difference between d6 and d5 is less than 1 μm. In an embodiment, the projections of the third metal layer 42 and the fourth metal layer 40 in the normal direction of the vertical substrate 30 may have similar areas.

In one embodiment, after the above 3D or 3E drawings, the substrate 30 may be removed and a portion of the second surface 3212 of the first conductive semiconductor layer 321 may be exposed to form a thin-film flip-chip. flip chip). In an embodiment, following the above-mentioned 3D or 3E drawings, the photovoltaic device 300 of the present invention may be formed by the first metal layer 382 and the second metal layer 381 or the third metal layer 42 and the fourth metal layer 40. Connected to a carrier board (not shown) to form a flip chip package. In one embodiment, the material of the first metal layer 382, the second metal layer 381, the third metal layer 42 or the fourth metal layer 40 includes, but is not limited to, copper (Cu), aluminum (Al), indium (In), and tin. (Sn), gold (Au), platinum (Pt), zinc (Zn), silver (Ag), titanium (Ti), nickel (Ni), lead (Pb), palladium (Pd), germanium (Ge), chromium (Cr), cadmium (Cd), cobalt (Co), manganese (Mn), antimony (Sb), bismuth (Bi), gallium (Ga), thorium (Tl), thorium (Po), iridium (Ir), thorium (Re), rhodium (Rh), thorium (Os), tungsten (W), lithium (Li), sodium (Na), potassium (K), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zirconium (Zr), molybdenum (Mo), sodium (La), silver-titanium (Ag-Ti), copper-tin (Cu-Sn), copper-zinc (Cu-Zn) , Copper-cadmium (Cu-Cd), tin-lead-antimony (Sn-Pb-Sb), tin-lead-zinc (Sn-Pb-Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni -Co), Au alloy, or germanium-gold-nickel (Ge-Au-Ni).

4A to 4C are schematic diagrams of a light emitting module, and FIG. 4A is a perspective view of an external light emitting module. A light emitting module 500 may include a carrier 502, a plurality of lenses 504, 506, 508, and 510, and two power supply terminals 512 and 514.

Figures 4B-4C are cross-sectional views of a light-emitting module, and Figure 4C is an enlarged view of area E in Figure 4B. The carrier 502 may include an upper carrier 503 and a download body 501, wherein a surface of the download body 501 may be in contact with the upper carrier 503. The lenses 504 and 508 are formed on the upper carrier 503. The upper carrier 503 may form at least one through-hole 515, and the light-emitting diode element 300 formed according to the embodiment of the present invention may be formed in the above-mentioned through-hole 515 and contact the download body 501, and is surrounded by the adhesive material 521. A lens 508 is provided on the adhesive 521.

As shown in FIG. 4C, in one embodiment, a reflective layer 519 may be formed on both sidewalls of the through hole 515 to increase light extraction efficiency; a metal layer 517 may be formed on the lower surface of the download body 501 to improve heat dissipation efficiency.

5A-5B are schematic diagrams 600 of a light source generating device. A light source generating device 600 may include a light emitting module 500, a housing 540, and a power supply system (not shown) to supply the light source generating device 600 with a current, And a control element (not shown) for controlling the power supply system (not shown). The light source generating device 600 may be a lighting device, such as a street light, a car light or an indoor lighting light source, or a traffic light or a backlight light source of a backlight module in a flat panel display.

Figure 6 is a schematic diagram of a light bulb. The bulb 700 includes a housing 921, a lens 922, a lighting module 924, a bracket 925, a heat sink 926, a series connection portion 927, and an electrical series connector 928. The lighting module 924 includes a carrier 923, and the carrier 923 includes at least one light-emitting diode element 300 in the above embodiment.

Specifically, the photovoltaic element 300 series includes a light emitting diode (LED), a photodiode, a photoresistor, a laser, an infrared emitter, and an organic light emitting diode. (Organic light-emitting diode) and solar cell (solar cell). The substrate 30 is a growth and / or carrying foundation. The candidate material may include a conductive substrate or a non-conductive substrate, a light-transmitting substrate, or a light-opaque substrate. One of the conductive substrate materials may be germanium (Ge), gallium arsenide (GaAs), indium phosphorus (InP), silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO ), Gallium nitride (GaN), aluminum nitride (AlN), metal. One of the light-transmitting substrate materials may be sapphire, lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, and diamond-like carbon (Diamond-Like Carbon; DLC), spinel (MgAl ₂ O ₄ ), aluminum oxide (Al ₂ O ₃ ), silicon oxide (SiO _X ), and lithium gallate (LiGaO ₂ ).

The above-mentioned first conductive type semiconductor layer 321 and the second conductive type semiconductor layer 323 are electrically, polar, or dopant-different semiconductor materials that are used to provide electrons and holes, respectively, in a single-layer or multilayer structure ("multilayer" means Two or more layers, the same below.) The electrical selection can be a combination of at least any two of p-type, n-type, and i-type. The active layer 322 is located between the above two parts with different electrical properties, polarities or dopants, or between semiconductor materials used to provide electrons and holes, respectively. It is possible that electrical energy and light energy may be converted or induced conversion. region. Those who convert or induce light energy such as light-emitting diodes, liquid crystal displays, and organic light-emitting diodes; those who convert or induce light energy such as solar cells, photovoltaic diodes. The material of the semiconductor epitaxial stack 32 includes one or more elements selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), and silicon ( Si). Commonly used materials are group III nitrides such as aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, and zinc oxide (ZnO) series. The structure of the active layer 322 is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multilayer quantum well (multi- quantum well (MQW) structure. When the photovoltaic element 300 is a light emitting diode, its light emission spectrum can be adjusted by changing the physical or chemical elements of the semiconductor single layer or multiple layers. Furthermore, adjusting the logarithm of the quantum well can also change the emission wavelength.

In one embodiment of the present invention, the semiconductor epitaxial stack 32 and the substrate 30 may optionally include a buffer layer (not shown). This buffer layer is between the two metal material systems, which "transitions" the material system of the substrate to the material system of the semiconductor system. As for the structure of the light emitting diode, on the one hand, the buffer layer is a material layer for matching the lattice between the two materials. On the other hand, the buffer layer can also be a single layer, multiple layers, or structure that is used to combine two types of materials or two separate structures. The materials that can be used include organic materials, inorganic materials, metals, and semiconductors. Selected structures are: reflective layer, thermally conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment layer, bonding layer, wavelength Conversion layer and mechanical fixing structure.

A contact layer (not shown) may be selectively formed on the semiconductor epitaxial stack 32. The contact layer is disposed on one side of the semiconductor epitaxial stack 32 and the substrate 30. Specifically, the contact layer may be an optical layer, an electrical layer, or a combination thereof. The optical layer system can change the electromagnetic radiation or light emitted from or into the active layer. As used herein, "change" refers to changing at least one optical characteristic of electromagnetic radiation or light. The aforementioned characteristics include, but are not limited to, frequency, wavelength, intensity, general efficiency, efficiency, color temperature, rendering index, and light field. (Light field), and angle of view. The electrical layer can make the voltage, resistance, voltage, and capacitance of at least one of the opposite sides of the contact layer change, the density, the distribution, or the tendency to change. The constituent materials of the contact layer include oxides, conductive oxides, transparent oxides, oxides with 50% or more penetrations, metal, relatively translucent metals, metals with 50% or more transmission, organic matter, At least one of an inorganic substance, a phosphor, a phosphor, a ceramic, a semiconductor, a doped semiconductor, and an undoped semiconductor. In some applications, the material of the contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. Rhenium is a relatively light-transmitting genus, and its thickness is preferably about 0.005 μm to 0.6 μm. In one embodiment, since the contact layer has a better lateral current diffusion rate, it can be used to help the current to evenly diffuse into the semiconductor epitaxial stack 32. Generally speaking, it varies according to the impurities mixed in the contact layer and the method of the process, and the width of the energy gap can be between 0.5eV and 5eV.

Although the above drawings and descriptions only correspond to specific embodiments, however, the elements, implementations, design guidelines, and technical principles described or disclosed in each embodiment are inconsistent, contradictory, or difficult to implement together. In addition, we shall be free to refer, exchange, match, coordinate, or merge as needed. Although the present invention has been described as above, it is not intended to limit the scope, implementation order, or materials and manufacturing methods of the present invention. Various modifications and changes made without departing from the spirit and scope of the invention.

100，100’‧‧‧‧Light-emitting element

200‧‧‧light-emitting device

202‧‧‧Circuit

20‧‧‧ sub-mount

22‧‧‧solder

24‧‧‧ Electrical connection structure

10‧‧‧ transparent substrate

12‧‧‧ semiconductor stack

14‧‧‧ electrode

141‧‧‧Reflective electrode

142‧‧‧ Diffusion barrier

120,321‧‧‧first conductive semiconductor layer

122, 322‧‧‧active layer

124,323‧‧‧Second Conductive Semiconductor Layer

300‧‧‧ Light Emitting Diode Element

30‧‧‧ substrate

32‧‧‧Semiconductor Epitaxial Stack

34‧‧‧ Insulation

341‧‧‧First insulation layer

342‧‧‧Second insulation layer

343‧‧‧third insulating layer

3211‧‧‧First surface of first conductive semiconductor layer

3231‧‧‧ the first surface of the second conductive semiconductor layer

36‧‧‧patterned photoresist layer

34S‧‧‧First surface

G‧‧‧Pitch

382‧‧‧first metal layer

381‧‧‧Second metal layer

383‧‧‧Temporary metal layer

42‧‧‧ third metal layer

40‧‧‧ Fourth metal layer

500‧‧‧light emitting module

502‧‧‧ carrier

504, 506, 508, 510‧‧‧ lens

512, 514‧‧‧ Power Supply Terminal

503‧‧‧ on carrier

501‧‧‧ download

515‧‧‧through hole

517‧‧‧metal layer

519‧‧‧Reflective layer

600‧‧‧ Light source generating device

700‧‧‧ bulb

921‧‧‧Shell

922‧‧‧ lens

923‧‧‧ carrier

924‧‧‧lighting module

925‧‧‧ bracket

926‧‧‧ Radiator

927‧‧‧Concatenation Department

928‧‧‧Electric connector

Figures 1A-1B are structural diagrams showing a side view structural diagram of a conventional array light emitting diode element;

FIG. 2 is a schematic diagram showing the structure of a conventional light emitting device;

3A-3E are schematic structural diagrams of a manufacturing process according to an embodiment of the present invention;

4A to 4C are schematic diagrams of a light emitting module;

5A-5B are schematic diagrams of a light source generating device; and

Figure 6 is a schematic diagram of a light bulb.

Claims (10)

A photovoltaic element comprising: A substrate A semiconductor stack, wherein the semiconductor stack includes a first semiconductor layer, a light emitting layer is located on the first semiconductor layer, and a second semiconductor layer is located on the light emitting layer; An insulating layer including a portion directly contacting the first semiconductor layer and another portion directly contacting a top of the second semiconductor layer; A first metal layer on the second semiconductor layer; A second metal layer on the first semiconductor layer and directly contacting the first semiconductor layer; A third metal layer on the first metal layer and the second semiconductor layer; and A fourth metal layer directly contacting the second metal layer and located on the first semiconductor layer and the second semiconductor layer, The top of the third metal layer and the surface of the first semiconductor layer have a shortest distance d6, the top of the fourth metal layer and the surface of the first semiconductor layer have a shortest distance d5, and the difference between d6 and d5 is Less than 1 μm, and The third metal layer and the fourth metal layer directly contact the insulating layer. The photovoltaic element according to item 1 of the scope of patent application, wherein the projections of the third metal layer and the fourth metal layer perpendicular to a normal direction of the substrate have similar areas. The photovoltaic element according to item 1 of the scope of patent application, wherein the top of the first metal layer to the top of the second semiconductor layer has a height h3, and the top of the other part of the insulating layer to the second semiconductor The top of the layer has a height h4, and the height h3 is close to the height h4 or the difference between the height h3 and the height h4 is less than 1 μm. The photovoltaic element according to item 1 of the scope of patent application, wherein the second metal layer is formed between the first semiconductor layer and the fourth metal layer, and there is a gap between the second metal layer and the insulating layer. . The photovoltaic element according to item 1 of the scope of patent application, wherein the top of the second metal layer and the bottom of the first semiconductor layer have a height h1, and the top of the portion of the insulating layer and the first semiconductor layer The base has a height h2, and the difference between h1 and h2 is less than 1 μm. The photovoltaic element according to item 1 of the scope of patent application, wherein the first metal layer and the insulating layer have a gap. The photovoltaic element according to item 4 or item 6 of the patent application scope, wherein the pitch is less than 3 μm. The photovoltaic element according to item 1 of the scope of patent application, wherein the materials of the first semiconductor layer, the light emitting layer, and the second semiconductor layer include AlGaInP series and AlGaInN. Series such as Group III nitride or zinc oxide (ZnO) series. The photovoltaic element according to item 1 of the scope of patent application, wherein the material of the first metal layer, the second metal layer, the third metal layer, and the fourth metal layer may be selected from chromium (Cr), titanium (Ti ), Nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), tungsten (W), tin (Sn), or silver (Ag) and other metal materials. A light-emitting module includes the photovoltaic element according to item 1 of the patent application scope; and a carrier board; wherein the carrier board is electrically connected to the third metal layer and the fourth metal layer.