TW201941456A - Optoelectronic device and method for manufacturing the same - Google Patents
Optoelectronic device and method for manufacturing the same Download PDFInfo
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Description
本發明係關於一種光電元件,尤其是關於一種光電元件的電極設計。The invention relates to a photovoltaic element, in particular to an electrode design of a photovoltaic element.
發光二極體(light-emitting diode, LED)的發光原理是利用電子在n型半導體與p型半導體間移動的能量差,以光的形式將能量釋放,這樣的發光原理係有別於白熾燈發熱的發光原理,因此發光二極體被稱為冷光源。此外,發光二極體具有高耐久性、壽命長、輕巧、耗電量低等優點,因此現今的照明市場對於發光二極體寄予厚望,將其視為新一代的照明工具,已逐漸取代傳統光源,並且應用於各種領域,如交通號誌、背光模組、路燈照明、醫療設備等。The light emitting principle of a light-emitting diode (LED) is to use the energy difference between electrons moving between an n-type semiconductor and a p-type semiconductor to release energy in the form of light. Such a light-emitting principle is different from an incandescent lamp The light emitting principle of heat generation, so the light emitting diode is called a cold light source. In addition, light-emitting diodes have the advantages of high durability, long life, light weight, and low power consumption. Therefore, the current lighting market has high hopes for light-emitting diodes and regards them as a new generation of lighting tools. Light source, and is used in various fields, such as traffic signs, backlight modules, street lighting, medical equipment, etc.
第1A圖係習知之發光元件結構示意圖,如第1A圖所示,習知之發光元件100,包含有一透明基板10、一位於透明基板10上之半導體疊層12,以及至少一電極14位於上述半導體疊層12上,其中上述之半導體疊層12由上而下至少包含一第一導電型半導體層120、一活性層122,以及一第二導電型半導體層124。FIG. 1A is a schematic view of a conventional light-emitting element structure. As shown in FIG. 1A, the conventional light-emitting element 100 includes a transparent substrate 10, a semiconductor stack 12 on the transparent substrate 10, and at least one electrode 14 on the semiconductor. On the stack 12, the above-mentioned semiconductor stack 12 includes at least a first conductive type semiconductor layer 120, an active layer 122, and a second conductive type semiconductor layer 124 from top to bottom.
第1B圖係習知之發光元件電極結構示意圖,如第1B圖所示,習知之發光元件100’,包含有一透明基板10、一位於透明基板10上之半導體疊層12,以及至少一電極14位於上述半導體疊層12上,其中電極14可包含一反射電極141及一擴散阻障層142。但因為擴散阻障層142可能無法透光,而降低了發光元件100的出光效率。FIG. 1B is a schematic diagram of a conventional light-emitting element electrode structure. As shown in FIG. 1B, the conventional light-emitting element 100 ′ includes a transparent substrate 10, a semiconductor stack 12 on the transparent substrate 10, and at least one electrode 14 on On the semiconductor stack 12, the electrode 14 may include a reflective electrode 141 and a diffusion barrier layer 142. However, because the diffusion barrier layer 142 may be unable to transmit light, the light emitting efficiency of the light emitting device 100 is reduced.
此外,上述之發光元件100更可以進一步地與其他元件組合連接以形成一發光裝置(light-emitting apparatus)。第2圖為習知之發光裝置結構示意圖,如第2圖所示,一發光裝置200包含一具有至少一電路202之次載體(sub-mount)20;至少一焊料(solder)22位於上述次載體20上,藉由此焊料22將上述發光元件100黏結固定於次載體20上並使發光元件100之基板10與次載體20上之電路202形成電連接;以及,一電性連接結構24,以電性連接發光元件100之電極14與次載體20上之電路202;其中,上述之次載體20 可以是導線架(lead frame)或大尺寸鑲嵌基底(mounting substrate),以方便發光裝置200之電路規劃並提高其散熱效果。In addition, the above-mentioned light-emitting element 100 can be further combined with other elements to form a light-emitting apparatus. FIG. 2 is a schematic structural diagram of a conventional light emitting device. As shown in FIG. 2, a light emitting device 200 includes a sub-mount 20 having at least one circuit 202; at least one solder 22 is located on the sub-carrier. 20, the above-mentioned light-emitting element 100 is adhered and fixed on the sub-carrier 20 by the solder 22, and the substrate 10 of the light-emitting element 100 is electrically connected to the circuit 202 on the sub-carrier 20; and an electrical connection structure 24 The electrode 14 of the light-emitting element 100 is electrically connected to the circuit 202 on the sub-carrier 20. The above-mentioned sub-carrier 20 may be a lead frame or a large-sized mounting substrate to facilitate the circuit of the light-emitting device 200 Plan and improve its cooling effect.
一光電元件,包含:一半導體疊層,其中半導體疊層包含一第一半導體層,一發光層位於第一半導體層之上,及一第二半導體層位於發光層之上;一第一電極位於第二半導體層之上,其中第一電極更包含一反射層;以及一絕緣層形成於第二半導體層之上,且第一電極與絕緣層具有一間距。A photovoltaic element includes: a semiconductor stack, wherein the semiconductor stack includes a first semiconductor layer, a light emitting layer is located on the first semiconductor layer, and a second semiconductor layer is located on the light emitting layer; a first electrode is located on On the second semiconductor layer, the first electrode further includes a reflective layer; and an insulating layer is formed on the second semiconductor layer, and the first electrode and the insulating layer have a gap.
本發明揭示一種發光元件及其製造方法,為了使本發明之敘述更加詳盡與完備,請參照下列描述並配合第3A圖至第6圖之圖示。The present invention discloses a light emitting element and a manufacturing method thereof. In order to make the description of the present invention more detailed and complete, please refer to the following description and cooperate with the diagrams of FIGS. 3A to 6.
第3A圖至第3E圖為本發明實施例製造流程結構示意圖,如第3A圖所示,提供一基板30,接著形成一半導體磊晶疊層32於此基板30之上,其中半導體磊晶疊層32由下而上包含一第一導電型半導體層321、一活性層322,以及一第二導電型半導體層323。3A to 3E are schematic diagrams showing the manufacturing process structure according to an embodiment of the present invention. As shown in FIG. 3A, a substrate 30 is provided, and then a semiconductor epitaxial stack 32 is formed on the substrate 30. The semiconductor epitaxial stack The layer 32 includes a first conductive type semiconductor layer 321, an active layer 322, and a second conductive type semiconductor layer 323 from bottom to top.
接著,形成一絕緣層34於半導體磊晶疊層32之上,且與第一導電型半導體層321之第一表面3211及第二導電型半導體層323之第一表面3231直接接觸。之後,形成一圖案化光阻層36於絕緣層34之第一表面34S之上,並裸露出部分的絕緣層第一表面34S。Next, an insulating layer 34 is formed on the semiconductor epitaxial stack 32 and is in direct contact with the first surface 3211 of the first conductive type semiconductor layer 321 and the first surface 3231 of the second conductive type semiconductor layer 323. After that, a patterned photoresist layer 36 is formed on the first surface 34S of the insulating layer 34, and a part of the first surface 34S of the insulating layer is exposed.
如第3B圖所示,藉由上述圖案化光阻層36對絕緣層34進行一蝕刻製程,將部分的絕緣層34移除,且裸露出部分的第一導電型半導體層321之第一表面3211及第二導電型半導體層323之部分第一表面3231,以形成一第一絕緣層341於第一導電型半導體層321之部分第一表面3211之上,一第二絕緣層342於第二導電型半導體層323之部分第一表面3231之上,及一第三絕緣層343於第二導電型半導體層323之部分第一表面3231之上及第一導電型半導體層321之部分第一表面3211之上。As shown in FIG. 3B, an etching process is performed on the insulating layer 34 by using the patterned photoresist layer 36, a part of the insulating layer 34 is removed, and a part of the first surface of the first conductive semiconductor layer 321 is exposed. 3211 and a portion of the first surface 3231 of the second conductive type semiconductor layer 323 to form a first insulating layer 341 on a portion of the first surface 3211 of the first conductive type semiconductor layer 321 and a second insulating layer 342 on the second A portion of the first surface 3231 of the conductive semiconductor layer 323 and a third insulating layer 343 on a portion of the first surface 3231 of the second conductive semiconductor layer 323 and a portion of the first surface of the first conductive semiconductor layer 321 Above 3211.
在一實施例中,可藉由圖案化光阻層36對絕緣層34進行一側蝕刻製程,使得部分位於圖案化光阻層36之下的絕緣層34也被蝕刻,亦即使部分上述第一絕緣層341及第二絕緣層342相對於圖案化光阻層36具有一底切(undercut)形狀。圖案化光阻層36因此於投影於半導體磊晶疊層32表面之邊緣會與第一絕緣層341及第二絕緣層342投影於半導體磊晶疊層32表面之邊緣具有一間距G。在一實施例中,上述間距G可小於3μm。在一實施例中,上述側蝕刻可為一濕式蝕刻。In one embodiment, the insulating layer 34 can be etched on one side by the patterned photoresist layer 36, so that part of the insulating layer 34 below the patterned photoresist layer 36 is also etched, even if part of the first The insulating layer 341 and the second insulating layer 342 have an undercut shape with respect to the patterned photoresist layer 36. Therefore, the edge of the patterned photoresist layer 36 projected on the surface of the semiconductor epitaxial stack 32 will have a gap G from the edge of the first insulating layer 341 and the second insulating layer 342 projected on the surface of the semiconductor epitaxial stack 32. In one embodiment, the pitch G may be less than 3 μm. In one embodiment, the above-mentioned side etching may be a wet etching.
接著,如第3C圖所示,以物理氣相沉積同時形成一第一金屬層382、一第二金屬層381及一暫時金屬層383。其中第一金屬層382形成於第二導電型半導體層323裸露出之部分第一表面3231之上;第二金屬層381形成於第一導電型半導體層321裸露出之部分第一表面3211之上;及暫時金屬層383形成於圖案化光阻層36之上,並覆蓋圖案化光阻層36 之上表面。在一實施例中,上述物理氣相沉積可為真空蒸鍍(Vacuum Evaporation)、濺鍍(Sputtering)、電子束蒸鍍(Electron Beam Evaporation)或離子鍍(Ion Plating)。Next, as shown in FIG. 3C, a first metal layer 382, a second metal layer 381, and a temporary metal layer 383 are simultaneously formed by physical vapor deposition. The first metal layer 382 is formed on a portion of the first surface 3231 where the second conductive type semiconductor layer 323 is exposed. The second metal layer 381 is formed on the portion of the first surface 3211 where the first conductive type semiconductor layer 321 is exposed. ; And the temporary metal layer 383 is formed on the patterned photoresist layer 36 and covers the upper surface of the patterned photoresist layer 36. In one embodiment, the physical vapor deposition may be vacuum evaporation, sputtering, electron beam evaporation, or ion plating.
在一實施例中,因為圖案化光阻層36具有一底切(undercut)形狀,因此第一金屬層382之側壁不會與上述第三絕緣層343及第二絕緣層342 之側壁直接接觸,且第二金屬層381之側壁不會與上述第一絕緣層341及第三絕緣層343之側壁直接接觸。In one embodiment, because the patterned photoresist layer 36 has an undercut shape, the sidewall of the first metal layer 382 does not directly contact the sidewalls of the third insulating layer 343 and the second insulating layer 342. In addition, the sidewall of the second metal layer 381 does not directly contact the sidewalls of the first insulating layer 341 and the third insulating layer 343.
在一實施例中,第一金屬層382可為一複數疊層,且可包含一反射層,此反射層之材料可選自反射率大於90%的材料。在一實施例中第一金屬層中之反射層之材料可選自鉻(Cr)、鈦(Ti)、鎳(Ni)、鉑(Pt)、銅(Cu)、金(Au)、鋁(Al)、鎢(W)、錫(Sn)、或銀(Ag)等金屬材料。In one embodiment, the first metal layer 382 may be a plurality of stacked layers and may include a reflective layer. The material of the reflective layer may be selected from materials with a reflectance greater than 90%. In an embodiment, the material of the reflective layer in the first metal layer may be selected from chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), hafnium (Au), aluminum ( Al), tungsten (W), tin (Sn), or silver (Ag) is a metal material.
接著,如第3D圖所示,移除圖案化光阻層36及其上之暫時金屬層383。在一實施例中,如第3D圖所示,第二金屬層381至第一導電型半導體層321之第一表面3211可具有一高度h1,而第一絕緣層341至第一導電型半導體層321之第一表面3211可具有一高度h2,藉由本發明之上述製程,第二金屬層381與第一絕緣層341可具有相近之高度或第二金屬層381與第一絕緣層341之高度差異小於1μm。在一實施例中,第二金屬層381與第一絕緣層341可具有一間距d1,且此間距d1小於3μm,及/或第二金屬層381與第三絕緣層343可具有一間距d2,且此間距d2小於3μm。在一實施例中,d1與d2可具有相同值。Next, as shown in FIG. 3D, the patterned photoresist layer 36 and the temporary metal layer 383 thereon are removed. In an embodiment, as shown in FIG. 3D, the first surface 3211 of the second metal layer 381 to the first conductive type semiconductor layer 321 may have a height h1, and the first insulating layer 341 to the first conductive type semiconductor layer The first surface 3211 of 321 may have a height h2. Through the above process of the present invention, the second metal layer 381 and the first insulating layer 341 may have similar heights or the height difference between the second metal layer 381 and the first insulating layer 341. Less than 1 μm. In one embodiment, the second metal layer 381 and the first insulation layer 341 may have a distance d1, and the distance d1 is less than 3 μm, and / or the second metal layer 381 and the third insulation layer 343 may have a distance d2, And this distance d2 is less than 3 μm. In an embodiment, d1 and d2 may have the same value.
在另一實施例中,第一金屬層382至第二導電型半導體層323之第一表面3231可具有一高度h3,而第二絕緣層342至第二導電型半導體層323之第一表面3231可具有一高度h4,藉由上述實施例揭露之製程,第一金屬層382與第二絕緣層342可具有相近之高度或第一金屬層382與第二絕緣層342之高度差異小於1μm。在一實施例中,第一金屬層382與第二絕緣層342可具有一間距d3,且此間距d3小於3μm,及/或第一金屬層382與第三絕緣層343可具有一間距d4,且此間距d4小於3μm。在一實施例中,d3與d4可具有相同值。在另一實施例中,d1、d2、d3與d4可具有相同值。In another embodiment, the first surface 3231 of the first metal layer 382 to the second conductive type semiconductor layer 323 may have a height h3, and the second insulating layer 342 to the first surface 3231 of the second conductive type semiconductor layer 323 It may have a height h4. According to the process disclosed in the above embodiment, the first metal layer 382 and the second insulating layer 342 may have similar heights or the height difference between the first metal layer 382 and the second insulating layer 342 is less than 1 μm. In an embodiment, the first metal layer 382 and the second insulation layer 342 may have a distance d3, and the distance d3 is less than 3 μm, and / or the first metal layer 382 and the third insulation layer 343 may have a distance d4, And this distance d4 is less than 3 μm. In an embodiment, d3 and d4 may have the same value. In another embodiment, d1, d2, d3, and d4 may have the same value.
最後,如第3E圖所示,形成一第三金屬層42於第一金屬層382之上,及形成一第四金屬層40於第二金屬層381之上以完成本發明之光電元件300。在一實施例中,部分第四金屬層40與第一導電型半導體層321之第一表面3211直接接觸,或部分第三金屬層42與第二導電型半導體層323之第一表面3231直接接觸。在一實施例中,上述第三金屬層42下方幾乎不存在第二絕緣層342。在另一實例中,第三金屬層42之頂部與第一半導體層321之第二表面3212具有一最短距離d6,及第四金屬層40之頂部與第一半導體層321之第二表面3212具有一最短距離d5,且d6與d5之差異小於1μm。在一實施例中,上述第三金屬層42及第四金屬層40於垂直基板30法線方向之投影可具有相近之面積。Finally, as shown in FIG. 3E, a third metal layer 42 is formed on the first metal layer 382, and a fourth metal layer 40 is formed on the second metal layer 381 to complete the photovoltaic device 300 of the present invention. In one embodiment, part of the fourth metal layer 40 is in direct contact with the first surface 3211 of the first conductive type semiconductor layer 321, or part of the third metal layer 42 is in direct contact with the first surface 3231 of the second conductive type semiconductor layer 323. . In one embodiment, there is almost no second insulating layer 342 under the third metal layer 42. In another example, the top of the third metal layer 42 and the second surface 3212 of the first semiconductor layer 321 have a shortest distance d6, and the top of the fourth metal layer 40 and the second surface 3212 of the first semiconductor layer 321 have a shortest distance d6. A shortest distance d5, and the difference between d6 and d5 is less than 1 μm. In an embodiment, the projections of the third metal layer 42 and the fourth metal layer 40 in the normal direction of the vertical substrate 30 may have similar areas.
在一實施例中,接續上述第3D圖或第3E圖之後,基板30可被移除並裸露出第一導電型半導體層321之部分第二表面3212以形成一薄膜式覆晶(thin-film flip chip)。在一實施例中,接續上述第3D圖或第3E圖之後,藉由第一金屬層382及第二金屬層381或第三金屬層42及第四金屬層40可將本發明之光電元件300連接至一載板(圖未示)以形成一覆晶封裝(flip chip package)。在一實施例中第一金屬層382、第二金屬層381、第三金屬層42或第四金屬層40之材料包含但不限於銅(Cu)、鋁(Al)、銦(In)、錫(Sn)、金(Au)、鉑(Pt)、鋅(Zn)、銀(Ag)、鈦(Ti)、鎳(Ni)、鉛(Pb)、鈀(Pd)、鍺(Ge)、鉻(Cr)、鎘(Cd)、鈷(Co)、錳(Mn)、銻(Sb)、鉍(Bi)、鎵(Ga)、鉈(Tl)、釙(Po)、銥(Ir)、錸(Re)、銠(Rh)、鋨(Os)、鎢(W)、鋰(Li)、鈉(Na)、鉀(K)、鈹(Be)、鎂(Mg)、鈣(Ca)、鍶(Sr)、鋇(Ba)、鋯(Zr)、鉬(Mo)、鈉(La)、銀-鈦(Ag-Ti)、銅-錫(Cu-Sn)、銅-鋅(Cu-Zn)、銅-鎘(Cu-Cd)、錫-鉛-銻(Sn-Pb-Sb)、錫-鉛-鋅(Sn-Pb-Zn)、鎳-錫(Ni-Sn)、鎳-鈷(Ni-Co)、金合金(Au alloy)、或鍺-金-鎳(Ge-Au-Ni)等金屬材料。In one embodiment, after the above 3D or 3E drawings, the substrate 30 may be removed and a portion of the second surface 3212 of the first conductive semiconductor layer 321 may be exposed to form a thin-film flip-chip. flip chip). In an embodiment, following the above-mentioned 3D or 3E drawings, the photovoltaic device 300 of the present invention may be formed by the first metal layer 382 and the second metal layer 381 or the third metal layer 42 and the fourth metal layer 40. Connected to a carrier board (not shown) to form a flip chip package. In one embodiment, the material of the first metal layer 382, the second metal layer 381, the third metal layer 42 or the fourth metal layer 40 includes, but is not limited to, copper (Cu), aluminum (Al), indium (In), and tin. (Sn), gold (Au), platinum (Pt), zinc (Zn), silver (Ag), titanium (Ti), nickel (Ni), lead (Pb), palladium (Pd), germanium (Ge), chromium (Cr), cadmium (Cd), cobalt (Co), manganese (Mn), antimony (Sb), bismuth (Bi), gallium (Ga), thorium (Tl), thorium (Po), iridium (Ir), thorium (Re), rhodium (Rh), thorium (Os), tungsten (W), lithium (Li), sodium (Na), potassium (K), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zirconium (Zr), molybdenum (Mo), sodium (La), silver-titanium (Ag-Ti), copper-tin (Cu-Sn), copper-zinc (Cu-Zn) , Copper-cadmium (Cu-Cd), tin-lead-antimony (Sn-Pb-Sb), tin-lead-zinc (Sn-Pb-Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni -Co), Au alloy, or germanium-gold-nickel (Ge-Au-Ni).
第4A圖至第4C圖係繪示出一發光模組示意圖,第4A圖係顯示一發光模組外部透視圖,一發光模組500可包含一載體502,複數個透鏡504、506、508及510,及兩電源供應終端512及514。4A to 4C are schematic diagrams of a light emitting module, and FIG. 4A is a perspective view of an external light emitting module. A light emitting module 500 may include a carrier 502, a plurality of lenses 504, 506, 508, and 510, and two power supply terminals 512 and 514.
第4B-4C圖係顯示一發光模組剖面圖,其中第4C圖係第4B圖之E區的放大圖。載體502可包含一上載體503及下載體501,其中下載體501之一表面可與上載體503接觸。透鏡504及508形成在上載體503之上。上載體503可形成至少一通孔515,而依本發明實施例形成之發光二極體元件300可形成在上述通孔515中並與下載體501接觸,且被膠材521包圍。膠材521之上具有一透鏡508。Figures 4B-4C are cross-sectional views of a light-emitting module, and Figure 4C is an enlarged view of area E in Figure 4B. The carrier 502 may include an upper carrier 503 and a download body 501, wherein a surface of the download body 501 may be in contact with the upper carrier 503. The lenses 504 and 508 are formed on the upper carrier 503. The upper carrier 503 may form at least one through-hole 515, and the light-emitting diode element 300 formed according to the embodiment of the present invention may be formed in the above-mentioned through-hole 515 and contact the download body 501, and is surrounded by the adhesive material 521. A lens 508 is provided on the adhesive 521.
如第4C圖所示,在一實施例中,通孔515之兩側壁之上可形成一反射層519以增加出光效率;下載體501之下表面可形成一金屬層517以增進散熱效率。As shown in FIG. 4C, in one embodiment, a reflective layer 519 may be formed on both sidewalls of the through hole 515 to increase light extraction efficiency; a metal layer 517 may be formed on the lower surface of the download body 501 to improve heat dissipation efficiency.
第5A-5B圖係繪示出一光源產生裝置示意圖600,一光源產生裝置600可包含一發光模組500、一外殼540、一電源供應系統(未顯示)以供應光源產生裝置600一電流、以及一控制元件(未顯示),用以控制電源供應系統(未顯示)。光源產生裝置600可以是一照明裝置,例如路燈、車燈或室內照明光源,也可以是交通號誌或一平面顯示器中背光模組的一背光光源。5A-5B are schematic diagrams 600 of a light source generating device. A light source generating device 600 may include a light emitting module 500, a housing 540, and a power supply system (not shown) to supply the light source generating device 600 with a current, And a control element (not shown) for controlling the power supply system (not shown). The light source generating device 600 may be a lighting device, such as a street light, a car light or an indoor lighting light source, or a traffic light or a backlight light source of a backlight module in a flat panel display.
第6圖係繪示一燈泡示意圖。燈泡700包括一個外殼921,一透鏡922,一照明模組924,一支架925,一散熱器926,一串接部927及一電串接器928。其中照明模組924係包括一載體923,並在載體923上包含至少一個上述實施例中的發光二極體元件300。Figure 6 is a schematic diagram of a light bulb. The bulb 700 includes a housing 921, a lens 922, a lighting module 924, a bracket 925, a heat sink 926, a series connection portion 927, and an electrical series connector 928. The lighting module 924 includes a carrier 923, and the carrier 923 includes at least one light-emitting diode element 300 in the above embodiment.
具體而言,光電元件300係包含發光二極體(LED)、光電二極體(photodiode)、光敏電阻(photoresistor)、雷射(laser)、紅外線發射體(infrared emitter)、有機發光二極體(organic light-emitting diode)及太陽能電池(solar cell)中至少其一。基板30係為一成長及/或承載基礎。候選材料可包含導電基板或不導電基板、透光基板或不透光基板。其中導電基板材料其一可為鍺(Ge)、砷化鎵(GaAs)、銦化磷(InP)、碳化矽(SiC)、矽(Si)、鋁酸鋰(LiAlO2 )、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)、金屬。透光基板材料其一可為藍寶石(Sapphire)、鋁酸鋰(LiAlO2)、氧化鋅(ZnO)、氮化鎵(GaN)、玻璃、鑽石、CVD鑽石、與類鑽碳(Diamond-Like Carbon;DLC)、尖晶石(spinel, MgAl2 O4 )、氧化鋁(Al2 O3 )、氧化矽(SiOX ) 及鎵酸鋰(LiGaO2 )。Specifically, the photovoltaic element 300 series includes a light emitting diode (LED), a photodiode, a photoresistor, a laser, an infrared emitter, and an organic light emitting diode. (Organic light-emitting diode) and solar cell (solar cell). The substrate 30 is a growth and / or carrying foundation. The candidate material may include a conductive substrate or a non-conductive substrate, a light-transmitting substrate, or a light-opaque substrate. One of the conductive substrate materials may be germanium (Ge), gallium arsenide (GaAs), indium phosphorus (InP), silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO 2 ), zinc oxide (ZnO ), Gallium nitride (GaN), aluminum nitride (AlN), metal. One of the light-transmitting substrate materials may be sapphire, lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, and diamond-like carbon (Diamond-Like Carbon; DLC), spinel (MgAl 2 O 4 ), aluminum oxide (Al 2 O 3 ), silicon oxide (SiO X ), and lithium gallate (LiGaO 2 ).
上述第一導電型半導體層321與第二導電型半導體層323係電性、極性或摻雜物相異,分別用以提供電子與電洞之半導體材料單層或多層結構(「多層」係指二層或二層以上,以下同。)其電性選擇可以為p型、n型、及i型中至少任意二者之組合。活性層322係位於上述二個部分之電性、極性或摻雜物相異、或者係分別用以提供電子與電洞之半導體材料之間,為電能與光能可能發生轉換或被誘發轉換之區域。電能轉變或誘發光能者係如發光二極體、液晶顯示器、有機發光二極體;光能轉變或誘發電能者係如太陽能電池、光電二極體。上述半導體磊晶疊層32其材料包含一種或一種以上之元素選自鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)以及矽(Si)所構成群組。常用之材料係如磷化鋁鎵銦(AlGaInP)系列、氮化鋁鎵銦(AlGaInN)系列等III族氮化物、氧化鋅(ZnO)系列等。活性層322之結構係如:單異質結構(single heterostructure;SH)、雙異質結構(double heterostructure;DH)、雙側雙異質結構(double-side double heterostructure;DDH)、或多層量子井(multi-quantum well;MQW)結構。當光電元件300為一發光二極體,其發光頻譜可以藉由改變半導體單層或多層之物理或化學要素進行調整。再者,調整量子井之對數亦可以改變發光波長。The above-mentioned first conductive type semiconductor layer 321 and the second conductive type semiconductor layer 323 are electrically, polar, or dopant-different semiconductor materials that are used to provide electrons and holes, respectively, in a single-layer or multilayer structure ("multilayer" means Two or more layers, the same below.) The electrical selection can be a combination of at least any two of p-type, n-type, and i-type. The active layer 322 is located between the above two parts with different electrical properties, polarities or dopants, or between semiconductor materials used to provide electrons and holes, respectively. It is possible that electrical energy and light energy may be converted or induced conversion. region. Those who convert or induce light energy such as light-emitting diodes, liquid crystal displays, and organic light-emitting diodes; those who convert or induce light energy such as solar cells, photovoltaic diodes. The material of the semiconductor epitaxial stack 32 includes one or more elements selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), and silicon ( Si). Commonly used materials are group III nitrides such as aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, and zinc oxide (ZnO) series. The structure of the active layer 322 is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multilayer quantum well (multi- quantum well (MQW) structure. When the photovoltaic element 300 is a light emitting diode, its light emission spectrum can be adjusted by changing the physical or chemical elements of the semiconductor single layer or multiple layers. Furthermore, adjusting the logarithm of the quantum well can also change the emission wavelength.
於本發明之一實施例中,半導體磊晶疊層32與基板30間尚可選擇性地包含一緩衝層(buffer layer,未顯示)。此緩衝層係介於二種材料系統之間,使基板之材料系統”過渡”至半導體系統之材料系統。對發光二極體之結構而言,一方面,緩衝層係用以降低二種材料間晶格不匹配之材料層。另一方面,緩衝層亦可以是用以結合二種材料或二個分離結構之單層、多層或結構,其可選用之材料係如:有機材料、無機材料、金屬、及半導體等;其可選用之結構係如:反射層、導熱層、導電層、歐姆接觸(ohmic contact)層、抗形變層、應力釋放(stress release)層、應力調整(stress adjustment)層、接合(bonding)層、波長轉換層、及機械固定構造等。In one embodiment of the present invention, the semiconductor epitaxial stack 32 and the substrate 30 may optionally include a buffer layer (not shown). This buffer layer is between the two metal material systems, which "transitions" the material system of the substrate to the material system of the semiconductor system. As for the structure of the light emitting diode, on the one hand, the buffer layer is a material layer for matching the lattice between the two materials. On the other hand, the buffer layer can also be a single layer, multiple layers, or structure that is used to combine two types of materials or two separate structures. The materials that can be used include organic materials, inorganic materials, metals, and semiconductors. Selected structures are: reflective layer, thermally conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment layer, bonding layer, wavelength Conversion layer and mechanical fixing structure.
半導體磊晶疊層32上更可選擇性地形成一接觸層(未顯示)。接觸層係設置於半導體磊晶疊層32遠離基板30之一側。具體而言,接觸層可以為光學層、電學層、或其二者之組合。光學層係可以改變來自於或進入活性層的電磁輻射或光線。在此所稱之「改變」係指改變電磁輻射或光之至少一種光學特性,前述特性係包含但不限於頻率、波長、強度、通量、效率、色溫、演色性(rendering index)、光場(light field)、及可視角(angle of view)。電學層係可以使得接觸層之任一組相對側間之電壓、電阻、電流、電容中至少其一之數值、密度、分布發生變化或有發生變化之趨勢。接觸層之構成材料係包含氧化物、導電氧化物、透明氧化物、具有50%或以上穿透率之氧化物、金屬、相對透光金屬、具有50%或以上穿透率之金屬、有機質、無機質、螢光物、磷光物、陶瓷、半導體、摻雜之半導體、及無摻雜之半導體中至少其一。於某些應用中,接觸層之材料係為氧化銦錫、氧化鎘錫、氧化銻錫、氧化銦鋅、氧化鋅鋁、與氧化鋅錫中至少其一。若為相對透光金屬,其厚度較佳地約為0.005μm~0.6μm。在一實施例中,由於接觸層具有較佳的橫向電流擴散速率,可以用以協助電流均勻擴散到半導體磊晶疊層32之中。一般而言,根據接觸層摻混的雜質與製程的方式不同而有所變動,其能隙的寬度可介於0.5eV至5eV之間。A contact layer (not shown) may be selectively formed on the semiconductor epitaxial stack 32. The contact layer is disposed on one side of the semiconductor epitaxial stack 32 and the substrate 30. Specifically, the contact layer may be an optical layer, an electrical layer, or a combination thereof. The optical layer system can change the electromagnetic radiation or light emitted from or into the active layer. As used herein, "change" refers to changing at least one optical characteristic of electromagnetic radiation or light. The aforementioned characteristics include, but are not limited to, frequency, wavelength, intensity, general efficiency, efficiency, color temperature, rendering index, and light field. (Light field), and angle of view. The electrical layer can make the voltage, resistance, voltage, and capacitance of at least one of the opposite sides of the contact layer change, the density, the distribution, or the tendency to change. The constituent materials of the contact layer include oxides, conductive oxides, transparent oxides, oxides with 50% or more penetrations, metal, relatively translucent metals, metals with 50% or more transmission, organic matter, At least one of an inorganic substance, a phosphor, a phosphor, a ceramic, a semiconductor, a doped semiconductor, and an undoped semiconductor. In some applications, the material of the contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. Rhenium is a relatively light-transmitting genus, and its thickness is preferably about 0.005 μm to 0.6 μm. In one embodiment, since the contact layer has a better lateral current diffusion rate, it can be used to help the current to evenly diffuse into the semiconductor epitaxial stack 32. Generally speaking, it varies according to the impurities mixed in the contact layer and the method of the process, and the width of the energy gap can be between 0.5eV and 5eV.
以上各圖式與說明雖僅分別對應特定實施例,然而,各個實施例中所說明或揭露之元件、實施方式、設計準則、及技術原理除在彼此顯相衝突、矛盾、或難以共同實施之外,吾人當可依其所需任意參照、交換、搭配、協調、或合併。雖然本發明已說明如上,然其並非用以限制本發明之範圍、實施順序、或使用之材料與製程方法。對於本發明所作之各種修飾與變更,皆不脫本發明之精神與範圍。Although the above drawings and descriptions only correspond to specific embodiments, however, the elements, implementations, design guidelines, and technical principles described or disclosed in each embodiment are inconsistent, contradictory, or difficult to implement together. In addition, we shall be free to refer, exchange, match, coordinate, or merge as needed. Although the present invention has been described as above, it is not intended to limit the scope, implementation order, or materials and manufacturing methods of the present invention. Various modifications and changes made without departing from the spirit and scope of the invention.
100,100’‧‧‧發光元件100,100’‧‧‧‧Light-emitting element
200‧‧‧發光裝置200‧‧‧light-emitting device
202‧‧‧電路202‧‧‧Circuit
20‧‧‧次載體(sub-mount)20‧‧‧ sub-mount
22‧‧‧焊料(solder)22‧‧‧solder
24‧‧‧電性連接結構24‧‧‧ Electrical connection structure
10‧‧‧透明基板10‧‧‧ transparent substrate
12‧‧‧半導體疊層12‧‧‧ semiconductor stack
14‧‧‧電極14‧‧‧ electrode
141‧‧‧反射電極141‧‧‧Reflective electrode
142‧‧‧擴散阻障層142‧‧‧ Diffusion barrier
120,321‧‧‧第一導電型半導體層120,321‧‧‧first conductive semiconductor layer
122,322‧‧‧活性層122, 322‧‧‧active layer
124,323‧‧‧第二導電型半導體層124,323‧‧‧Second Conductive Semiconductor Layer
300‧‧‧發光二極體元件300‧‧‧ Light Emitting Diode Element
30‧‧‧基板30‧‧‧ substrate
32‧‧‧半導體磊晶疊層32‧‧‧Semiconductor Epitaxial Stack
34‧‧‧絕緣層34‧‧‧ Insulation
341‧‧‧第一絕緣層341‧‧‧First insulation layer
342‧‧‧第二絕緣層342‧‧‧Second insulation layer
343‧‧‧第三絕緣層343‧‧‧third insulating layer
3211‧‧‧第一導電型半導體層之第一表面3211‧‧‧First surface of first conductive semiconductor layer
3231‧‧‧第二導電型半導體層之第一表面3231‧‧‧ the first surface of the second conductive semiconductor layer
36‧‧‧圖案化光阻層36‧‧‧patterned photoresist layer
34S‧‧‧第一表面34S‧‧‧First surface
G‧‧‧間距G‧‧‧Pitch
382‧‧‧第一金屬層382‧‧‧first metal layer
381‧‧‧第二金屬層381‧‧‧Second metal layer
383‧‧‧暫時金屬層383‧‧‧Temporary metal layer
42‧‧‧第三金屬層42‧‧‧ third metal layer
40‧‧‧第四金屬層40‧‧‧ Fourth metal layer
500‧‧‧發光模組500‧‧‧light emitting module
502‧‧‧載體502‧‧‧ carrier
504、506、508、510‧‧‧透鏡504, 506, 508, 510‧‧‧ lens
512、514‧‧‧電源供應終端512, 514‧‧‧ Power Supply Terminal
503‧‧‧上載體503‧‧‧ on carrier
501‧‧‧下載體501‧‧‧ download
515‧‧‧通孔515‧‧‧through hole
517‧‧‧金屬層517‧‧‧metal layer
519‧‧‧反射層519‧‧‧Reflective layer
600‧‧‧光源產生裝置示意圖600‧‧‧ Light source generating device
700‧‧‧燈泡700‧‧‧ bulb
921‧‧‧外殼921‧‧‧Shell
922‧‧‧透鏡922‧‧‧ lens
923‧‧‧載體923‧‧‧ carrier
924‧‧‧照明模組924‧‧‧lighting module
925‧‧‧支架925‧‧‧ bracket
926‧‧‧散熱器926‧‧‧ Radiator
927‧‧‧串接部927‧‧‧Concatenation Department
928‧‧‧電串接器928‧‧‧Electric connector
第1A-1B圖為一結構圖,顯示一習知陣列發光二極體元件側視結構圖;Figures 1A-1B are structural diagrams showing a side view structural diagram of a conventional array light emitting diode element;
第2圖為一示意圖,顯示一習知發光裝置結構示意圖;FIG. 2 is a schematic diagram showing the structure of a conventional light emitting device;
第3A-3E圖為本發明實施例製造流程結構示意圖;3A-3E are schematic structural diagrams of a manufacturing process according to an embodiment of the present invention;
第4A圖至第4C圖係繪示出一發光模組示意圖;4A to 4C are schematic diagrams of a light emitting module;
第5A-5B圖係繪示出一光源產生裝置示意圖;及5A-5B are schematic diagrams of a light source generating device; and
第6圖係繪示一燈泡示意圖。Figure 6 is a schematic diagram of a light bulb.
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