TWI619264B - Optoelectronic device and method for manufacturing the same - Google Patents

Abstract

A method of fabricating a photovoltaic element, comprising the steps of: providing a growth substrate; forming a transition layer over the growth substrate; forming a semiconductor layer over the transition layer; and performing a first etch on the semiconductor stack and the transition layer Forming at least one trench, wherein the trench divides the semiconductor stack and the transition layer into a plurality of semiconductor islands and a plurality of transition layer islands, and exposes a portion of the grown substrate; providing a carrier substrate to connect the semiconductor islands; and performing a second etching To remove the growth substrate.

Description

Photoelectric element and method of manufacturing same

The present invention relates to a photovoltaic element, and more particularly to a method of substrate replacement of a photovoltaic element.

The principle of light-emitting diode (LED) is to use energy difference between the n-type semiconductor and the p-type semiconductor to release energy in the form of light. This principle of illumination is different from incandescent lamps. The principle of heat generation, so the light-emitting diode is called a cold light source. In addition, the light-emitting diode has the advantages of high durability, long life, light weight, low power consumption, etc., so the current lighting market has high hopes for the light-emitting diode, and it is gradually replaced as a new generation of lighting tools. Light source, and is used in various fields, such as traffic signs, backlight modules, street lighting, medical equipment, etc.

1 is a schematic view showing the structure of a conventional light-emitting element. As shown in FIG. 1, a conventional light-emitting element 100 includes a transparent substrate 10, a semiconductor laminate 12 on a transparent substrate 10, and at least one electrode 14 located in the semiconductor. On the stack 12, the semiconductor stack 12 includes at least a first conductive semiconductor layer 120, an active layer 122, and a second conductive semiconductor layer 124 from top to bottom.

In addition, the above-described light-emitting element 100 can be further combined with other elements to form a light-emitting apparatus. 2 is a schematic view showing the structure of a conventional light-emitting device. As shown in FIG. 2, a light-emitting device 200 includes a sub-mount 20 having at least one circuit 202; at least one solder 22 is located in the above-mentioned sub-carrier 20, the light-emitting element 100 is bonded and fixed to the secondary carrier 20 by the solder 22, and the substrate 10 of the light-emitting element 100 is electrically connected to the circuit 202 on the secondary carrier 20; and an electrical connection structure 24 is Electrically connecting the electrode 14 of the light-emitting element 100 with the circuit 202 on the secondary carrier 20; wherein, the second load The body 20 can be a lead frame or a large-sized mounting substrate to facilitate circuit planning of the light-emitting device 200 and improve its heat dissipation effect.

However, as shown in FIG. 1, in the conventional light-emitting element 100, since the surface of the transparent substrate 10 is a flat surface, and the refractive index of the transparent substrate 10 is different from the refractive index of the external environment, the active layer 122 is emitted. When the light A enters the external environment from the substrate, total internal reflection (TIR) is easily formed, and the light extraction efficiency of the light-emitting element 100 is lowered.

A method of fabricating a photovoltaic element, comprising the steps of: providing a growth substrate; forming a buffer layer over the growth substrate, wherein the buffer layer completely covers the growth substrate; forming a semiconductor layer over the buffer layer; And the buffer layer performs a first etching to form at least one trench, wherein the trench divides the semiconductor stack and the transition layer into a plurality of semiconductor islands and a plurality of transition layer islands, and exposes a portion of the growth substrate; and provides a carrier substrate to connect the semiconductors Island; and performing a second etch to remove the grown substrate.

1 is a structural view showing a side view of a conventional light-emitting diode element; FIG. 2 is a schematic view showing a structure of a conventional light-emitting device; and FIG. 3A-3J is a manufacturing process of an embodiment of the present invention; Figure 4 is a schematic view showing a top view of the design of the present invention; Figures 5A to 5C are schematic views showing a light-emitting module; and Figures 6A-6B are a schematic view showing a light source generating device; Figure 7 shows a schematic diagram of a light bulb.

The present invention discloses a light-emitting element and a method of manufacturing the same. In order to make the description of the present invention more detailed and complete, please refer to the following description and cooperate with the drawings of FIGS. 3A to 7.

3A to 3J are schematic diagrams showing the structure of a manufacturing process according to an embodiment of the present invention, such as As shown in FIG. 3A, a substrate 30 is provided and a transition layer 32 is formed over the substrate 30, followed by a semiconductor epitaxial layer 34 on the transition layer 32, wherein the semiconductor epitaxial layer 34 includes a first A conductive semiconductor layer 341, an active layer 342, and a second conductive semiconductor layer 343.

The substrate 30 is a growth and/or carrier foundation. The candidate material may comprise a conductive substrate or a non-conductive substrate, a light transmissive substrate or an opaque substrate. One of the conductive substrate materials may be germanium (Ge), gallium arsenide (GaAs), indium phosphate (InP), tantalum carbide (SiC), germanium (Si), lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO). ), gallium nitride (GaN), aluminum nitride (AlN), metal. One of the transparent substrate materials may be sapphire, lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, and diamond-like carbon (Diamond-Like Carbon). ; DLC), spinel (MgAl ₂ O ₄ ), yttrium oxide (SiO _X ), and lithium gallate (LiGaO ₂ ). The material of the transition layer 32 may be selected from the group consisting of tantalum oxides or tantalum nitrides.

The material of the first semiconductor layer 341, the active layer 342, and the second semiconductor layer 343 may include one or more elements selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), and phosphorus ( A group consisting of P), nitrogen (N), and bismuth (Si). Commonly used materials are such as Group III nitrides such as aluminum gallium indium phosphide (AlGaInP) series and aluminum gallium indium nitride (AlGaInN) series, and zinc oxide (ZnO) series.

As shown in FIGS. 3B-3C, the first electrode 36 is formed over the first surface 34T of the semiconductor epitaxial stack 34. Next, a first connection layer 38 is formed over the first metal layer 36 and the semiconductor epitaxial laminate 34. In one embodiment, the first tie layer 38 is in direct contact with the first surface 34T of the portion of the semiconductor epitaxial stack 34.

Next, as shown in FIG. 3D, the semiconductor laminate 34 and the first connection layer 38 are first etched to form at least one trench T, wherein the trench T separates the semiconductor laminate 34 and the first connection layer 38 into a plurality of trenches T. The semiconductor island 34i and the plurality of first connection layer islands 38i. In one embodiment, each semiconductor island 34i has a first metal layer 36 on its upper surface.

Next, as shown in FIG. 3E, the first etching is continued from the trench T to the transition layer 32 to form at least one transition layer island 32i under each semiconductor island 34i, and a portion of the substrate 30 is exposed. In one embodiment, since the first etch has a higher etching efficiency to the transition layer 32 than the semiconductor layer 34, both edges of the transition layer island 32i may have an undercut U shape with respect to both edges of the semiconductor island 34i. . In an embodiment, the first The etching may be a chemical etching, and the etching solution may be selected from Hydrofluoric Acid (HF), Buffer Oxide Etcher (BOE) or Surfactanated Buffered Oxide Etchants (SBOE). . In one embodiment, the first etching time may be 20-50 minutes, and the etching solution concentration may be 30-60%.

Thereafter, as shown in FIGS. 3F to 3G, a carrier substrate 40 is provided, and a second connection layer 42 is formed on the carrier substrate 40. Next, a connection process is performed by the second connection layer 42 and the plurality of first connection layer islands 38i to connect the plurality of semiconductor islands 34i to the carrier substrate 40.

The candidate material of the carrier substrate 40 may include a conductive substrate or a non-conductive substrate, a light-transmitting substrate, or an opaque substrate. One of the conductive substrate materials may be germanium (Ge), gallium arsenide (GaAs), indium phosphate (InP), tantalum carbide (SiC), germanium (Si), lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO). ), gallium nitride (GaN), aluminum nitride (AlN), metal. One of the transparent substrate materials may be sapphire, lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, and diamond-like carbon (Diamond-Like Carbon). ; DLC), spinel (MgAl ₂ O ₄ ), yttrium oxide (SiO _X ), and lithium gallate (LiGaO ₂ ). In an embodiment, the carrier substrate 40 may have a complete surface, ie, without any holes.

Thereafter, as shown in FIG. 3H to FIG. 3I, a second etching is performed on the transition layer island 32i to remove the transition layer island 32i and the substrate 30, and the first surface 34B of the semiconductor island 34i is exposed. Thereafter, at least one second electrode 44 is formed over the first surface 34B of the semiconductor island 34i. In one embodiment, the second etching may be a chemical etching, and the etching solution may be selected from the group consisting of hydrofluoric acid (HF), Buffer Oxide Etcher (BOE) or cerium oxide etching. Surfactanated Buffered Oxide Etchants (SBOE). In an embodiment, the first etching time may be 20-50 minutes, or 40-60 minutes, or 60-90 minutes, or 90-120 minutes, or 120-150 minutes, or 150-180 minutes, or The etchant concentration can be 30-60% for 180-240 minutes. With the trench T disclosed in the above embodiment, the time required for the second etching can be reduced from one day to several hours, and the process yield efficiency can be greatly increased.

In an embodiment, the material of the first electrode 36 or the second electrode 44 includes, but is not limited to, copper (Cu), aluminum (Al), indium (In), tin (Sn), gold (Au), platinum (Pt). , zinc (Zn), silver (Ag), Titanium (Ti), nickel (Ni), lead (Pb), palladium (Pd), germanium (Ge), chromium (Cr), cadmium (Cd), cobalt (Co), manganese (Mn), antimony (Sb), Bi (Bi), gallium (Ga), thallium (Tl), antimony (Po), antimony (Ir), antimony (Re), antimony (Rh), antimony (Os), tungsten (W), lithium (Li), Sodium (Na), potassium (K), beryllium (Be), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), zirconium (Zr), molybdenum (Mo), sodium (La), Silver-titanium (Ag-Ti), copper-tin (Cu-Sn), copper-zinc (Cu-Zn), copper-cadmium (Cu-Cd), tin-lead-bismuth (Sn-Pb-Sb), tin - lead-zinc (Sn-Pb-Zn), nickel-tin (Ni-Sn), nickel-cobalt (Ni-Co), gold alloy (Au alloy), or bismuth-gold-nickel (Ge-Au-Ni) Metal materials.

Finally, as shown in FIG. 3J, in one embodiment, the second connection layer 42 and the carrier substrate 40 can be diced to complete the photovoltaic device 300 fabricated in accordance with the process of the present invention.

Figure 4 is a top view photo showing the design of the present invention. As shown in the photograph, a portion of the first surface 34B of the semiconductor island 34i in the photovoltaic element 300 fabricated in accordance with the process of the present invention is a rough surface M. The surface is a rough surface caused by a second etching of the transition layer island 32i and shifting the transition layer island 32i in the above process. In one embodiment, the rough surface M is formed in a geometric central region of a portion of the first surface 34B of the semiconductor island 34i.

5A to 5C are schematic views showing a light emitting module, and FIG. 5A is a perspective view showing an external light emitting module. The light emitting module 500 can include a carrier 502, a plurality of lenses 504, 506, and 508. 510, and two power supply terminals 512 and 514.

Fig. 5B-5C shows a cross-sectional view of a light emitting module, wherein Fig. 5C is an enlarged view of the E area of Fig. 5B. The carrier 502 can include an upper carrier 503 and a download body 501, wherein a surface of the download body 501 can be in contact with the upper carrier 503. Lenses 504 and 508 are formed over upper carrier 503. The upper carrier 503 may form at least one through hole 515, and the light emitting element 300 formed according to the embodiment of the present invention may be formed in the through hole 515 and in contact with the download body 501, and surrounded by the rubber 521. There is a lens 508 above the glue 521.

As shown in FIG. 5C, in one embodiment, a reflective layer 519 may be formed on both sidewalls of the via 515 to increase light extraction efficiency; a metal layer 517 may be formed on the lower surface of the download body 501 to improve heat dissipation efficiency.

6A-6B is a schematic diagram 600 of a light source generating device. A light source generating device 600 can include a light emitting module 500, a housing 540, and a power supply system (not shown) for supplying a current to the light emitting module 600. And a control element (not shown) for controlling the power supply System (not shown). The light source generating device 600 can be a lighting device, such as a street light, a car light or an indoor lighting source, or a backlight source of a traffic sign or a backlight module in a flat display.

Figure 7 is a schematic view of a light bulb. The light bulb 900 includes a housing 921, a lens 922, a lighting module 924, a bracket 925, a heat sink 926, a connecting portion 927 and an electrical connector 928. The illumination module 924 includes a carrier 923 and includes at least one of the photovoltaic elements 300 of the above embodiment on the carrier 923.

The first semiconductor layer 341 and the second semiconductor layer 343 are different in electrical conductivity, polarity or dopant, and are respectively used to provide a single or multi-layer structure of a semiconductor material of electrons and holes ("multilayer" means two or two layers. Above the layer, the following is the same.) The electrical selection may be a combination of at least any two of p-type, n-type, and i-type. The active layer 342 is located between the two portions of the electrical, polar or dopant, or between the semiconductor materials for providing electrons and holes, respectively, for the conversion of electrical energy and light energy or induced conversion. region. Those who convert or induce light energy are such as light-emitting diodes, liquid crystal displays, and organic light-emitting diodes; those that convert or induce light energy are such as solar cells and photodiodes. The structure of the active layer 342 is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-layer quantum well (multi- Quantum well; MQW) structure. When the photovoltaic element 300 is a light-emitting diode, its light-emitting spectrum can be adjusted by changing the physical or chemical elements of the semiconductor single layer or multiple layers. Furthermore, adjusting the logarithm of the quantum well can also change the wavelength of the illumination.

In an embodiment of the invention, the semiconductor epitaxial layer 34 and the substrate 30 may optionally include a buffer layer (not shown). The buffer layer is interposed between the two material systems to "transition" the material system of the substrate to the material system of the semiconductor system. For the structure of the light-emitting diode, on the one hand, the buffer layer is used to reduce the material layer of the lattice mismatch between the two materials. In another aspect, the buffer layer may also be a single layer, a plurality of layers or a structure for combining two materials or two separate structures, such as organic materials, inorganic materials, metals, and semiconductors; The selected structure is: reflective layer, thermally conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment (stress Adjustment) layer, bonding layer, wavelength conversion layer, mechanical fixing structure, and the like.

A contact layer (not shown) is more selectively formed on the semiconductor epitaxial laminate 34. The contact layer is disposed on one side of the semiconductor epitaxial layer 34 away from the substrate 30. In particular, the contact layer can be an optical layer, an electrical layer, or a combination of both. The optical layer can alter the electromagnetic radiation or light from or into the active layer. As used herein, "change" means changing at least one optical property of electromagnetic radiation or light, including but not limited to frequency, wavelength, intensity, flux, efficiency, color temperature, rendering index, light field. (light field), and angle of view. The electrical layer system may change or change the value, density, distribution of at least one of voltage, resistance, current, and capacitance between opposite sides of any one of the contact layers. The constituent material of the contact layer comprises an oxide, a conductive oxide, a transparent oxide, an oxide having a transmittance of 50% or more, a metal, a relatively light-transmissive metal, a metal having a transmittance of 50% or more, an organic substance, At least one of an inorganic substance, a phosphor, a phosphor, a ceramic, a semiconductor, a doped semiconductor, and an undoped semiconductor. In some applications, the material of the contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. In the case of a relatively light-transmitting metal, the thickness thereof is preferably about 0.005 μm to 0.6 μm. In one embodiment, the contact layer has a preferred lateral current spreading rate that can be used to assist in the uniform diffusion of current into the semiconductor epitaxial stack 34. Generally, the impurities blended according to the contact layer vary depending on the manner of the process, and the width of the energy gap may be between 0.5 eV and 5 eV.

The above figures and descriptions are only corresponding to specific embodiments, however, the elements, embodiments, design criteria, and technical principles described or disclosed in the various embodiments are inconsistent, contradictory, or difficult to implement together. In addition, we may use any reference, exchange, collocation, coordination, or merger as required. Although the invention has been described above, it is not intended to limit the scope of the invention, the order of implementation, or the materials and process methods used. Various modifications and variations of the present invention are possible without departing from the spirit and scope of the invention.

Claims (8)

A method of fabricating a photovoltaic element, comprising the steps of: providing a growth substrate; forming a transition layer over the growth substrate; forming a semiconductor layer over the transition layer; performing the semiconductor stack and the transition layer a first etching to form at least one trench, wherein the trench separates the semiconductor stack and the transition layer into a plurality of semiconductor islands and a plurality of transition layer islands, and the trench exposes a portion of the growth substrate; providing a non-conductive substrate Connecting the semiconductor islands; and removing the growth substrate. The method of claim 1, further comprising removing the plurality of transition layer islands, wherein the plurality of transition layer islands are located between the plurality of semiconductor islands and the growth substrate. The method of claim 1, further comprising forming an electrode on the semiconductor islands. The method of claim 1, wherein the first etching etchant is selected from the group consisting of hydrofluoric acid (HF), Buffer Oxide Etcher (BOE) or cerium oxide etching solution (Surfactanated). Buffered Oxide Etchants, SBOE). The method of claim 1, wherein the material of the transition layer is selected from the group consisting of an oxide of cerium or a nitride of cerium. The method of claim 1, further comprising forming a first connection layer over the semiconductor layer and performing a first etching on the first connection layer, the semiconductor layer and the transition layer to form at least one a trench, wherein the trench separates the first connecting layer into a plurality of first connecting layer islands, wherein the material of the first connecting layer is a conductive material. The method of claim 6, further comprising forming a second connection layer on the non-conductive substrate and then connecting to the semiconductor islands, wherein the material of the second connection layer is a conductive material. The method of claim 1, wherein the transitional islands have an undercut shape relative to the plurality of semiconductor islands.