TWI451597B - Optoelectronic device and method for manufacturing the same - Google Patents

Optoelectronic device and method for manufacturing the same Download PDF

Info

Publication number
TWI451597B
TWI451597B TW100102057A TW100102057A TWI451597B TW I451597 B TWI451597 B TW I451597B TW 100102057 A TW100102057 A TW 100102057A TW 100102057 A TW100102057 A TW 100102057A TW I451597 B TWI451597 B TW I451597B
Authority
TW
Taiwan
Prior art keywords
layer
transition
stack
transition layer
width
Prior art date
Application number
TW100102057A
Other languages
Chinese (zh)
Other versions
TW201218419A (en
Inventor
Wei Chih Peng
Min Hsun Hsieh
Ming Chi Hsu
Wei Yu Yen
Chun Kai Wang
Yen Chih Chen
Schang Jing Hon
Original Assignee
Epistar Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epistar Corp filed Critical Epistar Corp
Priority to TW100102057A priority Critical patent/TWI451597B/en
Priority to US13/178,323 priority patent/US8344409B2/en
Priority to US13/225,117 priority patent/US8519430B2/en
Publication of TW201218419A publication Critical patent/TW201218419A/en
Priority to US13/731,919 priority patent/US8946736B2/en
Priority to US13/967,193 priority patent/US9070827B2/en
Application granted granted Critical
Publication of TWI451597B publication Critical patent/TWI451597B/en
Priority to US14/589,683 priority patent/US9530940B2/en
Priority to US14/753,405 priority patent/US20150318439A1/en
Priority to US15/345,185 priority patent/US9876139B2/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02Details
    • H01L31/0232Optical elements or arrangements associated with the device
    • H01L31/02327Optical elements or arrangements associated with the device the optical elements being integrated or being directly associated to the device, e.g. back reflectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/054Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means
    • H01L31/0547Optical elements directly associated or integrated with the PV cell, e.g. light-reflecting means or light-concentrating means comprising light concentrating means of the reflecting type, e.g. parabolic mirrors, concentrators using total internal reflection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/80Constructional details
    • H10K50/85Arrangements for extracting light from the devices
    • H10K50/854Arrangements for extracting light from the devices comprising scattering means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/80Constructional details
    • H10K50/85Arrangements for extracting light from the devices
    • H10K50/856Arrangements for extracting light from the devices comprising reflective means
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00Organic light-emitting devices
    • H10K50/80Constructional details
    • H10K50/85Arrangements for extracting light from the devices
    • H10K50/858Arrangements for extracting light from the devices comprising refractive means, e.g. lenses
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • Y02E10/52PV systems with concentrators

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Led Devices (AREA)
  • Photovoltaic Devices (AREA)

Description

光電元件及其製造方法Photoelectric element and method of manufacturing same

本發明係關於一種具有形成在半導體與基板間之緩衝疊層結構之光電元件。The present invention relates to a photovoltaic element having a buffer laminate structure formed between a semiconductor and a substrate.

發光二極體是半導體元件中一種被廣泛使用的光源。相較於傳統的白熾燈泡或螢光燈管,發光二極體具有省電及使用壽命較長的特性,因此逐漸取代傳統光源,而應用於各種領域,如交通號誌、背光模組、路燈照明、醫療設備等產業。A light-emitting diode is a widely used light source among semiconductor elements. Compared with traditional incandescent bulbs or fluorescent tubes, LEDs have the characteristics of power saving and long service life, so they gradually replace traditional light sources and are used in various fields such as traffic signs, backlight modules, and street lamps. Lighting, medical equipment and other industries.

隨著發光二極體光源的應用與發展對於亮度的需求越來越高,如何增加其發光效率以提高其亮度,便成為產業界所共同努力的重要方向。With the application and development of the light-emitting diode light source, the demand for brightness is getting higher and higher, and how to increase its luminous efficiency to increase its brightness has become an important direction for the industry to work together.

第4A圖係習知之發光元件結構示意圖,如第4A圖所示,習知之發光元件100,包含有一透明基板10、一緩衝層11、一位於透明基板10上之半導體疊層12,以及至少一電極14位於上述半導體疊層12上,其中上述之半導體疊層12由下而上至少包含一第一導電型半導體層120、一活性層122,以及一第二導電型半導體層124。其中緩衝層11中包含至少一孔隙111。4A is a schematic view showing the structure of a conventional light-emitting element. As shown in FIG. 4A, a conventional light-emitting element 100 includes a transparent substrate 10, a buffer layer 11, a semiconductor laminate 12 on the transparent substrate 10, and at least one. The electrode 14 is disposed on the semiconductor stack 12, wherein the semiconductor stack 12 includes at least a first conductive semiconductor layer 120, an active layer 122, and a second conductive semiconductor layer 124 from bottom to top. The buffer layer 11 includes at least one aperture 111 therein.

然而,如第4B圖所示,於習知之發光元件100中,由於緩衝層11中之孔隙111容易造成發光元件100產生灰面,反而降低透光性。However, as shown in FIG. 4B, in the conventional light-emitting element 100, since the aperture 111 in the buffer layer 11 easily causes the light-emitting element 100 to generate a gray surface, the light transmittance is reduced.

一種光電元件,包含:一基板,及一第一過渡疊層,位於基板之上,其中第一過渡疊層包含至少一第一過渡層,位於基板之上,且第一過渡層內部具有至少一孔洞結構,及一第二過渡層,係為一非故意摻雜層或一未摻雜層,且位於第一過渡層之上。A photovoltaic element comprising: a substrate, and a first transition stack on the substrate, wherein the first transition stack comprises at least one first transition layer on the substrate, and the first transition layer has at least one inside The hole structure, and a second transition layer, is an unintentionally doped layer or an undoped layer and is located above the first transition layer.

為了使本發明之敘述更加詳盡與完備,請參照下列描述並配合第1A圖至第1E圖之圖示。如第1A~第1E圖所例示,依據本發明第一實施例之光電元件100之製造方法簡述如下:如第1A~1B圖所示,在一具有一法線方向N之基板101第一表面1011上成長一第一過渡層1021,其中第一過渡層1021之厚度可介於0.3μm~3μm,或0.4μm~3μm,或0.5μm~3μm,或0.7μm~3μm,或1μm~3μm,或2μm~3μm。In order to make the description of the present invention more detailed and complete, please refer to the following description and the diagrams of FIGS. 1A to 1E. As illustrated in FIGS. 1A to 1E, the manufacturing method of the photovoltaic element 100 according to the first embodiment of the present invention is briefly described as follows: as shown in FIGS. 1A to 1B, the substrate 101 having a normal direction N is first. A first transition layer 1021 is grown on the surface 1011, wherein the thickness of the first transition layer 1021 can be between 0.3 μm and 3 μm, or 0.4 μm to 3 μm, or 0.5 μm to 3 μm, or 0.7 μm to 3 μm, or 1 μm to 3 μm. Or 2μm~3μm.

之後,第一過渡層1021可藉由電化學蝕刻、非等向性蝕刻,例如感應耦合電漿(inductive coupling plasma,ICP)之乾蝕刻,或使用草酸、氫氧化鉀、或磷酸硫酸溶液等單一溶液或混合溶液進行濕蝕刻,使第一過渡層1021之內部包含至少一個孔洞結構,例如為孔洞(pore,void,bore)、針孔(pinhole),或至少兩個孔洞結構可相互連結形成一網狀孔洞結構(porous structure),其形成之一種方法可參閱本案申請人之第099132135號台灣專利申請案,並援引其為本申請案之一部分。Thereafter, the first transition layer 1021 can be etched by electrochemical etching, anisotropic etching, such as dry etching of inductive coupling plasma (ICP), or using a single oxalic acid, potassium hydroxide, or phosphoric acid sulfuric acid solution. The solution or the mixed solution is subjected to wet etching so that the inside of the first transition layer 1021 includes at least one pore structure, for example, a pore, a void, a pinhole, or at least two pore structures may be connected to each other to form a A porous structure is disclosed in the Taiwan Patent Application No. 099132135, the entire disclosure of which is incorporated herein by reference.

之後,如第1B圖所示,於第一過渡層1021上成長一第二過渡層1022,其中第一過渡層1021與第二過渡層1022可合稱為一第一過渡疊層102a。第二過渡層1022之成長溫度可介於800~1200℃,壓力範圍100~700 mbar,其調整係配合第一過渡層1021之孔洞大小與密度,以在第一過渡層1021之上進行橫向修補癒合,使靠近第一過渡層1021與第二過渡層1022介面之孔洞變小,並繼續成長第二過渡層1022。Then, as shown in FIG. 1B, a second transition layer 1022 is grown on the first transition layer 1021, wherein the first transition layer 1021 and the second transition layer 1022 can be collectively referred to as a first transition stack 102a. The second transition layer 1022 may have a growth temperature of 800 to 1200 ° C and a pressure range of 100 to 700 mbar, and the adjustment is matched with the hole size and density of the first transition layer 1021 to perform lateral repair on the first transition layer 1021. Healing, the pores close to the interface between the first transition layer 1021 and the second transition layer 1022 are made smaller, and the second transition layer 1022 continues to grow.

其中上述複數層第一過渡層1021可包含相同或不同寬度之孔洞結構。在一實施例中,上述複數層第一過渡層1021各層中之孔洞結構之寬度從靠近基板處往靠近第二過渡層1022方向漸減。在本實施例中,第一過渡疊層102a之材料包含一種或一種以上之元素選自鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)以及矽(Si)所構成群組。在一實施例中,第一過渡層1021可為一n-type摻雜層,摻雜濃度可介於1E15~1E19 cm-3 ,或1E16~1E19 cm-3 ,或1E17~1E19 cm-3 ,或1E18~1E19 cm-3 ,或5x1E18~1E19 cm-3 ,或5x1E17~1E19 cm-3 ,或5x1E17~1E18 cm-3 。在一實施例中,第二過渡層1022係為一非故意摻雜層(unintentional doped layer)或一未摻雜層(undoped layer)。Wherein the plurality of first layer first transition layers 1021 may comprise pore structures of the same or different widths. In one embodiment, the width of the hole structure in each of the plurality of first transition layers 1021 is gradually reduced from near the substrate toward the second transition layer 1022. In this embodiment, the material of the first transition layer stack 102a comprises one or more elements selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), and nitrogen ( N) and 矽 (Si) constitute a group. In an embodiment, the first transition layer 1021 can be an n-type doped layer, and the doping concentration can be 1E15~1E19 cm -3 , or 1E16~1E19 cm -3 , or 1E17~1E19 cm -3 . Or 1E18~1E19 cm -3 , or 5x1E18~1E19 cm -3 , or 5x1E17~1E19 cm -3 , or 5x1E17~1E18 cm -3 . In an embodiment, the second transition layer 1022 is an unintentional doped layer or an undoped layer.

在本實施例中,第一過渡層1021中之孔洞或網狀孔洞之寬度可介於10nm~2000nm,或100nm~2000nm,或300nm~2000nm,或500nm~2000nm,或800nm~2000nm,或1000nm~2000nm,或1300nm~2000nm,或1500nm~2000nm,或1800nm~2000nm。在一實施例中,較接近基板之孔洞寬度大於較接近第二過渡層之孔洞寬度。In this embodiment, the width of the hole or the mesh hole in the first transition layer 1021 may be between 10 nm and 2000 nm, or 100 nm to 2000 nm, or 300 nm to 2000 nm, or 500 nm to 2000 nm, or 800 nm to 2000 nm, or 1000 nm. 2000 nm, or 1300 nm to 2000 nm, or 1500 nm to 2000 nm, or 1800 nm to 2000 nm. In one embodiment, the hole width closer to the substrate is greater than the hole width closer to the second transition layer.

在另一實施例中,第一過渡層1021中之複數個孔洞或網狀孔洞群可為一規則陣列結構。其中複數個孔洞之平均寬度Wx 可介於10nm~2000nm,或100nm~2000nm,或300nm~2000nm,或500nm~2000nm,或800nm~2000nm,或1000nm~2000nm,或1300nm~2000nm,或1500nm~2000nm,或1800nm~2000nm。在一實施例中,上述複數個孔洞或網狀孔洞群之平均間距可介於10nm~2000nm,或100nm~2000nm,或300nm~2000nm,或500nm~2000nm,或800nm~2000nm,或1000nm~2000nm,或1300nm~2000nm,或1500nm~2000nm,或1800nm~2000nm。In another embodiment, the plurality of holes or mesh holes in the first transition layer 1021 may be a regular array structure. The average width W x of the plurality of holes may be between 10 nm and 2000 nm, or 100 nm to 2000 nm, or 300 nm to 2000 nm, or 500 nm to 2000 nm, or 800 nm to 2000 nm, or 1000 nm to 2000 nm, or 1300 nm to 2000 nm, or 1500 nm to 2000 nm. , or 1800nm~2000nm. In an embodiment, the average spacing of the plurality of holes or mesh holes may be between 10 nm and 2000 nm, or 100 nm to 2000 nm, or 300 nm to 2000 nm, or 500 nm to 2000 nm, or 800 nm to 2000 nm, or 1000 nm to 2000 nm. Or 1300nm~2000nm, or 1500nm~2000nm, or 1800nm~2000nm.

上述複數個孔洞或網狀孔洞群形成之孔隙度Φ(porosity)定義為孔洞或網狀孔洞群之總體積VV 除以整體體積VT (),其中整體體積VT 為第一過渡層1021總體積。在本實施例中,孔隙度Φ可介於5%-90%,或10%-90%,或20%-90%,或30%-90%,或40%-90%,或50%-90%,或60%-90%,或70%-90%,或80%-90%。接著,如第1C圖所示,於上述第二過渡層1022之上繼續成長一第一半導體層103、一主動層104與一第二半導體層105。The porosity Φ formed by the plurality of holes or mesh groups is defined as the total volume V V of the holes or mesh holes divided by the total volume V T ( Wherein the overall volume V T is the total volume of the first transition layer 1021. In this embodiment, the porosity Φ may be between 5% and 90%, or 10% to 90%, or 20% to 90%, or 30% to 90%, or 40% to 90%, or 50%. 90%, or 60%-90%, or 70%-90%, or 80%-90%. Next, as shown in FIG. 1C, a first semiconductor layer 103, an active layer 104 and a second semiconductor layer 105 are grown on the second transition layer 1022.

最後,如第1D圖所示,於第二半導體層105與基板101之上分別形成兩電極106、107以形成一垂直式光電元件100。Finally, as shown in FIG. 1D, two electrodes 106, 107 are formed on the second semiconductor layer 105 and the substrate 101, respectively, to form a vertical photovoltaic element 100.

在另一實施例中,如第1E圖所示,蝕刻部分上述主動層104與一第二半導體層105以露出部分第一半導體層103後,於第一半導體層103及第二半導體層105之上形成兩電極106、107以形成一水平式光電元件100’。上述電極106、107材料可選自:鉻(Cr)、鈦(Ti)、鎳(Ni)、鉑(Pt)、銅(Cu)、金(Au)、鋁(Al)、或銀(Ag)等金屬材料。In another embodiment, as shown in FIG. 1E, after the active portion 104 and a second semiconductor layer 105 are etched to expose a portion of the first semiconductor layer 103, the first semiconductor layer 103 and the second semiconductor layer 105 are Two electrodes 106, 107 are formed thereon to form a horizontal photovoltaic element 100'. The materials of the electrodes 106 and 107 may be selected from the group consisting of chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or silver (Ag). Metal materials.

第1F圖係依本發明上述實施例所形成光電元件之部分掃描式電子顯微鏡(Scanning Electron Microscopy,SEM)圖,其中包含基板101、第一過渡層1021、第二過渡層1022與第一半導體層103。1F is a partial scanning electron microscope (SEM) image of a photovoltaic element formed according to the above embodiment of the present invention, comprising a substrate 101, a first transition layer 1021, a second transition layer 1022 and a first semiconductor layer. 103.

上述第一過渡層1021中之複數個孔洞或網狀孔洞群係為中空結構,此複數個孔洞或網狀孔洞群具有一折射率,適可作為空氣透鏡,當光線於光電元件100中行進至複數個孔洞或網狀孔洞群時,由於複數個孔洞或網狀孔洞群內外部材料折射率之差異(例如,半導體層之折射率約介於2~3之間,空氣的折射率為1),光線會在複數個孔洞或網狀孔洞群處改變行進方向而離開光電元件,因而增加光摘出效率。另外,複數個孔洞或網狀孔洞群也可作為一散射中心(scattering center)以改變光子之行進方向並且減少全反射。藉由孔洞密度的增加,可更增加上述功效。The plurality of holes or mesh holes in the first transition layer 1021 are hollow structures, and the plurality of holes or mesh holes have a refractive index, which is suitable as an air lens, when the light travels to the photoelectric element 100 to When a plurality of holes or mesh holes are different, the refractive index difference between the inner and outer materials of a plurality of holes or mesh holes (for example, the refractive index of the semiconductor layer is between 2 and 3, and the refractive index of air is 1) The light will change the direction of travel at a plurality of holes or mesh holes to leave the photovoltaic element, thereby increasing the light extraction efficiency. In addition, a plurality of holes or mesh holes can also serve as a scattering center to change the direction of travel of the photons and reduce total reflection. By increasing the density of the holes, the above effects can be further increased.

而第二過渡層1022可為一非故意摻雜層(unintentional doped layer)或一未摻雜層(undoped layer),其成長在第一過渡層1021上時係先進行上述複數個孔洞或網狀孔洞群結構之修補與癒合,再往上繼續磊晶成長,可避免直接成長n型或p型摻雜之半導體層時因摻雜物質,例如為(Si)或鎂(Mg)吸附於孔洞周圍,而造成透光性下降,反而使光電元件之光取出效率下降。The second transition layer 1022 can be an unintentional doped layer or an undoped layer. When growing on the first transition layer 1021, the plurality of holes or meshes are first performed. The repair and healing of the pore group structure, and further epitaxial growth, can avoid the direct growth of the n-type or p-type doped semiconductor layer due to dopant substances, such as (Si) or magnesium (Mg) adsorbed around the hole As a result, the light transmittance is lowered, and the light extraction efficiency of the photovoltaic element is lowered.

如第2A~第2C圖所例示,顯示本發明另一實施例之光電元件結構簡圖:如第2A~2C圖所示,第一過渡疊層102a也可包含多層的第一過渡層1021與一層第二過渡層1022。如第2A圖所示,可包含兩層第一過渡層1021形成於基板(圖未示)之上及一層第二過渡層1022形成於第一過渡層1021之上。As shown in FIGS. 2A-2C, a schematic diagram of a structure of a photovoltaic element according to another embodiment of the present invention is shown. As shown in FIGS. 2A-2C, the first transition layer 102a may also include a plurality of layers of the first transition layer 1021 and A second layer of transition layer 1022. As shown in FIG. 2A, two first transition layers 1021 may be formed on a substrate (not shown) and a second transition layer 1022 may be formed on the first transition layer 1021.

如第2B圖所示,可包含三層第一過渡層1021形成於基板(圖未示)之上及一層第二過渡層1022形成於第一過渡層1021之上。如第2C圖所示,依元件之實際設計也可包含n層的第一過渡層1021,其中n≧4,以達到更好之光學效果或減少應力之效果。在本實施例中,任一第一過渡層1021中包含至少一個孔洞結構,可為孔洞(pore,void,bore)、針孔(pinhole),或至少兩個孔洞結構可相互連結形成一網狀孔洞結構(porous structure),其形成方法、材料、大小與其他特性與上述實施例相同,在此不再贅述。As shown in FIG. 2B, three first transition layers 1021 may be formed on a substrate (not shown) and a second transition layer 1022 may be formed on the first transition layer 1021. As shown in FIG. 2C, the n-layer first transition layer 1021, n ≧ 4, may also be included depending on the actual design of the component to achieve a better optical effect or stress reduction effect. In this embodiment, any of the first transition layers 1021 includes at least one pore structure, which may be a pore, void, or a pinhole, or at least two pore structures may be connected to each other to form a mesh. The porous structure, the forming method, material, size and other characteristics are the same as those in the above embodiment, and will not be described herein.

如第3A~第3C圖所例示,顯示本發明另一實施例之光電元件結構簡圖:如第3A圖所示,本發明另一實施例之光電元件200,在本實施例中,在第一過渡疊層102a之上尚可包含一第二過渡疊層102b。在一實施例中,第一過渡疊層102a如同上述實施例,可包含至少一層第一過渡層(圖未示)及一層第二過渡層(圖未示),且第二過渡疊層102b,可包含至少一層第一過渡層(圖未示)及一層第二過渡層(圖未示)。在另一實施例中,如上述實施例所例示,第一過渡疊層102a與第二過渡疊層102b也可分別包含多層的第一過渡層(圖未示),且每一第一過渡層(圖未示)中包含至少一個孔洞結構,可為孔洞(pore,void,bore)、針孔(pinhole),或至少兩個孔洞結構可相互連結形成一網狀孔洞結構(porous structure),其形成方法、材料、大小與其他特性與上述實施例相同,在此不再贅述。As shown in FIGS. 3A to 3C, there is shown a schematic structural view of a photovoltaic element according to another embodiment of the present invention: as shown in FIG. 3A, a photovoltaic element 200 according to another embodiment of the present invention, in this embodiment, A second transition stack 102b may also be included over a transition stack 102a. In an embodiment, the first transition stack 102a, as in the above embodiment, may include at least one first transition layer (not shown) and a second transition layer (not shown), and the second transition stack 102b, At least one first transition layer (not shown) and one second transition layer (not shown) may be included. In another embodiment, as illustrated in the above embodiments, the first transition stack 102a and the second transition stack 102b may also respectively include a plurality of first transition layers (not shown), and each first transition layer (not shown) includes at least one pore structure, which may be a pore, void, or a pinhole, or at least two pore structures may be connected to each other to form a porous structure. The formation method, material, size and other characteristics are the same as those of the above embodiment, and will not be described again.

如第3B圖所示,本發明另一實施例之光電元件300,在本實施例中,在第一過渡疊層102a之上尚可包含一第二過渡疊層102b及一第三過渡疊層102c,其中第一過渡疊層102a如同上述實施例,可包含至少一層第一過渡層(圖未示)及一層第二過渡層(圖未示),且第二過渡疊層102b,可包含至少一層第一過渡層(圖未示)及一層第二過渡層(圖未示),且第三過渡疊層102c,可包含至少一層第一過渡層(圖未示)及一層第二過渡層(圖未示)。在一實施例中,如上述實施例所例示,第一過渡疊層102a、第二過渡疊層102b與第三過渡疊層102c也可分別包含多層的第一過渡層(圖未示),且每一第一過渡層(圖未示)中包含至少一個孔洞結構,可為孔洞(pore,void,bore)、針孔(pinhole),或至少兩個孔洞結構可相互連結形成一網狀孔洞結構(porous structure),其形成方法、材料、大小與其他特性與上述實施例相同,在此不再贅述。As shown in FIG. 3B, a photovoltaic element 300 according to another embodiment of the present invention may further include a second transition layer 102b and a third transition layer on the first transition layer 102a. 102c, wherein the first transition layer 102a, as in the above embodiment, may include at least one first transition layer (not shown) and a second transition layer (not shown), and the second transition stack 102b may include at least a first transition layer (not shown) and a second transition layer (not shown), and the third transition stack 102c may include at least one first transition layer (not shown) and a second transition layer ( The figure is not shown). In an embodiment, as illustrated in the above embodiments, the first transition stack 102a, the second transition stack 102b, and the third transition stack 102c may also include a plurality of first transition layers (not shown), and Each of the first transition layers (not shown) includes at least one pore structure, which may be a pore, void, or a pinhole, or at least two pore structures may be connected to each other to form a mesh-like pore structure. (porous structure), the formation method, material, size and other characteristics are the same as those of the above embodiment, and will not be described herein.

如第3C圖所示,本發明另一實施例之光電元件400,在本實施例中,在第一過渡疊層102a之上尚可包含一第二過渡疊層102b、一第三過渡疊層102c......至第n層過渡疊層,其中n≧4,其中每一過渡疊層,可包含至少一層第一過渡層(圖未示)及一層第二過渡層(圖未示)。在一實施例中,如上述實施例所例示,每一過渡疊層也可分別包含多層的第一過渡層(圖未示),且每一第一過渡層(圖未示)中包含至少一個孔洞結構,可為孔洞(pore,void,bore)、針孔(pinhole),或至少兩個孔洞結構可相互連結形成一網狀孔洞結構(porous structure),其形成方法、材料、大小與其他特性與上述實施例相同,在此不再贅述。As shown in FIG. 3C, a photovoltaic element 400 according to another embodiment of the present invention may further include a second transition layer 102b and a third transition layer on the first transition layer 102a. 102c ... to an n-th layer transition stack, wherein n ≧ 4, wherein each transition stack may comprise at least one first transition layer (not shown) and a second transition layer (not shown) ). In an embodiment, as illustrated in the above embodiments, each transition stack may also include a plurality of first transition layers (not shown), and each of the first transition layers (not shown) includes at least one The pore structure may be a pore, void, or a pinhole, or at least two pore structures may be connected to each other to form a porous structure, a method, a material, a size, and other characteristics. The same as the above embodiment, and details are not described herein again.

具體而言,光電元件100、200、300、400係包含發光二極體(LED)、光電二極體(photodiode)、光敏電阻(photoresister)、雷射(laser)、紅外線發射體(infrared emitter)、有機發光二極體(organic light-emitting diode)及太陽能電池(solar cell)中至少其一。基板101係為一成長及/或承載基礎。候選材料可包含導電基板或不導電基板、透光基板或不透光基板。其中導電基板材料其一可為鍺(Ge)、砷化鎵(GaAs)、銦化磷(InP)、碳化矽(SiC)、矽(Si)、鋁酸鋰(LiAlO2 )、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)、金屬。透光基板材料其一可為藍寶石(Sapphire)、鋁酸鋰(LiAlO2 )、氧化鋅(ZnO)、氮化鎵(GaN)、氮化鋁(AlN)、金屬、玻璃、鑽石、CVD鑽石、與類鑽碳(Diamond-Like Carbon;DLC)、尖晶石(spinel,MgAl2 O4 )、氧化鋁(Al2 O3 )、氧化矽(SiOX )及鎵酸鋰(LiGaO2 )。Specifically, the photovoltaic elements 100, 200, 300, and 400 include a light emitting diode (LED), a photodiode, a photoresistor, a laser, and an infrared emitter. At least one of an organic light-emitting diode and a solar cell. The substrate 101 is a growth and/or carrier foundation. The candidate material may comprise a conductive substrate or a non-conductive substrate, a light transmissive substrate or an opaque substrate. One of the conductive substrate materials may be germanium (Ge), gallium arsenide (GaAs), indium phosphate (InP), tantalum carbide (SiC), germanium (Si), lithium aluminate (LiAlO 2 ), zinc oxide (ZnO). ), gallium nitride (GaN), aluminum nitride (AlN), metal. One of the transparent substrate materials may be sapphire, lithium aluminate (LiAlO 2 ), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), metal, glass, diamond, CVD diamond, And Diamond-Like Carbon (DLC), spinel (MgAl 2 O 4 ), alumina (Al 2 O 3 ), yttrium oxide (SiO X ), and lithium gallate (LiGaO 2 ).

上述第一半導體層103及第二半導體層105係彼此中至少二個部分之電性、極性或摻雜物相異、或者係分別用以提供電子與電洞之半導體材料單層或多層(「多層」係指二層或二層以上,以下同。),其電性選擇可以為p型、n型、及i型中至少任意二者之組合。主動層104係位於第一半導體層103及第二半導體層105之間,為電能與光能可能發生轉換或被誘發轉換之區域。電能轉變或誘發光能者係如發光二極體、液晶顯示器、有機發光二極體;光能轉變或誘發電能者係如太陽能電池、光電二極體。上述第一半導體層103、主動層104及第二半導體層105其材料包含一種或一種以上之元素選自鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)以及矽(Si)所構成群組。The first semiconductor layer 103 and the second semiconductor layer 105 are different in electrical conductivity, polarity, or dopant from at least two portions, or are used to provide a single or multiple layers of semiconductor materials for electrons and holes, respectively (" "Multilayer" means two or more layers, the same applies hereinafter.) The electrical selection may be a combination of at least any two of p-type, n-type, and i-type. The active layer 104 is located between the first semiconductor layer 103 and the second semiconductor layer 105, and is a region where electrical energy and light energy may be converted or induced to be converted. Those who convert or induce light energy are such as light-emitting diodes, liquid crystal displays, and organic light-emitting diodes; those that convert or induce light energy are such as solar cells and photodiodes. The first semiconductor layer 103, the active layer 104, and the second semiconductor layer 105 have a material containing one or more elements selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), and phosphorus (P). ), a group of nitrogen (N) and bismuth (Si).

依據本發明之另一實施例之光電元件100、200、300、400係一發光二極體,其發光頻譜可以藉由改變半導體單層或多層之物理或化學要素進行調整。常用之材料係如磷化鋁鎵銦(AlGaInP)系列、氮化鋁鎵銦(AlGaInN)系列、氧化鋅(ZnO)系列等。主動層104之結構係如:單異質結構(single heterostructure;SH)、雙異質結構(double heterostructure;DH)、雙側雙異質結構(double-side double heterostructure;DDH)、或多層量子井(multi-quantμm well;MQW)。再者,調整量子井之對數亦可以改變發光波長。The photovoltaic element 100, 200, 300, 400 according to another embodiment of the present invention is a light-emitting diode whose light-emitting spectrum can be adjusted by changing the physical or chemical elements of the semiconductor single layer or layers. Commonly used materials are such as aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, zinc oxide (ZnO) series and the like. The structure of the active layer 104 is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-layer quantum well (multi- Quantμm well; MQW). Furthermore, adjusting the logarithm of the quantum well can also change the wavelength of the illumination.

於本發明之一實施例中,第一半導體層103與第一過渡疊層102a或第一過渡疊層102a與基板101間尚可選擇性地包含一緩衝層(buffer layer,未顯示)。此緩衝層係介於二種材料系統之間,使基板之材料系統”過渡”至半導體系統之材料系統。對發光二極體之結構而言,一方面,緩衝層係用以降低二種材料間晶格不匹配之材料層。另一方面,緩衝層亦可以是用以結合二種材料或二個分離結構之單層、多層或結構,其可選用之材料係如:有機材料、無機材料、金屬、及半導體等;其可選用之結構係如:反射層、導熱層、導電層、歐姆接觸(ohmic contact)層、抗形變層、應力釋放(stress release)層、應力調整(stress adjustment)層、接合(bonding)層、波長轉換層、及機械固定構造等。在一實施例中,此緩衝層之材料可為AlN、GaN,且形成方法可為濺鍍(Sputter)或原子層沉積(Atomic Layer Deposition,ALD)。In one embodiment of the present invention, the first semiconductor layer 103 and the first transition layer 102a or the first transition layer 102a and the substrate 101 may optionally include a buffer layer (not shown). The buffer layer is interposed between the two material systems to "transition" the material system of the substrate to the material system of the semiconductor system. For the structure of the light-emitting diode, on the one hand, the buffer layer is used to reduce the material layer of the lattice mismatch between the two materials. In another aspect, the buffer layer may also be a single layer, a plurality of layers or a structure for combining two materials or two separate structures, such as organic materials, inorganic materials, metals, and semiconductors; The selected structure is: reflective layer, thermally conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment layer, bonding layer, wavelength Conversion layer, mechanical fixing structure, etc. In an embodiment, the material of the buffer layer may be AlN, GaN, and the forming method may be sputtering or Atomic Layer Deposition (ALD).

第二半導體層105上更可選擇性地形成一接觸層(未顯示)。接觸層係設置於第二半導體層105遠離主動層104之一側。具體而言,接觸層可以為光學層、電學層、或其二者之組合。光學層係可以改變來自於或進入主動層104的電磁輻射或光線。在此所稱之「改變」係指改變電磁輻射或光之至少一種光學特性,前述特性係包含但不限於頻率、波長、強度、通量、效率、色溫、演色性(rendering index)、光場(light field)、及可視角(angle of view)。電學層係可以使得接觸層之任一組相對側間之電壓、電阻、電流、電容中至少其一之數值、密度、分布發生變化或有發生變化之趨勢。接觸層之構成材料係包含氧化物、導電氧化物、透明氧化物、具有50%或以上穿透率之氧化物、金屬、相對透光金屬、具有50%或以上穿透率之金屬、有機質、無機質、螢光物、磷光物、陶瓷、半導體、摻雜之半導體、及無摻雜之半導體中至少其一。於某些應用中,接觸層之材料係為氧化銦錫、氧化鎘錫、氧化銻錫、氧化銦鋅、氧化鋅鋁、與氧化鋅錫中至少其一。若為相對透光金屬,其厚度係約為0.005μm~0.6μm。A contact layer (not shown) is more selectively formed on the second semiconductor layer 105. The contact layer is disposed on a side of the second semiconductor layer 105 away from the active layer 104. In particular, the contact layer can be an optical layer, an electrical layer, or a combination of both. The optical layer can change the electromagnetic radiation or light from or into the active layer 104. As used herein, "change" means changing at least one optical property of electromagnetic radiation or light, including but not limited to frequency, wavelength, intensity, flux, efficiency, color temperature, rendering index, light field. (light field), and angle of view. The electrical layer system may change or change the value, density, distribution of at least one of voltage, resistance, current, and capacitance between opposite sides of any one of the contact layers. The constituent material of the contact layer comprises an oxide, a conductive oxide, a transparent oxide, an oxide having a transmittance of 50% or more, a metal, a relatively light-transmissive metal, a metal having a transmittance of 50% or more, an organic substance, At least one of an inorganic substance, a phosphor, a phosphor, a ceramic, a semiconductor, a doped semiconductor, and an undoped semiconductor. In some applications, the material of the contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. In the case of a relatively light-transmissive metal, the thickness is about 0.005 μm to 0.6 μm.

以上各圖式與說明雖僅分別對應特定實施例,然而,各個實施例中所說明或揭露之元件、實施方式、設計準則、及技術原理除在彼此顯相衝突、矛盾、或難以共同實施之外,吾人當可依其所需任意參照、交換、搭配、協調、或合併。The above figures and descriptions are only corresponding to specific embodiments, however, the elements, embodiments, design criteria, and technical principles described or disclosed in the various embodiments are inconsistent, contradictory, or difficult to implement together. In addition, we may use any reference, exchange, collocation, coordination, or merger as required.

雖然本發明已說明如上,然其並非用以限制本發明之範圍、實施順序、或使用之材料與製程方法。對於本發明所作之各種修飾與變更,皆不脫本發明之精神與範圍。Although the invention has been described above, it is not intended to limit the scope of the invention, the order of implementation, or the materials and process methods used. Various modifications and variations of the present invention are possible without departing from the spirit and scope of the invention.

101...基板101. . . Substrate

102a...第一過渡疊層102a. . . First transition stack

102b...第二過渡疊層102b. . . Second transition stack

102c...第三過渡疊層102c. . . Third transition stack

1021...第一過渡層1021. . . First transition layer

1022...第二過渡層1022. . . Second transition layer

103...第一半導體層103. . . First semiconductor layer

104...主動層104. . . Active layer

105...第二半導體層105. . . Second semiconductor layer

106、107...電極106, 107. . . electrode

第1A~1E圖係本發明實施例之光電元件之製程示意圖;1A to 1E are schematic views showing a process of a photovoltaic element according to an embodiment of the present invention;

第1F圖係依本發明實施例所形成光電元件之部分掃描式電子顯微鏡(Scanning Electron Microscopy,SEM)圖;1F is a partial scanning electron microscope (SEM) image of a photovoltaic element formed according to an embodiment of the present invention;

第2A~第2C圖係顯示本發明另一實施例之光電元件結構簡圖;2A to 2C are diagrams showing the structure of a photovoltaic element according to another embodiment of the present invention;

第3A~第3C圖係顯示本發明另一實施例之光電元件結構簡圖;3A to 3C are diagrams showing the structure of a photovoltaic element according to another embodiment of the present invention;

第4A圖係習知之發光元件結構示意圖;及Figure 4A is a schematic view showing the structure of a conventional light-emitting element;

第4B圖係習知之發光元件結構上視圖。Fig. 4B is a top view showing the structure of a conventional light-emitting element.

101...基板101. . . Substrate

102a...第一過渡疊層102a. . . First transition stack

103...第一半導體層103. . . First semiconductor layer

104...主動層104. . . Active layer

105...第二半導體層105. . . Second semiconductor layer

106、107...電極106, 107. . . electrode

Claims (18)

一種光電元件,包含:一基板;及一第一過渡疊層,位於該基板之上,其中該第一過渡疊層包含至少一第一過渡層,位於該基板之上,且該第一過渡層內部具有至少一孔洞結構,及一第二過渡層,係為一非故意摻雜層或一未摻雜層,且位於該第一過渡層之上。A photovoltaic element comprising: a substrate; and a first transition stack over the substrate, wherein the first transition stack comprises at least a first transition layer over the substrate, and the first transition layer The interior has at least one hole structure, and a second transition layer is an unintentionally doped layer or an undoped layer and is located above the first transition layer. 如請求項1所述之光電元件,其中該孔洞結構具有一寬度,其中該寬度係為該孔洞結構於平行該表面方向之最大尺寸,且該寬度介於10nm~2000nm。The photovoltaic device according to claim 1, wherein the hole structure has a width, wherein the width is a maximum dimension of the hole structure in a direction parallel to the surface, and the width is between 10 nm and 2000 nm. 如請求項1所述之光電元件,其中該光電元件包含複數個該孔洞結構,該些孔洞結構可相互連結,形成一個或複數個網狀孔洞群;或該些孔洞結構呈一規則陣列,且該些孔洞結構其平均間距介於10nm~2000nm,孔隙度介於5%-90%。The photovoltaic element of claim 1, wherein the photovoltaic element comprises a plurality of the hole structures, the hole structures may be coupled to each other to form one or a plurality of mesh holes; or the holes are in a regular array, and The pore structures have an average spacing of 10 nm to 2000 nm and a porosity of 5% to 90%. 如請求項1所述之光電元件,更包含一第一半導體層、一主動層及一第二半導體層形成於該過渡疊層之上,其中該過渡疊層、該第一半導體層、該主動層及該第二半導體層之材料包含一種或一種以上之元素選自鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)以及矽(Si)所構成群組。The photovoltaic device of claim 1, further comprising a first semiconductor layer, an active layer and a second semiconductor layer formed on the transition stack, wherein the transition stack, the first semiconductor layer, the active The material of the layer and the second semiconductor layer comprises one or more elements selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), and antimony ( Si) is a group. 如請求項2所述之光電元件,其中較接近基板之該孔洞結構寬度大於較接近第二過渡層之該孔洞結構寬度。The photovoltaic element of claim 2, wherein the width of the hole structure closer to the substrate is greater than the width of the hole structure closer to the second transition layer. 如請求項2所述之光電元件,其中該過渡疊層包含複數層第一過渡層,且該複數層第一過渡層包含不同寬度之孔洞結構,且該複數層第一過渡層各層中之該孔洞結構之寬度從靠近該基板處往靠近該第二過渡層方向漸減。The photovoltaic element according to claim 2, wherein the transition layer comprises a plurality of first transition layers, and the plurality of first transition layers comprise pore structures of different widths, and the plurality of layers of the first transition layer The width of the hole structure tapers from near the substrate toward the second transition layer. 如請求項1所述之光電元件,更包含一第二過渡疊層形成於該第一過渡疊層之上,其中該第二過渡疊層包含至少一第一過渡層,位於該第一過渡疊層之上,且該第一過渡層內部具有至少一孔洞結構,及一第二過渡層,係為一非故意摻雜層或一未摻雜層,且位於該第一過渡層之上。The photovoltaic element of claim 1, further comprising a second transition stack formed on the first transition stack, wherein the second transition stack comprises at least one first transition layer, the first transition stack Above the layer, the first transition layer has at least one hole structure inside, and a second transition layer is an unintentionally doped layer or an undoped layer, and is located above the first transition layer. 如請求項1所述之光電元件,其中該第一過渡層可為一n-type摻雜層,摻雜濃度可介於1E15~1E19 cm-3The photovoltaic device of claim 1, wherein the first transition layer is an n-type doped layer, and the doping concentration may be between 1E15 and 1E19 cm -3 . 一種製造一光電元件之方法,包含下列步驟:提供一基板;形成一第一過渡層於該基板之上;形成至少一孔洞結構,於該第一過渡層內;及形成一第二過渡層於該第一過渡層之上,其中該第二過渡層係為一非故意摻雜層或一未摻雜層。A method of fabricating a photovoltaic element, comprising the steps of: providing a substrate; forming a first transition layer over the substrate; forming at least one hole structure in the first transition layer; and forming a second transition layer Above the first transition layer, wherein the second transition layer is an unintentionally doped layer or an undoped layer. 如請求項9所述之方法,其中於該第一過渡層中形成孔洞結構之步驟包含電化學蝕刻、非等向性乾蝕刻或非等向性濕蝕刻。The method of claim 9, wherein the step of forming the void structure in the first transition layer comprises electrochemical etching, anisotropic dry etching, or anisotropic wet etching. 如請求項9所述之方法,其中該孔洞結構具有一寬度,其中該寬度係為該孔洞結構於平行該表面方向之最大尺寸,且該寬度介於10nm~2000nm。The method of claim 9, wherein the hole structure has a width, wherein the width is a maximum dimension of the hole structure in a direction parallel to the surface, and the width is between 10 nm and 2000 nm. 如請求項9所述之方法,其中該光電元件包含複數個該孔洞結構,該些孔洞結構可相互連結,形成一個或複數個網狀孔洞群;或該些孔洞結構呈一規則陣列,且該些孔洞結構其平均間距介於10nm~2000nm,孔隙度介於5%-90%。The method of claim 9, wherein the photovoltaic element comprises a plurality of the hole structures, the hole structures may be coupled to each other to form one or a plurality of mesh hole groups; or the hole structures are in a regular array, and the hole structure The pore structures have an average spacing of 10 nm to 2000 nm and a porosity of 5% to 90%. 如請求項9所述之方法,更包含形成一第一半導體層、一主動層及一第二半導體層於該過渡疊層之上,其中該過渡疊層、該第一半導體層、該主動層及該第二半導體層之材料包含一種或一種以上之元素選自鎵(Ga)、鋁(Al)、銦(In)、砷(As)、磷(P)、氮(N)以及矽(Si)所構成群組。The method of claim 9, further comprising forming a first semiconductor layer, an active layer and a second semiconductor layer over the transition stack, wherein the transition stack, the first semiconductor layer, the active layer And the material of the second semiconductor layer comprising one or more elements selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), and antimony (Si) ) the group formed. 如請求項11所述之方法,其中較接近基板之該孔洞結構寬度大於較接近第二過渡層之該孔洞結構寬度。The method of claim 11, wherein the width of the hole structure closer to the substrate is greater than the width of the hole structure closer to the second transition layer. 如請求項11所述之方法,其中該過渡疊層包含複數層第一過渡層,且該複數層第一過渡層包含不同寬度之孔洞結構,且該複數層第一過渡層各層中之該孔洞結構之寬度從靠近該基板處往靠近該第二過渡層方向漸減。The method of claim 11, wherein the transition stack comprises a plurality of first transition layers, and the plurality of first transition layers comprise pore structures of different widths, and the holes in the layers of the first transition layer of the plurality of layers The width of the structure tapers from near the substrate toward the second transition layer. 如請求項9所述之方法,其中該第一過渡疊層可更包含形成多層的第一過渡層於該基板及該第二過渡層之間。The method of claim 9, wherein the first transition stack further comprises a first transition layer forming a plurality of layers between the substrate and the second transition layer. 如請求項9所述之方法,更包含一第二過渡疊層形成於該第一過渡疊層之上,其中該第二過渡疊層包含至少一第一過渡層,位於該第一過渡疊層之上,且該第一過渡層內部具有至少一孔洞結構,及一第二過渡層,係為一非故意摻雜層或一未摻雜層,且位於該第一過渡層之上。The method of claim 9, further comprising forming a second transition stack over the first transition stack, wherein the second transition stack comprises at least one first transition layer over the first transition stack Above, the first transition layer has at least one hole structure inside, and a second transition layer is an unintentionally doped layer or an undoped layer, and is located above the first transition layer. 如請求項9所述之方法,其中該第一過渡層可為一n-type摻雜層,摻雜濃度可介於1E15~1E19 cm-3The method of claim 9, wherein the first transition layer is an n-type doped layer, and the doping concentration may be between 1E15 and 1E19 cm -3 .
TW100102057A 2005-10-19 2011-01-19 Optoelectronic device and method for manufacturing the same TWI451597B (en)

Priority Applications (8)

Application Number Priority Date Filing Date Title
TW100102057A TWI451597B (en) 2010-10-29 2011-01-19 Optoelectronic device and method for manufacturing the same
US13/178,323 US8344409B2 (en) 2010-10-29 2011-07-07 Optoelectronic device and method for manufacturing the same
US13/225,117 US8519430B2 (en) 2010-10-29 2011-09-02 Optoelectronic device and method for manufacturing the same
US13/731,919 US8946736B2 (en) 2010-10-29 2012-12-31 Optoelectronic device and method for manufacturing the same
US13/967,193 US9070827B2 (en) 2010-10-29 2013-08-14 Optoelectronic device and method for manufacturing the same
US14/589,683 US9530940B2 (en) 2005-10-19 2015-01-05 Light-emitting device with high light extraction
US14/753,405 US20150318439A1 (en) 2008-09-15 2015-06-29 Optoelectronic device and method for manufacturing the same
US15/345,185 US9876139B2 (en) 2005-10-19 2016-11-07 Light-emitting device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW99137445 2010-10-29
TW100102057A TWI451597B (en) 2010-10-29 2011-01-19 Optoelectronic device and method for manufacturing the same

Publications (2)

Publication Number Publication Date
TW201218419A TW201218419A (en) 2012-05-01
TWI451597B true TWI451597B (en) 2014-09-01

Family

ID=45995699

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100102057A TWI451597B (en) 2005-10-19 2011-01-19 Optoelectronic device and method for manufacturing the same

Country Status (2)

Country Link
US (1) US8344409B2 (en)
TW (1) TWI451597B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11631782B2 (en) 2018-01-26 2023-04-18 Cambridge Enterprise Limited Method for electrochemically etching a semiconductor structure
US11651954B2 (en) 2017-09-27 2023-05-16 Cambridge Enterprise Ltd Method for porosifying a material and semiconductor structure

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5961557B2 (en) 2010-01-27 2016-08-02 イェイル ユニヴァーシティ Conductivity-based selective etching for GaN devices and applications thereof
CN102054916B (en) * 2010-10-29 2012-11-28 厦门市三安光电科技有限公司 Reflector, manufacturing method thereof and luminescent device applying same
US9330911B2 (en) * 2011-08-22 2016-05-03 Invenlux Limited Light emitting device having group III-nitride current spreading layer doped with transition metal or comprising transition metal nitride
CN103474549B (en) * 2012-06-07 2016-12-14 清华大学 Semiconductor structure
US9583353B2 (en) 2012-06-28 2017-02-28 Yale University Lateral electrochemical etching of III-nitride materials for microfabrication
US9034686B2 (en) * 2012-06-29 2015-05-19 First Solar, Inc. Manufacturing methods for semiconductor devices
TWI565532B (en) * 2012-08-07 2017-01-11 國立交通大學 Nano-ball solution application method and application thereof
US8941111B2 (en) 2012-12-21 2015-01-27 Invensas Corporation Non-crystalline inorganic light emitting diode
DE102013111785A1 (en) * 2013-10-25 2015-04-30 Osram Oled Gmbh Optoelectronic component and method for producing an optoelectronic component
US11095096B2 (en) 2014-04-16 2021-08-17 Yale University Method for a GaN vertical microcavity surface emitting laser (VCSEL)
CN107078190B (en) 2014-09-30 2020-09-08 耶鲁大学 Method for GaN vertical microcavity surface emitting laser (VCSEL)
US11018231B2 (en) 2014-12-01 2021-05-25 Yale University Method to make buried, highly conductive p-type III-nitride layers
EP3298624B1 (en) 2015-05-19 2023-04-19 Yale University A method and device concerning iii-nitride edge emitting laser diode of high confinement factor with lattice matched cladding layer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW535300B (en) * 1999-12-03 2003-06-01 Cree Lighting Co Light emitting diode with enhanced light extraction, method for growing the same and method for manufacturing the same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0678196B1 (en) * 1993-01-08 2002-04-10 Massachusetts Institute Of Technology Low-loss optical and optoelectronic integrated circuits
US6918946B2 (en) * 2001-07-02 2005-07-19 Board Of Regents, The University Of Texas System Applications of light-emitting nanoparticles
US20060005763A1 (en) * 2001-12-24 2006-01-12 Crystal Is, Inc. Method and apparatus for producing large, single-crystals of aluminum nitride
DE102005004640B4 (en) * 2005-01-28 2009-01-29 Cross Match Technologies Gmbh Arrangement for the optoelectronic recording of large fingerprints
US20100135937A1 (en) * 2007-03-26 2010-06-03 The Trustees Of Columbia University In The City Of New York Metal oxide nanocrystals: preparation and uses
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
AU2009260690B2 (en) * 2008-03-14 2015-02-05 Nano-C, Inc. Carbon nanotube-transparent conductive inorganic nanoparticles hybrid thin films for transparent conductive applications
US8248305B2 (en) * 2008-06-03 2012-08-21 University Of Houston Antennas based on a conductive polymer composite and methods for production thereof
US8318126B2 (en) * 2009-05-04 2012-11-27 Wong Stanislaus S Methods of making metal oxide nanostructures and methods of controlling morphology of same
US8211782B2 (en) * 2009-10-23 2012-07-03 Palo Alto Research Center Incorporated Printed material constrained by well structures
EP3651212A3 (en) * 2010-08-07 2020-06-24 Tpk Holding Co., Ltd Device components with surface-embedded additives and related manufacturing methods

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW535300B (en) * 1999-12-03 2003-06-01 Cree Lighting Co Light emitting diode with enhanced light extraction, method for growing the same and method for manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11651954B2 (en) 2017-09-27 2023-05-16 Cambridge Enterprise Ltd Method for porosifying a material and semiconductor structure
US11631782B2 (en) 2018-01-26 2023-04-18 Cambridge Enterprise Limited Method for electrochemically etching a semiconductor structure

Also Published As

Publication number Publication date
US20120104440A1 (en) 2012-05-03
US8344409B2 (en) 2013-01-01
TW201218419A (en) 2012-05-01

Similar Documents

Publication Publication Date Title
TWI451597B (en) Optoelectronic device and method for manufacturing the same
TWI419367B (en) Optoelectronic device and method for manufacturing the same
US8519430B2 (en) Optoelectronic device and method for manufacturing the same
TWI501421B (en) Optoelectronic device and method for manufacturing the same
JP5763789B2 (en) Photoelectric device and manufacturing method thereof
US9070827B2 (en) Optoelectronic device and method for manufacturing the same
US8946736B2 (en) Optoelectronic device and method for manufacturing the same
TWI431810B (en) Optoelectronic device and method for manufacturing the same
CN102544287B (en) Photoelectric cell and manufacture method thereof
TWI495155B (en) Optoelectronic device and method for manufacturing the same
TWI618264B (en) Optoelectronic device and method for manufacturing the same
CN102420281B (en) Photoelectric element and manufacturing method thereof
CN102623580B (en) Photoelectric element and manufacturing method thereof
TWI528592B (en) Optoelectronic device
JP2012094752A (en) Photoelectric element and method of manufacturing the same
KR101643213B1 (en) Optoelectronic device and method for manufacturing the same
TWI619264B (en) Optoelectronic device and method for manufacturing the same
KR20120040426A (en) Optoelectronic device and method for manufacturing the same
TWI604635B (en) Optoelectronic device and method for manufacturing the same
JP2012142473A (en) Photoelectric element and method of manufacturing the same
TW201424059A (en) Optoelectronic device and method for manufacturing the same