TWI495155B - Optoelectronic device and method for manufacturing the same - Google Patents

Description

Photoelectric element and method of manufacturing same

The present invention relates to a photovoltaic element having a pore structure formed in a semiconductor layer.

A light-emitting diode is a widely used light source among semiconductor elements. Compared with traditional incandescent bulbs or fluorescent tubes, LEDs have the characteristics of power saving and long service life, so they gradually replace traditional light sources and are used in various fields such as traffic signs, backlight modules, and street lamps. Lighting, medical equipment and other industries.

With the application and development of the light-emitting diode light source, the demand for brightness is getting higher and higher, and how to increase its luminous efficiency to increase its brightness has become an important direction for the industry to work together.

A photovoltaic element comprising: a semiconductor stack; a first metal layer formed over the semiconductor stack, wherein the first metal layer has a first major plane and the thickness of both edges of the first metal layer is progressively thinned And a second metal layer formed on the first metal layer, wherein the second metal layer has a second main plane parallel to the first main plane and the thickness of both edges of the second metal layer is progressively thinned, And the edge of the second metal layer exceeds the edge of the first metal layer, and comprises: a substrate having a surface and having a normal direction perpendicular to the surface; and a plurality of first seed columns on the surface of the substrate Contacting the surface and exposing a surface of a portion of the substrate; a first protective layer on the sidewall of the first seed column and the exposed surface of the substrate; a first buffer layer located in the plurality of first seed columns Above, the first The punch layer has a first surface and a second surface opposite to the first surface, and the first surface is in direct contact with the plurality of first seed columns; and at least one first hole structure is located in the plurality of first seed columns Between the surface of the substrate and the first surface of the first buffer layer, wherein the at least one first hole structure has a width and a height, wherein the width is the largest dimension of the first hole structure in the direction of the parallel surface, and the height is The maximum dimension of the first hole structure in the direction parallel to the normal direction, wherein the ratio of the height to the width is between 1/5 and 3.

A photovoltaic element comprising: a substrate having a surface and having a normal direction perpendicular to the surface; a first semiconductor layer comprising a plurality of irregular pore structures on the surface of the substrate; and a protective layer at a plurality of a sidewall of the hole structure; and a buffer layer over the first semiconductor layer.

A method of fabricating a photovoltaic element, comprising the steps of: providing a substrate having a surface and having a normal direction perpendicular to the surface; forming a first semiconductor layer on the surface of the substrate; patterning the first a semiconductor layer to form a plurality of hole structures; a protective layer over the sidewalls of the hole structure; and a buffer layer over the first semiconductor layer.

1A to 1D, 1F is a schematic diagram of a process of a photovoltaic element according to an embodiment of the present invention; and FIG. 1E is a scanning electron microscope (SEM) diagram of a first hole formed according to an embodiment of the present invention; A schematic cross-sectional view of the optoelectronic semiconductor device of the present invention; and 3A to 3F are schematic views of the process of the photovoltaic device of the embodiment of the present invention.

The present invention discloses a light-emitting element and a method of manufacturing the same. In order to make the description of the present invention more detailed and complete, please refer to the following description and cooperate with the drawings of FIGS. 3A to 7. In order to make the description of the present invention more detailed and complete, please refer to the following description and cooperate with Figures 1A to 3 Graphic. As illustrated in FIGS. 1A to 1F, a method of manufacturing a photovoltaic element according to a first embodiment of the present invention is as follows: as shown in FIG. 1A, a first seed crystal is grown on a first surface 1011 of a substrate 101. Layer 102, wherein the substrate has a normal direction N.

Thereafter, as shown in FIG. 1B, the first seed layer 102 is etched into a plurality of first seed columns 1021 formed on the first surface 1011 of the substrate 101. In this embodiment, the first seed column 1021 is subjected to electrochemical etching, anisotropic etching, such as dry etching of an inductive coupling plasma (ICP), or using oxalic acid, potassium hydroxide, or Wet etching of a single solution or a mixed solution such as a phosphoric acid sulfuric acid solution to include at least one pore structure, such as pore, void, pinhole, or at least two pore structures may be connected to each other to form a net A method of forming a porous structure can be found in the Taiwan Patent Application No. 099132135, which is incorporated herein by reference.

Thereafter, as shown in FIG. 1C, a protective layer 103 is disposed on the surface of the first seed column 1021 and the exposed first surface of the substrate, and includes a sidewall coated on the first seed column 1021. The first protective layer 1031 is coated on the second protective layer 1032 on the first surface 1011 of the substrate exposed by the first seed column 1021, and the third surface coated on the top surface of the first seed column 1021. Protective layer 1033. In one embodiment, the protective layer 103 is formed by spin-on glass coating (SOG), and the material of the protective layer 103 may be SiO ₂ , HSQ (Hydrogen Silesquioxane), MSQ (Methylsequioxane), etc., by Silsequioxane. Polymer of the substrate (Polymer).

After the third protective layer 1033 is removed, the first buffer layer 105 is further grown, wherein the first buffer layer 105 is laterally elongated along the top surface of the plurality of first seed columns 1021 (Epitaxial Lateral). The method of Overgrowth, ELOG) grows laterally and upwardly. As shown in FIG. 1D, while growing the first buffer layer 105, it will be in two adjacent first seed column 1021, substrate 101 and first buffer. At least one first aperture 104 is formed between the layers 105. In the present embodiment, since the first protective layer 1031 covers the sidewall of the first seed column 1021, the directivity and spatial growth priority of the growth of the first buffer layer 105 can be effectively controlled. In this embodiment, the first seed layer 102 or the first buffer layer 105 may be an unintentionally doped layer or an undoped layer, or an n-type doped layer.

In an embodiment, the width of the first hole 104 may be between 50 nm and 600 nm. Or 50nm~500nm, or 50nm~400nm, or 50nm~300nm, or 50nm~200nm, or 50nm~100nm. The height of the first hole 104 may be between 0.5 μm and 2 μm, or 0.5 μm to 1.8 μm, or 0.5 μm to 1.6 μm, or 0.5 μm to 1.4 μm, or 0.5 μm to 1.2 μm, or 0.5 μm to 1 μm, or 0.5. Mm~0.8μm. In addition, in an embodiment, the first hole may have an aspect ratio (ratio of height to width) of 1/5~3, or 1/5~2, or 1/5~1, or 1/5. ~1/2, or 1/5~1/3, or 1/5~1/4. In an embodiment, a plurality of first holes 104 may be formed between two adjacent first seed columns 1021 and the substrate 101. In another embodiment, since the plurality of first seed columns 1021 can be a regular array structure, the plurality of first holes 104 can also be a regular array structure.

FIG. 1E shows a scan of the first hole 104 formed in accordance with an embodiment of the present invention. Scanning Electron Microscopy (SEM) image, as shown in FIG. 1E, the plurality of first holes 104 may be separate first holes 1041 independent of each other, or the first first holes 1041 may be connected to each other to form a Or a plurality of mesh first hole groups 1042.

The average width W _{x of} the plurality of first holes 104 may be between 50 nm and 600 nm, or 50 nm to 500 nm, or 50 nm to 400 nm, or 50 nm to 300 nm, or 50 nm to 200 nm, or 50 nm to 100 nm. The average height H _{x of} the plurality of first holes 104 may be between 0.5 μm and 2 μm, or 0.5 μm to 1.8 μm, or 0.5 μm to 1.6 μm, or 0.5 μm to 1.4 μm, or 0.5 μm to 1.2 μm, or 0.5. Mm~1μm, or 0.5μm~0.8μm. In an embodiment, the average spacing of the plurality of first holes 104 may be between 10 nm and 1.5 μm, or 30 nm to 1.5 μm, or 50 nm to 1.5 μm, 80 nm to 1.5 μm, or 1 μm to 1.5 μm, or 1.2 μm. ~1.5μm. In addition, in an embodiment, the plurality of first holes 104 may have an average aspect ratio (the ratio of the average height to the average width) is between 1/5 and 3, or 1/5 to 2, or 1/5. ~1, or 1/5~1/2, or 1/5~1/3, or 1/5~1/4. The porosity Φ formed by the plurality of first holes 104 is defined as the total volume V _V of the first hole 104 divided by the overall volume. Wherein the overall volume V _T is the total volume of the first hole 104 plus the volume of the first seed layer 102. In this embodiment, the porosity Φ may be between 5% and 90%, or 10% to 90%, or 20% to 90%, or 30% to 90%, or 40% to 90%, or 50%. 90%, or 60%-90%, or 70%-90%, or 80%-90%.

Next, as shown in FIG. 1F, continuing on the first buffer layer 105 After the first semiconductor layer 106, an active layer 107 and a second semiconductor layer 108 are formed, a portion of the active layer 107 and a second semiconductor layer 108 are etched to expose a portion of the first semiconductor layer 106, after the first semiconductor layer 106. Two electrodes 109, 110 are formed over the second semiconductor layer 108 to form a photovoltaic element 100. The materials of the electrodes 109 and 110 may be selected from the group consisting of chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or silver (Ag). A single composition of a metallic material or a combination of alloys or laminates.

In this embodiment, since the first hole 104 is a hollow structure, this The first hole 104 has a refractive index suitable as an air lens. When the light travels in the photovoltaic element 100 to the first hole 104, the refractive index of the outer material in the first hole 104 is different (for example, the refractive index of the buffer layer). Between about 2 and 3, the refractive index of the air is 1), the light will change direction at the first hole 104, and the light extraction efficiency is increased. In addition, the first hole 104 can also serve as a scattering center to change the direction of travel of the photons and reduce total reflection. By increasing the density of the first holes 104, the above effects can be further increased.

As illustrated in Fig. 2, a schematic cross-sectional view of a photovoltaic element according to a second embodiment of the present invention will be described. The process of this embodiment is substantially the same as that of the first embodiment. For details, refer to the first embodiment, and details are not described herein again. In this embodiment, a substrate 201 is formed on the plurality of first seed columns 2021 formed on the substrate 201, and a first protective layer 2031 is coated on the sidewall of the first seed column 2021, and a second protective layer is disposed. 2032 is coated on the first surface 2011 of the substrate exposed by the first seed column 2021. In one embodiment, the first protective layer 2031 and the second protective layer 2032 are formed by spin-on glass coating (SOG). The material of the first protective layer 2031 and the second protective layer 2032 may be a polymer (Polymer) based on Silsequioxane such as SiO ₂ , HSQ (Hydrogen Silesquioxane), and MSQ (Methylsequioxane).

Then, a first buffer layer 205 is simultaneously grown laterally and upwardly along the top surface of the plurality of first seed crystal columns 2021 by Epitaxial Lateral Overgrowth (ELOG), and in two adjacent At least one first hole 204 is formed between the seed column 2021, the substrate 201, and the first buffer layer 205. In the present embodiment, since the first protective layer 2031 covers the sidewall of the first seed column 2021, the directivity and spatial growth priority of the growth of the first buffer layer 205 can be effectively controlled. In this embodiment, the first buffer layer 205 can be an unintentionally doped layer or an undoped layer, or an n-type doped layer.

Thereafter, a plurality of second seed columns 2061 are formed on the first buffer layer 205, and a third protective layer 2071 is coated on the sidewall of the first seed column 2021, and a fourth protective layer 2072 is coated between the phases. The first seed column 2021 is exposed on the first surface 2051 of the first buffer layer. In one embodiment, the first protective layer 2031, the second protective layer 2032, the third protective layer 2071, and the fourth protective layer 2072 are formed by spin-on glass coating (SOG), and the material may be SiO. ₂ , HSQ (Hydrogen Silesquioxane) and MSQ (Methylsequioxane) and other polymers based on Silsequioxane (Polymer).

Thereafter, the top surface of the plurality of second seed crystal columns 2061 is laterally epitaxially formed. The method of Epitaxial Lateral Overgrowth (ELOG) simultaneously grows a second buffer layer 209 laterally and upwardly, and forms between two adjacent second seed column 2061, the first buffer layer 205 and the second buffer layer 209. At least one second hole 208. In the present embodiment, since the third protective layer 2071 covers the sidewall of the second seed column 2061, the directivity and spatial growth priority of the growth of the second buffer layer 209 can be effectively controlled. In this embodiment, the second buffer layer 209 can be an unintentionally doped layer or an undoped layer, or an n-type doped layer.

In an embodiment, the width of the first hole 204 and the second hole 208 may be between 50 nm to 600 nm, or 50 nm to 500 nm, or 50 nm to 400 nm, or 50 nm to 300 nm, or 50 nm to 200 nm, or 50 nm to 100 nm. The height of the first hole 204 and the second hole 208 may be between 0.5 μm and 2 μm, or 0.5 μm to 1.8 μm, or 0.5 μm to 1.6 μm, or 0.5 μm to 1.4 μm, or 0.5 μm to 1.2 μm, or 0.5 μm. ~1μm, or 0.5μm~0.8μm. In addition, in an embodiment, the first hole 204 and the second hole 208 may respectively have an aspect ratio (ratio of height to width) of 1/5~3, or 1/5~2, or 1/5. ~1, or 1/5~1/2, or 1/5~1/3, or 1/5~1/4.

In one embodiment, the volume of the first hole 204 is almost equal to the second hole 208. In another embodiment, the first hole 204 has a larger volume than the second hole 208.

In an embodiment, a plurality of first holes 204 may be formed between two adjacent first seed columns 2021 and the substrate 201. In another embodiment, since the plurality of first seed columns 2021 can be a regular array structure, the plurality of first holes 204 can also be a regular array structure. In another embodiment, the plurality of first holes 204 may be a single first hole, or the separate first holes may be coupled to each other to form one or a plurality of mesh first holes.

The average width W _{x of} the plurality of first holes 204 may be between 50 nm and 600 nm, or 50 nm to 500 nm, or 50 nm to 400 nm, or 50 nm to 300 nm, or 50 nm to 200 nm, or 50 nm to 100 nm. The average height H _{x of} the plurality of first holes 204 may be between 0.5 μm and 2 μm, or 0.5 μm to 1.8 μm, or 0.5 μm to 1.6 μm, or 0.5 μm to 1.4 μm, or 0.5 μm to 1.2 μm, or 0.5. Mm~1μm, or 0.5μm~0.8μm. In an embodiment, the average spacing of the plurality of first holes 204 may be between 10 nm and 1.5 μm, or 30 nm to 1.5 μm, or 50 nm to 1.5 μm, 80 nm to 1.5 μm, or 1 μm to 1.5 μm, or 1.2 μm. ~1.5μm. In addition, in an embodiment, the plurality of first holes 204 may have an average aspect ratio (the ratio of the average height to the average width) is between 1/5 and 3, or 1/5 to 2, or 1/5. ~1, or 1/5~1/2, or 1/5~1/3, or 1/5~1/4. The porosity Φ formed by the plurality of first holes 204 is defined as the total volume V _V of the first hole 204 divided by the overall volume. Wherein the overall volume V _T is the total volume of the first hole 204 plus the volume of the first seed column 2021. In this embodiment, the porosity Φ may be between 5% and 90%, or 10% to 90%, or 20% to 90%, or 30% to 90%, or 40% to 90%, or 50%. 90%, or 60%-90%, or 70%-90%, or 80%-90%.

In an embodiment, the two adjacent second seed column 2061 and the second buffer layer 205 A plurality of second holes 208 may be formed therebetween. In another embodiment, since the plurality of second seed columns 2061 can be a regular array structure, the plurality of second holes 208 can also be a regular array structure. In another embodiment, the plurality of second holes 208 can be a single second hole, or the separate second holes can be joined to each other to form one or a plurality of mesh second holes.

The average width W _{x of} the plurality of second holes 208 may be between 50 nm and 600 nm, or 50 nm to 500 nm, or 50 nm to 400 nm, or 50 nm to 300 nm, or 50 nm to 200 nm, or 50 nm to 100 nm. The average height H _{x of} the plurality of second holes 208 may be between 0.5 μm and 2 μm, or 0.5 μm to 1.8 μm, or 0.5 μm to 1.6 μm, or 0.5 μm to 1.4 μm, or 0.5 μm to 1.2 μm, or 0.5. Mm~1μm, or 0.5μm~0.8μm. In an embodiment, the average spacing of the plurality of second holes 208 may be between 10 nm and 1.5 μm, or 30 nm to 1.5 μm, or 50 nm to 1.5 μm, 80 nm to 1.5 μm, or 1 μm to 1.5 μm, or 1.2 μm. ~1.5μm. In addition, in an embodiment, the plurality of second holes 208 may have an average aspect ratio (the ratio of the average height to the average width) is between 1/5 and 3, or 1/5 to 2, or 1/5. ~1, or 1/5~1/2, or 1/5~1/3, or 1/5~1/4. The porosity Φ formed by the plurality of second holes 208 is defined as the total volume V _V of the second holes 208 divided by the overall volume. Wherein the overall volume V _T is the total volume of the second hole 208 plus the volume of the second seed column 2061. In this embodiment, the porosity Φ may be between 5% and 90%, or 10% to 90%, or 20% to 90%, or 30% to 90%, or 40% to 90%, or 50%. 90%, or 60%-90%, or 70%-90%, or 80%-90%.

After the first semiconductor layer 210, an active layer 211 and a second semiconductor layer 212 are grown on the second buffer layer 209, a portion of the active layer 211 and a second semiconductor layer 212 are etched to expose a portion of the first semiconductor. After the layer 210, two electrodes 213, 214 are formed on the first semiconductor layer 210 and the second semiconductor layer 212 to form a photovoltaic element 200. The materials of the electrodes 213 and 214 may be selected from the group consisting of chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or silver (Ag). A single composition of a metallic material or a combination of alloys or laminates.

In this embodiment, the first hole 204 and the second hole 208 are hollow structures. The first hole 204 and the second hole 208 have a refractive index and can serve as an air lens. When the light travels in the photovoltaic element 200 to the first hole 204 and the second hole 208, the first hole 204 and the second hole 208 are formed. The difference in refractive index between the inner and outer materials (for example, the refractive index of the buffer layer is between about 2 and 3, and the refractive index of air is 1), the light will change direction at 204 and the second hole 208, and the light extraction is increased. effectiveness. In addition, 204 and second holes 208 can also serve as a scattering center to change the direction of travel of the photons and reduce total reflection. This effect can be further increased by the increase in density of 204 and second holes 208.

In another embodiment, the second buffer layer 209 and the first semiconductor layer 210 are selectively formed into a third seed column (not shown) and a third buffer layer according to the same process of the above embodiment. Not shown), and at least a third hole (not shown) is formed between the second buffer layer 209 and the third seed column (not shown) to further increase the above-described effect of increasing light extraction efficiency. In one embodiment, the first hole 204, the second hole 208, and the third hole (not shown) have substantially the same volume. In another embodiment, the first hole 204 has a larger volume than the second hole 208, and the second hole 208 has a larger volume than the third hole (not shown).

In another embodiment, a fourth hole (not shown), a fifth hole (not shown), and the like may be sequentially formed according to the same process of the above embodiment, and the volume of the first hole to the fifth hole may gradually become smaller. .

As illustrated in FIGS. 3A to 3F, the above-described first embodiment will be described in more detail. A method of etching the first semiconductor layer 102 into a plurality of first semiconductor pillars 1021. As shown in FIG. 3A, a first seed layer 302 is grown on the first surface 3011 of the substrate 301.

Thereafter, as shown in FIG. 3B, an anti-etching layer 303 is grown on the first semiconductor layer 302, and the material may be cerium oxide (SiO ₂ ). A thin film metal layer 304 is further formed on the anti-etching layer 303. The thin film metal layer 304 may be made of nickel, and the thin film metal layer 304 has a thickness of between 500 and 2000 nm.

Thereafter, as shown in FIG. 3C, the thin film metal layer 304 is subjected to heat treatment at a temperature of 750 to 900 ° C to form the thin film metal layer 304 into a plurality of regular-sized metal particles 3041 which are regularly or irregularly arranged.

As shown in FIG. 3D, the plurality of nano-sized metal particles 3041 are used as a mask to perform an anisotropic etching on the etching layer 303, for example, an inductive coupling plasma (ICP), which is resistant to etching. Layer 303 forms a plurality of nano anti-etch columns 3031.

As shown in FIGS. 3E to 3F, the acid etching was performed by immersing in a nitric acid etching solution at 100 ° C to remove residual metal particles 3041. The first seed layer 302 is then dry etched using the plurality of anti-etch columns 3031 as a mask to form a plurality of first seed columns 3021. Finally, a plurality of anti-etch columns 3031 are removed.

Specifically, the photovoltaic elements 100 and 200 are a light emitting diode (LED), a photodiode, a photoresistor, a laser, an infrared emitter, and an organic light emitting diode. At least one of an organic light-emitting diode and a solar cell.

The substrates 101 and 201 are a growth and bearing foundation. The candidate materials include but are not limited to germanium (Ge), gallium arsenide (GaAs), indium phosphate (InP), sapphire (Sapphire), tantalum carbide (SiC), germanium (Si), lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), metals, glass, composites, diamonds, CVD diamonds, and diamond-like carbon (DLC), Spinel (MgAl ₂ O ₄ ), alumina (Al ₂ O ₃ ), cerium oxide (SiO _X ), and lithium gallate (LiGaO ₂ ).

The first semiconductor layers 106, 210 and the second semiconductor layers 108, 212 are different in electrical, polar or dopants of at least two of the two, or are respectively used to provide electrons The semiconductor material of the hole and the single hole or the plurality of layers ("multilayer" means two or more layers, the same below), and the electrical selection may be a combination of at least two of p type, n type, and i type. . The active layers 107, 211 are located between the first semiconductor layers 106, 210 and the second semiconductor layers 108, 212, and are regions where electrical energy and light energy may be converted or induced to be converted. Those who convert or induce light energy are such as light-emitting diodes, liquid crystal displays, and organic light-emitting diodes; those that convert or induce light energy are such as solar cells and photodiodes. The first seed layer 102, 202, the first buffer layer 105, 205, the second seed layer 206, the second buffer layer 209, the first semiconductor layer 106, 210, the active layers 107, 211 and the second semiconductor layer 108 212 includes one or more elements selected from the group consisting of gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P), nitrogen (N), and cerium (Si).

The photovoltaic element 100, 200 according to another embodiment of the present invention is a light-emitting two In polar bodies, the luminescence spectrum can be adjusted by changing the physical or chemical elements of a single layer or multiple layers of a semiconductor. Commonly used materials are such as aluminum gallium indium phosphide (AlGaInP) series, aluminum gallium indium nitride (AlGaInN) series, zinc oxide (ZnO) series and the like. The structure of the conversion unit is: single heterostructure (SH), double heterostructure (DH), double-side double heterostructure (DDH), or multi-quant μm Well; MQW). Furthermore, adjusting the logarithm of the quantum well can also change the wavelength of the illumination.

In an embodiment of the invention, the first seed layer 102, 202 and the substrate 101, 201 A transition layer (not shown) may optionally be included. This transition layer is between the two material systems, "transition" the material system of the substrate to the material system of the semiconductor system. For the structure of the light-emitting diode, on the one hand, a transition layer such as a buffer layer or the like is used to reduce the material layer of the lattice mismatch between the two materials. On the other hand, the transition layer may also be a single layer, a plurality of layers or a structure for combining two materials or two separate structures, such as organic materials, inorganic materials, metals, and semiconductors; The selected structure is: reflective layer, thermally conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment layer, bonding layer, wavelength Conversion layer, mechanical fixing structure, etc.

A contact layer (not shown) is more selectively formed on the second semiconductor layers 108, 212. The contact layer is disposed on a side of the second semiconductor layer 108, 212 away from the active layers 107, 211. In particular, the contact layer can be an optical layer, an electrical layer, or a combination of both. Optical layer system To change the electromagnetic radiation or light from or into the active layers 107, 211. As used herein, "change" means changing at least one optical property of electromagnetic radiation or light, including but not limited to frequency, wavelength, intensity, flux, efficiency, color temperature, rendering index, light field. (light field), and angle of view. The electrical layer system may change or change the value, density, distribution of at least one of voltage, resistance, current, and capacitance between opposite sides of any one of the contact layers. The constituent material of the contact layer comprises an oxide, a conductive oxide, a transparent oxide, an oxide having a transmittance of 50% or more, a metal, a relatively light-transmissive metal, a metal having a transmittance of 50% or more, an organic substance, At least one of an inorganic substance, a phosphor, a phosphor, a ceramic, a semiconductor, a doped semiconductor, and an undoped semiconductor. In some applications, the material of the contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. In the case of a relatively light-transmissive metal, the thickness is about 0.005 μm to 0.6 μm.

The above figures and descriptions are only corresponding to specific embodiments, however, the elements, embodiments, design criteria, and technical principles described or disclosed in the various embodiments are inconsistent, contradictory, or difficult to implement together. In addition, we may use any reference, exchange, collocation, coordination, or merger as required.

Although the invention has been described above, it is not intended to limit the scope of the invention, the order of implementation, or the materials and process methods used. Various modifications and variations of the present invention are possible without departing from the spirit and scope of the invention.

Claims (10)

A photovoltaic element comprising: a substrate having a surface and having a normal direction perpendicular to the surface; a first semiconductor layer comprising a plurality of irregular pore structures on the surface of the substrate; a protective layer, Located on a sidewall of the plurality of holes; and a buffer layer over the first semiconductor layer. The photovoltaic element according to claim 1, wherein the pore structures are independent of each other; or may be connected to each other; or form one or a plurality of networked first pore groups; or in a regular array, and the pore structures are averaged The spacing is between 100Å and 1.5μm and the porosity is between 5% and 90%. The photovoltaic device according to claim 1, further comprising a second semiconductor layer, an active layer and a third semiconductor layer formed on the buffer layer. The photovoltaic device of claim 1, wherein the buffer layer is an unintentionally doped layer or an undoped layer or an n-type doped layer. The photovoltaic element according to claim 1, wherein the material of the protective layer is SiO ₂ , HSQ (Hydrogen Silesquioxane) or MSQ (Methylsequioxane) or the like (Siliequioxane) based polymer (Polymer). A method of fabricating a photovoltaic element, comprising the steps of: providing a substrate having a surface and having a normal direction perpendicular to the surface; Forming a first semiconductor layer on the surface of the substrate; patterning the first semiconductor layer to form a plurality of holes; providing a protective layer over the sidewall of the hole structure; and forming a buffer layer thereon Above the first semiconductor layer. The method of claim 6, wherein the patterning the first semiconductor layer comprises: forming an anti-etching layer on the first seed layer; forming a thin film metal layer on the anti-etching layer; heating the The thin film metal layer is formed into a plurality of metal particles; the plurality of metal particles are used as a mask, the anti-etching layer is anisotropically etched to form a pattern; the plurality of metal particles are removed; and the patterned resist is used The etching layer acts as a mask to dry etch the first seed layer. The method of claim 6, wherein the pore structures are independent of each other; or may be connected to each other; or form one or a plurality of networked first pore groups; or in a regular array, and the average spacing of the pore structures It is between 100Å and 1.5μm and the porosity is between 5% and 90%. The method of claim 6, further comprising forming a second semiconductor layer, an active layer, and a third semiconductor layer over the buffer layer. The method of claim 6, wherein the protective layer is formed by spin-on glass coating (SOG).