JP2012094752A - Photoelectric element and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a photoelectric element and a method of manufacturing the same.SOLUTION: The photoelectric element comprises a substrate having a surface and a normal direction perpendicular to the surface, a first semiconductor layer located on the surface of the substrate and comes into contact therewith, and at least one cavity structure located between the first semiconductor layer and the surface of the substrate. The cavity structure has a width and a height, where the width is the maximum dimension of the cavity structure in the direction parallel with the surface, and the height is the maximum dimension of the cavity structure in the direction parallel with the normal direction and the height is less than the width.

Description

  The present invention relates to a photoelectric device having a cavity structure formed between a semiconductor and a substrate.

  Among semiconductor elements, a light emitting diode is a light source used in a wide range. Compared with conventional incandescent bulbs or fluorescent lamp tubes, light-emitting diodes have characteristics of power saving and long service life, so they gradually replace conventional light sources, such as traffic signal lights, backlight modules, street lamp lighting and medical equipment, etc. Applied to various fields such as industry.

  With the application and development of light emitting diode light sources, the demand for brightness has also increased. At present, in this field, increasing luminous efficiency and increasing luminance has become an important issue to be worked on together.

  The present invention provides a photoelectric device and a manufacturing method thereof.

  The photoelectric element of the present invention, a substrate having a surface and a normal direction perpendicular to the surface, a first semiconductor layer located on the surface of the substrate and in contact with the surface, and between the first semiconductor layer and the surface of the substrate And at least one cavity structure having a width and a height, the width being a maximum dimension in a direction parallel to the surface of the cavity structure, the height being a method in the cavity structure It is the maximum dimension in the direction parallel to the line direction, and the height is smaller than the width.

  A method for manufacturing a photoelectric device according to the present invention, comprising a surface and a substrate having a normal direction perpendicular to the surface, forming a first semiconductor layer on the surface of the substrate, patterning the first semiconductor layer, and Forming at least one cavity structure overlying the patterned first semiconductor layer and forming at least one cavity structure located between the second semiconductor layer and the surface of the substrate. Has a width and a height, where the width is the maximum dimension in the direction parallel to the surface of the cavity structure, the height is the maximum dimension in the direction parallel to the normal direction in the cavity structure, and the height is less than the width .

It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is a figure which shows the manufacturing process of the photoelectric element by the Example of this invention. It is sectional drawing of the photoelectric semiconductor element of this invention. It is sectional drawing of the photoelectric semiconductor element of this invention. It is sectional drawing of the photoelectric semiconductor element of this invention. It is sectional drawing of the photoelectric semiconductor element of this invention. FIG. 3 is a view of a cavity formed by an embodiment of the present invention by a scanning electron microscope. FIG. 3 is a view of a cavity formed by an embodiment of the present invention by a scanning electron microscope. FIG. 3 is a view of a cavity formed by an embodiment of the present invention by a scanning electron microscope.

  To more fully and fully describe the present invention, it will be described as follows with reference to FIGS. 1A to 4C.

  With reference to FIGS. 1A to 1F, a method for manufacturing a photoelectric device according to the first embodiment of the present invention will be briefly described.

  As shown in FIG. 1A, a first semiconductor layer 102 is grown on a first surface 1011 of a substrate 101. This substrate has a normal direction N.

  Subsequently, as shown in FIG. 1B, the first semiconductor layer 102 is etched to form a plurality of first semiconductor pillars 1021 on the first surface 1011 of the substrate 101. The side walls of the plurality of first semiconductor pillars 1021 and the first surface 1011 of the substrate 101 are not perpendicular. In this embodiment, both side walls of the first semiconductor pillar 1021 and the first surface 1011 of the substrate 101 form angles α1 and β1, where α1 is in the range of 20 ° to 75 °, and β1 is in the range of 20 ° to 75 °. Is in range. In the embodiment, the average width of the first semiconductor pillar 1021 is in the range of 0.5 μm to 10 μm, and the average interval is in the range of 0.5 μm to 10 μm.

  Subsequently, as shown in FIG. 1C, a second semiconductor layer 1022 is grown on the first surface of the substrate. The second semiconductor layer 1022 is grown by an epitaxial lateral growth (ELOG) method. The second semiconductor layer 1022 is grown, and at least one first cavity 1031 is formed between two adjacent first semiconductor pillars 1021 and the first surface 1011 of the substrate 101. As shown in FIG. 1D, in the normal direction N of the substrate, the entire cross section of the first cavity 1031 has a bell shape, and has a width W and a height H, and the width W is parallel to the surface. The height H is the maximum dimension of the first cavity 1031 in the direction parallel to the normal, and the height H is smaller than the width W. The width W is in the range of 0.5 μm to 10 μm, 1 μm to 10 μm, 2 μm to 10 μm, 3 μm to 10 μm, 4 μm to 10 μm, 5 μm to 10 μm, 6 μm to 10 μm, 7 μm to 10 μm, 8 μm to 10 μm, or 9 μm to 10 μm. In another embodiment, the ratio of height H to width W of the first cavity 1031 is not greater than 2/3.

In another embodiment, a plurality of first cavities 1031 can be formed. In an embodiment, the cavities are interconnected to form one or more mesh cavities. In addition, since the plurality of first semiconductor pillars 1021 has a regular array structure, the plurality of first cavities 1031 may also be formed in a regular array structure. Note that the average height Hx of the plurality of first cavities 1031 is smaller than the average width Wx. The average width Wx is in the range of 0.5 μm to 10 μm, 1 μm to 10 μm, 2 μm to 10 μm, 3 μm to 10 μm, 4 μm to 10 μm, 5 μm to 10 μm, 6 μm to 10 μm, 7 μm to 10 μm, 8 μm to 10 μm, or 9 μm to 10 μm. . In the embodiment, the ratio between the average height Hx and the average width Wx of the plurality of first cavities 1031 is not larger than 2/3. In the embodiment, the average interval between the plurality of first cavities 1031 is 0.5 μm to 10 μm, 1 μm to 10 μm, 2 μm to 10 μm, 3 μm to 10 μm, 4 μm to 10 μm, 5 μm to 10 μm, 6 μm to 10 μm, 7 μm to 10 μm. , 8 μm to 10 μm or 9 μm to 10 μm. Said plurality of cavities porosity formed by a first cavity 1031 Ф (porosity), the value divided by the total volume _{V T} of the total volume Vv of the first cavity

で定義され、全体体積Ｖ_Ｔは第一空洞の総体積に第二半導体層の体積を加えた値である。本実施例において、空洞隙率Фは、５％〜９０％、１０％〜９０％、３０％〜９０％、４０％〜９０％、５０％〜９０％、６０％〜９０％、７０％〜９０％又は８０％〜９０％の範囲にある。

The total volume V _T is a value obtained by adding the volume of the second semiconductor layer to the total volume of the first cavity. In this example, the void ratio is 5% to 90%, 10% to 90%, 30% to 90%, 40% to 90%, 50% to 90%, 60% to 90%, 70% to It is in the range of 90% or 80% to 90%.

  Subsequently, as illustrated in FIG. 1E, the main dynamic layer 104 and the third semiconductor layer 105 are grown on the upper surface of the second semiconductor layer 1022.

  Finally, as shown in FIG. 1F, a part of the main dynamic layer 104 and the third semiconductor layer 105 is etched to expose a part of the second semiconductor layer 1022, and the second semiconductor layer 1022 and the second semiconductor layer 1022 Two electrodes 108 and 109 are formed as the photoelectric element 100 on the three semiconductor layers 105. The electrodes 108 and 109 are made of a metal such as chromium (Cr), titanium (Ti), nickel (Ni), platinum (Pt), copper (Cu), gold (Au), aluminum (Al) or silver (Ag). It is configured by selecting from materials.

  In this embodiment, the first cavity 1031 has a hollow structure defined in the process. The first cavity 1031 has a refractive index and is applied as an air lens. When the light beam enters the first cavity 1031 of the photoelectric device 100, the refractive index difference between the inside of the first cavity 1031 and the external material (for example, the refractive index of the semiconductor layer is between about 2 to 3, The refractive index is about 1), and the light beam is emitted from the photoelectric element in the first cavity 1031 with the emission direction changed. Thereby, the light extraction rate is increased. On the other hand, the first cavity 1031 can be used as a scattering center to change the emission direction of photons and reduce total reflection. The above effect can be further increased by increasing the density of the cavities.

Specifically, the photoelectric device 100 includes a light emitting diode (LED), a photodiode, a photoresistor, a laser, an infrared emitter, an organic light-emitting diode, and an organic light-emitting diode. Including at least one of the solar cells. The substrate 101 is the basis for growth and / or mounting and can be selected from a conductive or non-conductive substrate, a translucent substrate or a non-translucent substrate. The material of the conductive substrate is germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO), One of gallium nitride (GaN), aluminum nitride (AlN), and metal. The material of the transparent substrate is sapphire (Sapphire), lithium aluminate (LiAlO ₂ ), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), metal, glass, diamond, CVD diamond, diamond-like carbon (Diamond-Like Carbon; DLC), spinel (spinel, MgAl ₂ O ₄ ), alumina (Al ₂ O ₃ ), silicon oxide (SiOx), and lithium gallate (LiGaO ₂ ).

  The first semiconductor layer 102, the second semiconductor layer 1022, and the third semiconductor layer 105 are different from each other in at least two portions of electrical characteristics, polarities, or impurities, or are each a single semiconductor material that provides electrons and holes. A layer or a multilayer (“multilayer” means two or more layers, the same applies to the following), and electrical characteristics are selected from a combination of at least one of p-type, n-type and i-type it can. The main dynamic layer 104 is located between the second semiconductor layer 1022 and the third semiconductor layer 105, and is an area that induces conversion of electrical energy and light energy. There are a light-emitting diode, a liquid crystal display, and an organic light-emitting diode that convert or induce electrical energy into light energy, and a solar cell and a photodiode that convert or induce light energy into electrical energy. The first semiconductor layer 102, the second semiconductor layer 1022, the main dynamic layer 104, and the third semiconductor layer 105 are made of gallium (Ga), aluminum (Al), indium (In), arsenic (As), phosphorus (P ), One or more substances selected from the group consisting of nitrogen (N) and silicon (Si).

  The photoelectric device 100 according to another embodiment of the present invention is a light emitting diode, and the frequency spectrum of the light emission can be adjusted by changing a physical or chemical element of a semiconductor single layer or a multilayer. Usually, materials such as aluminum gallium indium phosphide (AlGaInP), aluminum gallium indium nitride (AlGaInN), and zinc oxide (ZnO) are used. The structure of the primary dynamic layer 104 may be, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (double-heterostructureD), or a double-side double heterostructure (well) multi-quantum well (MQW). Furthermore, the wavelength of light emission can be changed by adjusting the logarithm of the quantum well.

  In an embodiment of the present invention, a transition layer (not shown) may be selectively included between the first semiconductor layer 102 and the substrate 101. This transition layer is located between the two types of material systems to allow the substrate material system to “transition” to the semiconductor system material system. In the structure of a light emitting diode, the transition layer is a material layer that reduces the degree of lattice mismatch between two materials, such as a buffer layer. In addition, the transition layer may be a single layer or a multilayer structure that combines two kinds of materials or two separated structures, and the material is selected from organic materials, inorganic materials, metals, semiconductors, etc., and the structure is a reflective layer, a heat conduction layer. , Conductive layer, ohmic contact layer, strain resistance layer, stress release layer, stress adjustment layer, bonding layer, stress adjustment layer, mechanical fixing structure, etc. You can choose from.

  A contact layer (not shown) can be further selectively formed on the third semiconductor layer 105. The contact layer is provided on the side of the third semiconductor layer 105 away from the main dynamic layer 104. Specifically, the contact layer is an optical layer, an electrical layer, or a combination of the two. The optical layer modifies electromagnetic radiation or light emanating from the main dynamic layer 104 or electromagnetic radiation or light entering the main active layer 104. The term “change” as used herein means changing at least one optical characteristic of electromagnetic radiation or light, and the above characteristics include frequency, wavelength, intensity, flux, efficiency, color temperature, and rendering index. , Light field, and angle of view, but are not limited to these. The electrical layer causes a change or a tendency to change in the numerical value, density, and distribution of at least one of voltage, resistance, current, and capacitor between any pair of relative sides of the contact layer. As a material constituting the contact layer, an oxide, an electrically conductive oxide, a transparent oxide, an oxide having a transmittance of 50% or more, a metal, a relative light-transmitting metal, a transmittance of 50% or more It includes at least one of a metal, an organic substance, an inorganic substance, a fluorescent substance, a phosphorescent substance, ceramics, a semiconductor, a semiconductor containing impurities, and a semiconductor containing no impurities. Depending on the application, the material of the contact layer is at least one of indium tin oxide, cadmium oxide-tin oxide, antimony tin oxide, indium-zinc oxide, zinc-aluminum oxide and zinc tin oxide. Can be. In the case of the opposite translucent metal, the thickness is about 0.005 μm to 0.6 μm.

A method for etching the first semiconductor layer 102 described in the first embodiment into the plurality of first semiconductor pillars 1021 will be described in more detail with reference to FIGS. 2A to 2F. Referring to FIG. 2A, the first semiconductor layer 102 is grown on the first surface 1011 of the substrate 101. Thereafter, an etching resist layer 106 is grown on the first semiconductor layer 102, and the material thereof is silica (SiO ₂ ).

  Next, referring to FIG. 2C to FIG. 2D, a discontinuous photoresist layer 107 is formed on the upper surface of the etching resist layer 106, and the etching resist layer 106 is formed through a photomask in a photolithography process (Photolithography). Development is performed to form a patterned etching resist layer 1061. In this embodiment, the patterned etching resist layer 1061 is a regular array pattern, an average width h is 0.5 μm to 10 μm, and an average interval is 0.5 μm to 10 μm. .

  Referring to FIG. 2E, anisotropic etching is performed on the first semiconductor layer 102 through the patterned etching resist layer 1061 described above. For example, the first semiconductor layer 102 exposed by inductively coupled plasma (ICP) etching is etched to form a plurality of first semiconductor pillars 1021. In an Example, the average width | variety of this 1st semiconductor pillar 1021 is 0.5 micrometer-10 micrometers, and an average space | interval is 0.5 micrometer-10 micrometers.

  Lastly, referring to FIG. 2F, a single or mixed solution such as oxalic acid, potassium hydroxide, phosphoric acid, or sulfuric acid solution is used as an etchant, and is localized with respect to the plurality of first semiconductor pillars 1021 described above. An anisotropic wet etching (wet etching) is performed. When anisotropic etching is used, the sidewalls of the plurality of first semiconductor pillars 1021 and the first surface 1011 of the substrate 101 are not perpendicular to each other. In brief, the etch rate of the etchant for different crystal structures or crystal qualities can be used to define the sidewall structure and corresponding size of the first semiconductor pillar 1021. In the embodiment, both side walls of the first semiconductor pillar 1021 and the first surface 1011 of the substrate 101 form an angle of -α1 and β1, α1 is in the range of 20 ° to 75 °, and β1 is in the range of 20 ° to 75 °. It is in the range of °.

  Another embodiment of the present invention will be described with reference to FIGS. 3A to 3D. In this embodiment, cavities having different shapes are formed by adjusting the etching method shown in FIGS. 2E to 2F. The other steps are the same as in the above embodiment, and the description thereof is omitted here.

  Referring to FIG. 3A, the plurality of first semiconductor pillars 1021 includes a first portion 10211 whose sidewall is perpendicular to the substrate surface and a second portion 10212 whose sidewall is not perpendicular to the substrate 101. In this embodiment, both side walls of the second portion 10212 of the first semiconductor pillar and the first surface 1011 of the substrate 101 form an angle of −α2 and β2, α2 is in the range of 20 ° to 75 °, and β2 Is in the range of 20 ° to 75 °. The average width of the first semiconductor pillar 1021 is 0.5 μm to 10 μm, and the average interval is 0.5 μm to 10 μm.

  Next, referring to FIG. 3B, the second semiconductor layer 1022 is formed through the above-described process, and covers at least one second cavity 1032 and two adjacent first semiconductor pillars 1021 and the substrate 101.

Referring to FIGS. 3C to 3D, in the normal direction N of the substrate, the entire cross section of the second cavity 1032 is formed in the shape of a wizard's hat, and is formed in a substantially flat plate-like lower portion. 10321 and an upper portion 10322 formed in a substantially conical shape. The lower portion 10321 has a long side parallel to the surface of the substrate 101, and the entire cross section of the second cavity 1032 has a height H ₂ (the total height including the upper portion 10321 and the lower portion 10322) parallel to the normal direction. The height H ₂ is the maximum dimension parallel to the normal direction in the second cavity 1032, the lower part 10321 has a width W ₂ (long side width), and the width W ₂ is the lower part in the second cavity. This is the maximum dimension in the direction parallel to the surface of 10321. The height _{H 2} of the above smaller than the width _{W 2.} The width W2 is in the range of 0.5 μm to 10 μm, 1 μm to 10 μm, ₂ μm to 10 μm, 3 μm to 10 μm, 4 μm to 10 μm, 5 μm to 10 μm, 6 μm to 10 μm, 7 μm to 10 μm, 8 μm to 10 μm, or 9 μm to 10 μm. In another embodiment, the ratio of the height H ₂ to the width W ₂ is not greater than 2/3. In this embodiment, the upper section 10322 of the entire cross section is formed in a conical shape. That is, the width of the bottom surface close to the substrate gradually decreases in the direction away from the substrate, the apexes are formed in sharp corners, arcs, and balls, and the upper portion 10322 is located in the lower portion 10321 when viewed from above.

  In another embodiment, referring to FIG. 3D, two long edges of the lower portion 10321 and the surface of the substrate 101 form a depression angle θ, where θ is in the range of 20 ° to 75 °.

In another embodiment, a plurality of second cavities 1032 are formed between two adjacent first semiconductor pillars 1021 and the substrate 101. In an embodiment, the cavities are interconnected to form one or more mesh cavities. In addition, since the plurality of first semiconductor pillars 1021 has a regular array structure, the plurality of second cavities 1032 may also be formed in a regular array structure. The average height H ₂ x of the plurality of second cavities 1032 is smaller than the average width W ₂ x. The average width W ₂ x is in the range of 0.5 μm to 10 μm, 1 μm to 10 μm, 2 μm to 10 μm, 3 μm to 10 μm, 4 μm to 10 μm, 5 μm to 10 μm, 6 μm to 10 μm, 7 μm to 10 μm, 8 μm to 10 μm, or 9 μm to 10 μm. It is in. In the embodiment, the ratio of the average height H ₂ x and the average width W ₂ x of the second cavity 1032 is not larger than 2/3. In the embodiment, the average interval between the second cavities 1032 is 0.5 μm to 10 μm, 1 μm to 10 μm, 2 μm to 10 μm, 3 μm to 10 μm, 4 μm to 10 μm, 5 μm to 10 μm, 6 μm to 10 μm, 7 μm to 10 μm, 8 μm. 10 μm or 9 μm to 10 μm. The above plurality of second cavity 1032 void porosity Ф formed by (porosity), the value divided by the second overall total volume Vv of the cavity volume _{V T}

で定義され、全体体積Ｖ_Ｔは第二空洞の総体積に第二半導体層の体積を加えた値である。本実施例において、空洞隙率Фは、５％〜９０％、１０％〜９０％、３０％〜９０％、４０％〜９０％、５０％〜９０％、６０％〜９０％、７０％〜９０％又は８０％〜９０％の範囲にある。

The total volume V _T is a value obtained by adding the volume of the second semiconductor layer to the total volume of the second cavity. In this example, the void ratio is 5% to 90%, 10% to 90%, 30% to 90%, 40% to 90%, 50% to 90%, 60% to 90%, 70% to It is in the range of 90% or 80% to 90%.

  4A to 4C are views of a cavity formed according to an embodiment of the present invention by a scanning electron microscope (SEM). Referring to FIG. 4A, the top vertex of the cavity is formed into a sharp corner. Referring to FIG. 4B, the top vertex of the cavity is formed in an arc shape. Referring to FIG. 4C, the cavities form a regular array.

  Although each of the above drawings and descriptions correspond to particular embodiments, those skilled in the art will clearly understand that the elements, implementations, design criteria and technical principles described or disclosed in each embodiment are mutually conflicting, contradictory or cannot be implemented together. Except in any case, it should be understood that it can be freely referenced, exchanged, combined, harmonized or merged as required.

  Although the present invention has been described as described above, the scope of the present invention, the order of execution, or the materials and process methods used are not limited by the above description. Various changes and modifications made to the invention still fall within the scope of the invention.

101 Substrate 102 First Semiconductor Layer 1031 First Cavity 1032 Second Cavity 104 Main Active Layer 1022 Second Semiconductor Layer 105 Third Semiconductor Layer 106 Etching Resist Layer 107 Photoresist Layer

Claims (13)

A photoelectric element,
A substrate having a surface and a normal direction perpendicular to the surface;
A first semiconductor layer located on the surface of the substrate and in contact with the surface;
Having at least one cavity structure located between the first semiconductor layer and the surface of the substrate;
The at least one cavity structure has a width and a height, wherein the width is a maximum dimension in a direction parallel to the surface of the cavity structure, and the height is a direction parallel to the normal direction of the cavity structure. The photoelectric device is characterized in that the height is smaller than the width.   2. The photoelectric device according to claim 1, wherein the shape of the entire cross section of the at least one cavity structure is one of a hanging bell or a wizard hat.   2. The photoelectric device according to claim 1, wherein the width is in a range of 0.5 μm to 10 μm, and a ratio of the height to the width is not larger than 2/3.   The photoelectric device has a plurality of the cavity structures, and the plurality of cavity structures are interconnected to form one or a plurality of mesh-like cavities, or the plurality of cavity structures form a regular array. 2. The photoelectric device according to claim 1, wherein an average interval between the plurality of cavity structures is in a range of 0.5 μm to 10 μm, and a void ratio is in a range of 5% to 90%.   The photoelectric device according to claim 1, further comprising a main dynamic layer and a second semiconductor layer formed on the first semiconductor layer.   The entire cross section of the hollow structure is formed in the shape of a wizard hat, and has a flat plate-like lower portion and a conical upper portion, and the upper apex is formed in a sharp square shape, an arc shape, or a ball shape, The photoelectric device according to claim 2, wherein when viewed from above, the upper portion is located in the lower portion.   The lower part has a long side, the long side is parallel to the surface of the substrate, the width of the long side is in the range of 0.5 μm to 10 μm, and / or two edges of the long side and the substrate The photoelectric device according to claim 6, wherein the surface forms a depression angle θ, and the θ angle is in a range of 20 ° to 75 °. A method of manufacturing a photoelectric element,
Providing a substrate having a surface and a normal direction perpendicular to the surface;
Forming a first semiconductor layer on the surface of the substrate;
Patterning the first semiconductor layer;
Forming a second semiconductor layer on the substrate to cover the patterned first semiconductor layer;
Forming at least one cavity structure located between the second semiconductor layer and the surface of the substrate, the at least one cavity structure having a width and a height, wherein the width is the cavity structure. Wherein the height is a maximum dimension in a direction parallel to the normal direction in the cavity structure, and the height is smaller than the width. Manufacturing method.   9. The method of manufacturing a photoelectric device according to claim 8, wherein the shape of the entire cross section of the at least one hollow structure is one of a hanging bell or a wizard hat.   9. The method of manufacturing a photoelectric device according to claim 8, wherein the width is in a range of 0.5 [mu] m to 10 [mu] m, and a ratio of the height to the width is not larger than 2/3.   The photoelectric device has a plurality of the cavity structures, and the plurality of cavity structures are interconnected to form one or a plurality of mesh-like cavities, or the plurality of cavity structures form a regular array. 9. The method of manufacturing a photoelectric device according to claim 8, wherein an average interval between the plurality of cavity structures is in a range of 0.5 [mu] m to 10 [mu] m, and a cavity porosity is in a range of 5% to 90%. .   The entire cross section of the hollow structure is formed in the shape of a wizard hat, and has a flat plate-like lower portion and a conical upper portion, and the upper apex is formed in a sharp square shape, an arc shape, or a ball shape, The method of claim 9, wherein the upper part is located in the lower part when viewed from the viewpoint.   The lower part has a long side, the long side is parallel to the surface of the substrate, the width of the long side is in the range of 0.5 μm to 10 μm, and / or two edges of the long side and the substrate The method for producing a photoelectric device according to claim 12, wherein the surface forms a depression angle θ, and the θ angle is in a range of 20 ° to 75 °.

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