TW201939767A - Optoelectronic device and method for manufacturing the same - Google Patents

Abstract

An optoelectronic device including a epitaxial stack including a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer; multiple boundaries exposing the first semiconductor layer, two adjacent boundaries of the multiple boundaries forming a corner of the first semiconductor layer; first parts of a first conductive type electrodes formed on the first semiconductor layer exposed by the multiple boundaries, wherein the first parts of a first conductive type electrodes are separated from each other, and not surrounded by the second semiconductor layer; a third electrode formed on the first parts of a first conductive type electrodes and the second semiconductor layer; and one or more fourth electrodes formed on the second semiconductor layer.

Description

Photoelectric element and manufacturing method thereof

The invention relates to a photovoltaic element, in particular to an electrode design of a photovoltaic element.

The light emitting principle of a light-emitting diode (LED) is to use the energy difference between electrons moving between an n-type semiconductor and a p-type semiconductor to release energy in the form of light. Such a light-emitting principle is different from an incandescent lamp The light emitting principle of heat generation, so the light emitting diode is called a cold light source. In addition, light-emitting diodes have the advantages of high durability, long life, light weight, and low power consumption. Therefore, the current lighting market has high hopes for light-emitting diodes and regards them as a new generation of lighting tools, which has gradually replaced traditional Light source, and is used in various fields, such as traffic signs, backlight modules, street lighting, medical equipment, etc.

FIG. 1 is a schematic diagram of a conventional light-emitting element structure. As shown in FIG. 1, the conventional light-emitting element 100 includes a transparent substrate 10, a semiconductor stack 12 on the transparent substrate 10, and at least one electrode 14 on the semiconductor. On the stack 12, the above-mentioned semiconductor stack 12 includes at least a first conductive type semiconductor layer 120, an active layer 122, and a second conductive type semiconductor layer 124 from top to bottom.

In addition, the above-mentioned light-emitting element 100 can be further combined with other elements to form a light-emitting apparatus. FIG. 2 is a schematic structural diagram of a conventional light emitting device. As shown in FIG. 2, a light emitting device 200 includes a sub-mount 20 having at least one circuit 202; at least one solder 22 is located on the sub-carrier. 20, the above-mentioned light-emitting element 100 is adhered and fixed on the sub-carrier 20 by the solder 22, and the substrate 10 of the light-emitting element 100 is electrically connected to the circuit 202 on the sub-carrier 20; and an electrical connection structure 24 The electrode 14 of the light-emitting element 100 is electrically connected to the circuit 202 on the sub-carrier 20. The above-mentioned sub-carrier 20 may be a lead frame or a large-sized mounting substrate to facilitate the circuit of the light-emitting device 200. Plan and improve its cooling effect.

A photovoltaic element includes: a first semiconductor layer having at least four boundaries, a first surface, and a second surface opposite to the first surface, wherein any two adjacent boundaries may form a corner; a second semiconductor A layer is formed on the first surface of the first semiconductor layer; a second electrical electrode is formed on the second semiconductor layer; and at least two first electrical electrodes are formed on the first surface of the first semiconductor layer , Wherein the at least two first electrical electrodes are separated from each other and form a design pattern.

The present invention discloses a light emitting element and a manufacturing method thereof. In order to make the description of the present invention more detailed and complete, please refer to the following description and cooperate with the diagrams of FIGS. 3A to 7.

3A and 3B are a top view and a side view of the photovoltaic element 300 according to the first embodiment of the present invention. FIG. 3B is a side view structural view in the direction A-B-C in FIG. 3A. The photovoltaic element 300 includes a substrate 30. The substrate 30 is not limited to a single material, and may be a composite substrate composed of a combination of a plurality of different materials. For example, the substrate 30 may include two first substrates (not shown) and a second substrate (not shown) bonded to each other.

An epitaxial stack 31 is formed on the substrate 30 by a conventional epitaxial growth process, including a first semiconductor layer 311 having a first surface 3111 and a second surface 3112 opposite to the first surface. An active layer 312 is formed. On the first surface 3111 of the first semiconductor layer 311, a second semiconductor layer 313 is formed on the active layer 312. Next, a part of the epitaxial stack is selectively removed by the yellow light lithography process technology to expose a portion of the first semiconductor layer 311 at the boundary of the photovoltaic device 300, and a trench S is formed in the photovoltaic device 300. In one embodiment, the trench S exposes a portion of the first semiconductor layer 311 and is surrounded by the second semiconductor layer 313. In one embodiment, the trench S has an elongated shape in the top view.

Next, a first insulating layer 341 is deposited on the surface of the epitaxial stack 31 of the photovoltaic element 300 and the sidewall of the trench S by a technique such as chemical vapor deposition (CVD) or physical vapor deposition (PVD).

Next, at least one first first electrical electrode 321 is formed on the first semiconductor layer 311 exposed on the border of the photovoltaic element 300. In one embodiment, the first first electrical electrode 321 is not surrounded by the second semiconductor layer 313, and a second first electrical electrode 322 is formed in the trench S. In this embodiment, the separated first first electrical electrodes 321 and the second first electrical electrodes 322 form an electrode design type of the first electrical electrodes.

In the embodiment of the present invention, the electrode design type may include the selection of the number of electrodes, the shape of the electrodes, and the positions of the electrodes, so as to improve the current spreading of the photovoltaic element near the boundary region. For example, the electrode design type of the first electrical electrode may include one or more first first electrical electrodes 321 and one or more second first electrical electrodes 322. The top view is surrounded by the second semiconductor layer 313 and is extended.

In one embodiment, the first semiconductor layer 311 of the photovoltaic element 300 has at least four borders, and two adjacent borders can form a corner, and there is no conductive structure crossing the borders. In this embodiment, the first first electrical electrodes 321 are formed at two corners on the same boundary of the photovoltaic element 300, are separated from each other and do not cross the boundary of the photovoltaic element 300.

In an embodiment, the projection of the first first electrical electrode 321 on the first semiconductor layer 311 may have a pattern, and the pattern may be a polygon, a circle, an ellipse, a semicircle, or a circle. Curved surface. The second first electrical electrode 322 may be linear, curved, mixed linear and curved, or may have at least one branch. In one embodiment, the second first electrical electrode 322 may have a head end and a tail end, and the head end has a width greater than a width of the tail end.

Next, a second electrical electrode 33 is formed on the second semiconductor layer 313. In one embodiment, a ratio of a projection area of the second electrical electrode 33 on the first semiconductor layer 311 to a surface area above the second semiconductor layer 313 is between 90% and 100%.

After that, a second insulating layer 342 may be formed on the first first electrical electrode 321, the second first electrical electrode 322, the second electrical electrode 33, and a portion of the first insulating layer 341. The second insulating layer 342 may have a first opening 3421 for electrically connecting the second electrical electrode 33 and a fourth electrode 36 to be formed later. The second insulating layer 342 may also have a second opening 3422 as a first opening. A first electrical electrode 321 is electrically connected to a third electrode 35 to be formed subsequently. In one embodiment, the first insulating layer 341 or the second insulating layer 342 can completely cover the first semiconductor layer 311 exposed above.

In one embodiment, the first insulating layer 341 or the second insulating layer 342 may be a transparent insulating layer. The material of the first insulating layer 341 or the second insulating layer 342 may be an oxide, a nitride, or a polymer. The oxide may include aluminum oxide (Al2O3), silicon oxide (SiO2), titanium dioxide (TiO2), Tantalum Pentoxide (Ta2O5) or aluminum oxide (AlOx); nitrides can include aluminum nitride (AlN), silicon nitride (SiNx); polymers can include polyimide or benzo rings Materials such as butane (benzocyclobutane, BCB) or a composite combination of the above. In one embodiment, the first insulation layer 341 or the second insulation layer 342 may be a distributed Bragg reflector structure.

Finally, a third electrode 35 is formed on the second insulating layer 342, the first first electrical electrode 321, and the second first electrical electrode 322, and is connected to the first first electrical electrode 321 and the second first electrical electrode. The electric electrode 322 is electrically connected; and a fourth electrode 36 is formed on the second insulating layer 342 and the second electric electrode 33 and is electrically connected to the second electric electrode 33. In an embodiment, the ratio of the projected area of the third electrode 35 to the fourth electrode 36 on the first semiconductor layer 311 is from 80 to 100% when viewed from above.

In one embodiment, the third electrode 35 may cover only part of the first first electrical electrode 321; in another embodiment, the third electrode 35 may not cover the first first electrical electrode 321 at all.

In one embodiment, the upper edge of the third electrode 35 to the upper edge of the substrate 30 has a height H1, and the upper edge of the fourth electrode 36 to the upper edge of the substrate 30 has a height H2, and H1 is substantially equal to H2. In one embodiment, the difference between H1 and H2 is less than 5-10%. By adjusting the difference between H1 and H2, it is possible to reduce the disconnection probability of subsequent formation of a flip-chip structure between the optoelectronic element 300 and the carrier board or circuit element, thereby increasing the product yield. In one embodiment, the boundary between the third electrode 35 and the boundary between the fourth electrode 36 has a minimum distance D1, and D1 is greater than 50 μm. In an embodiment, D1 may be 50-200 μm and 100-200 μm.

In an embodiment, the first first electrical electrode 321, the second first electrical electrode 322, the second electrical electrode 33, the third electrode 35, and the fourth electrode 36 may have a multilayer structure, and / or It includes a reflective layer (not shown), and can have a reflectivity of more than 80% for the light emitted from the active layer 312. In one embodiment, the first first electrical electrode 321, the second first electrical electrode 322, and the third electrode 35 can also be formed in the same process. In one embodiment, the light emitted by the photovoltaic element 300 may be reflected by the first first electrical electrode 321, the second first electrical electrode 322, the second electrical electrode 33, the third electrode 35, or the fourth electrode 36. The photovoltaic element 300 is separated from the substrate 30.

In order to achieve a certain conductivity, the material of the first first electrical electrode 321, the second first electrical electrode 322, the second electrical electrode 33, the third electrode 35, and the fourth electrode 36 may be, for example, metal, For example, gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), tin (Sn), etc., their alloys or Its laminated combination.

In an embodiment, a carrier board or a circuit element (not shown) may be provided, and a first carrier board electrode (not shown) is formed on the carrier board or circuit element by means of wire bonding or soldering, and a Second carrier electrode (not shown). The first carrier plate electrode and the second carrier plate electrode may form a flip-chip structure with the third electrode 35 and the fourth electrode 36 of the photovoltaic element 300.

In one embodiment, a first adjustment layer (not shown) may be formed between the first first electrical electrode 321, and / or the second first electrical electrode 322 and the third electrode 35, and the electrical Connected to the first first electrical electrode 321 and / or the second first electrical electrode 322 and the third electrode 35. In one embodiment, a second adjustment layer (not shown) may be formed between the second electrical electrode 33 and the fourth electrode 36 and electrically connected to the second electrical electrode 33 and the fourth electrode 36. In this embodiment, the first adjustment layer and the second adjustment layer may have a height, respectively, and because the formation positions of the first adjustment layer and the second adjustment layer make the heights of the first adjustment layer and the second adjustment layer affect The heights of the above H1 and H2. Therefore, by designing the formation height of the first adjustment layer and / or the second adjustment layer separately, the height difference between the above-mentioned H1 and H2 can be reduced, and the breakage of the subsequent formation of a flip-chip structure between the photovoltaic element 300 and the carrier board or circuit element can be reduced. Line probability, which in turn increases product yield. In one embodiment, the projection area of the first adjustment layer on the first semiconductor layer 311 is larger than the projection area of the third electrode 35 on the first semiconductor layer 311, or the projection of the second adjustment layer on the first semiconductor layer 311. The area is larger than the projected area of the fourth electrode 36 on the first semiconductor layer 311. In an embodiment, the material of the first adjustment layer or the second adjustment layer may be, for example, metal, such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), Platinum (Pt), nickel (Ni), titanium (Ti), tin (Sn), or the like, an alloy thereof, or a laminated combination thereof. In an embodiment, the first adjustment layer or the second adjustment layer may have a multi-layer structure, and / or include a reflective layer (not shown), and may reflect more than 80% of the light emitted by the active layer 312. rate.

Figure 3C is a top view of a photovoltaic device 400 according to a second embodiment of the present invention. The manufacturing method, materials, and reference numerals used in this embodiment are the same as those in the first embodiment, and are not repeated here. In the embodiment of the present invention, the electrode design type may include the selection of the number of electrodes, the shape of the electrodes, and the positions of the electrodes, so as to improve the current spreading of the photovoltaic element 400 near the boundary region.

In an embodiment, the first semiconductor layer 311 of the photovoltaic element 400 has at least four boundaries, and two adjacent boundaries may form a corner, and there is no conductive structure crossing the boundaries. In this embodiment, the first first electrical electrode 321 is formed on any corner of the first semiconductor layer 311, and the second insulating layer 342 may have a second opening 3422 as the first first electrical electrode 321 is used for electrical connection with the third electrode 35 formed subsequently. The second first electrical electrode 322 is formed on the first semiconductor layer 311 and is surrounded by the second semiconductor layer 313. The second insulating layer 342 may also have a third opening 3423 as the second first electrical electrode. 322 is used for electrical connection with a third electrode 35 to be formed subsequently.

In this embodiment, the projection of the first first electrical electrode 321 on the first semiconductor layer 311 may have a pattern, wherein the pattern may be a polygon, a circle, an ellipse, a semicircle, or a shape Arc surface. The second first electrical electrode 322 is extended, and the shape may be a linear shape, an arc shape, a mixed shape of a linear shape and an arc shape, or may have at least one branch. In one embodiment, the second first electrical electrode 322 may have a head end and a tail end, and the head end may have a width greater than a width of the tail end.

In this embodiment, the third first electrical electrode 323 is formed on the first semiconductor layer 311 exposed beside the boundary of the photovoltaic element 400. In an embodiment, the third first electrical electrode 323 is not surrounded by the second semiconductor layer 313, and the second insulating layer 342 has a fourth opening 3424 to serve as the third first electrical electrode 323 and the first formed electrode. The three electrodes 35 are used for electrical connection. The fourth first electrical electrode 324 is formed on the first semiconductor layer 311 exposed near the boundary of the photovoltaic element 400. In an embodiment, the fourth first electrical electrode 324 is not surrounded by the second semiconductor layer 313, and the second insulating layer 342 has a fifth opening 3425 to serve as the fourth first electrical electrode 324 and a subsequently formed first electrode. The three electrodes 35 are used for electrical connection.

In this embodiment, the projection of the third first electrical electrode 323 on the first semiconductor layer 311 may have a figure, wherein the figure may be a polygon, a circle, an ellipse, a semicircle, or a shape Arc surface. The shape of the fourth first electrical electrode 324 may be a linear shape, an arc shape, a mixed shape of a linear shape and an arc shape, or may have at least one branch. In an embodiment, the fourth first electrical electrode 324 may have a head end and a tail end, and the head end may have a width greater than a width of the tail end. In one embodiment, the shapes of the third first electrical electrode 323 and the fourth first electrical electrode 324 are different.

In one embodiment, according to product design requirements, the first first electrical electrode 321 and the third first electrical electrode 323 may be formed beside the same boundary of the photovoltaic element 400 and separated from each other. In an embodiment, the first first electrical electrode 321 and the fourth first electrical electrode 324, or the third first electrical electrode 323 and the fourth first electrical electrode 324 are not formed on the same photovoltaic device 400. Beside the border.

In one embodiment, a head end of the fourth first electrical electrode 324 may be covered by the third electrode 35, and a tail end of the fourth first electrical electrode 324 may not be covered by the fourth electrode 36. In this embodiment, a projection area of the third electrode 35 on the first semiconductor layer 311 is larger than a projection area of the fourth electrode 36 on the first semiconductor layer 311, and the third electrode 35 and the fourth electrode 36 are on the first semiconductor The ratio of the projected area on layer 311 is between 110% and 120%. In one embodiment, the extending directions of the tail ends of the second first electrical electrode 322 and the fourth first electrical electrode 324 are substantially parallel to each other.

FIG. 4A is a top view showing a photovoltaic element 500 according to a third embodiment of the present invention. The manufacturing method, materials, and reference numerals used in this embodiment are the same as those in the first embodiment, and are not repeated here. In the embodiment of the present invention, the electrode design type may include the selection of the number of electrodes, the shape of the electrodes, and the positions of the electrodes, so as to improve the current spreading of the photovoltaic element 500 near the boundary region.

In this embodiment, the four borders of the photovoltaic element 500 form a rectangle, two adjacent borders can form a corner, and there is no conductive structure that crosses the border. The border has a first long side B1 and a second long side B3. A first short side B2 and a second short side B4. In one embodiment, the length of the first long side B1 or the second long side B3 is larger than the first short side B2 or the second short side B4. In this embodiment, the projections of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 are arranged along the first long side B1 or the second long side B3.

In this embodiment, two first first electrical electrodes 321 separated from each other are formed on two corners of the first short side B2, and the second insulating layer 342 may also have a second opening 3422 as The first first electrical electrode 321 is electrically connected to a third electrode 35 to be formed subsequently. The two fourth first electrical electrodes 324 are respectively located on the first semiconductor layer 311 exposed beside the boundaries of the first long side B1 and a second long side B3. In this embodiment, the third first electrical electrode 323 is formed on the first short side B2, and the second insulating layer 342 may also have a fourth opening 3424 as the third first electrical electrode 323 and The third electrode 35 formed subsequently is used for electrical connection. The fourth first electrical electrode 324 is not surrounded by the second semiconductor layer 313, and the second insulating layer 342 may also have a third opening 3423 to serve as the fourth first electrical electrode 324 and the third electrode 35 to be formed subsequently. For sexual connection.

In one embodiment, the distance between the third first electrical electrode 323 and the two first first electrical electrodes 321 is substantially equal. In addition, the first first electrical electrode 321, the fourth first electrical electrode 324, and the third electrode 35 can be formed in the same process.

In this embodiment, the projection of the first first electrical electrode 321 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle, or an arc surface. The projection of the third first electrical electrode 323 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle, or an arc surface. The fourth first electrical electrode 324 is extended, and may be linear, curved, mixed of linear and curved, or may have at least one branch. In an embodiment, the fourth first electrical electrode 324 has a head end and a tail end, and the head end may have a width greater than a width of the tail end. In one embodiment, the shapes of the third first electrical electrode 323 and the fourth first electrical electrode 324 are different.

In one embodiment, a head end of the fourth first electrical electrode 324 is directed to the first short side B2 and a tail end is directed to the second short side B4. In an embodiment, a head end of the fourth first electrical electrode 324 may be covered by the third electrode 35, and a tail end of the fourth first electrical electrode 324 may not be covered by the fourth electrode 36. In one embodiment, the extending directions of the tail ends of the two fourth first electrical electrodes 324 are substantially parallel to each other. In this embodiment, the projected area of the third electrode 35 on the first semiconductor layer 311 is larger than the projected area of the fourth electrode 36 on the first semiconductor layer 311; and the third electrode 35 and the fourth electrode 36 on the first semiconductor The ratio of the projected area on layer 311 is between 110% and 120%.

FIG. 4B is a top view showing a photovoltaic element 600 according to a fourth embodiment of the present invention. The manufacturing method, materials, and reference numerals used in this embodiment are the same as those in the first embodiment, and are not repeated here. In the embodiment of the present invention, the electrode design type may include the selection of the number of electrodes, the shape of the electrodes, and the positions of the electrodes, so as to improve the current spreading of the photovoltaic element 600 near the boundary region.

In this embodiment, the four borders of the photovoltaic element 600 form a rectangle, and two adjacent borders may form a corner, and there is no conductive structure crossing the borders. The photovoltaic element 600 has a first long side B1, a second long side B3, a first short side B2, and a second short side B4. In one embodiment, the length of the first long side B1 or the second long side B3 is larger than the first short side B2 or the second short side B4. In this embodiment, the projections of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 are arranged along the first long side B1 or the second long side B3.

In this embodiment, at least one first first electrical electrode 321 is included. In an embodiment, four first first electrical electrodes 321 may be formed on the four corners of the first semiconductor layer 311, and the second insulating layer 342 may also have a second opening 3422 as the first first An electrical electrode 321 is electrically connected to a third electrode 35 to be formed subsequently. Two second first electrical electrodes 322 are formed on the first semiconductor layer 311 and are surrounded by the second semiconductor layer 313. The second insulating layer 342 may also have a third opening 3423 as the second first electrical layer. The sexual electrode 322 is electrically connected to a third electrode 35 to be formed subsequently.

In this embodiment, the projection of the first first electrical electrode 321 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle, or an arc surface. The projection of the second first electrical electrode 322 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle or an arc surface. In an embodiment, the projection shapes of the two second first electrical electrodes 322 on the first semiconductor layer 311 may be the same or different.

In this embodiment, the third electrode 35 includes two extending portions 351, and the two extending portions 351 may form a notch R, and the fourth electrode 36 is located in the notch R. In addition, the first first electrical electrode 321, the second first electrical electrode 322, and the third electrode 35 can be formed in the same process.

FIG. 4C is a top view showing a photovoltaic element 700 according to a fifth embodiment of the present invention. The manufacturing method, materials, and reference numerals used in this embodiment are the same as those in the first embodiment, and are not repeated here. In the embodiment of the present invention, the electrode design type may include the selection of the number of electrodes, the shape of the electrodes, and the positions of the electrodes, so as to improve the current spreading of the photovoltaic element 700 near the boundary region.

In one embodiment, the first semiconductor layer 311 of the photovoltaic element 700 has at least four boundaries, and two adjacent boundaries may form a corner, and there is no conductive structure crossing the boundaries. In this embodiment, four first electrical electrodes 321 are formed on the four corners of the first semiconductor layer 311, and the second insulating layer 342 may also have a second opening 3422 as The first first electrical electrode 321 is electrically connected to a third electrode 35 to be formed subsequently. A plurality of second first electrical electrodes 322 are formed on the first semiconductor layer 311 and are surrounded by the second semiconductor layer 313. The second insulating layer 342 may also have a fourth opening 3424 as a second first electrical layer. The sexual electrode 322 is electrically connected to a third electrode 35 to be formed subsequently. The plurality of third first electrical electrodes 323 are formed on the first semiconductor layer 311 exposed near the boundary of the photovoltaic element 700. In other words, the third first electrical electrode 323 is not surrounded by the second semiconductor layer 313, and any one of the boundaries of the first semiconductor layer 311 may include one or more third first electrical electrodes 323. The second insulating layer 342 may have a third opening 3423 for electrically connecting the second first electrical electrode 322 and the third electrode 35 to be formed subsequently.

In this embodiment, the projection of the first first electrical electrode 321 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle, or an arc surface. The projection of the second first electrical electrode 322 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle or an arc surface. In one embodiment, the shape of the second first electrical electrode 322 may be extended, and an extending direction thereof may be parallel to an extending direction of the extending portion 351. The second first electrical electrode 322 may be linear, curved, mixed linear and curved, or may have at least one branch. In one embodiment, the projected areas of the plurality of second first electrical electrodes 322 on the first semiconductor layer 311 may be the same or different. The projection of the third first electrical electrode 323 on the first semiconductor layer 311 may have a figure, wherein the figure is a polygon, a circle, an ellipse, a semicircle, or an arc surface.

In this embodiment, the third electrode 35 includes three extensions 351, and the three extensions 351 may form two notches R, and two fourth electrodes 36 may be formed in the two notches R. . In this embodiment, at least one second first electrical electrode 322 may be formed in the extension portion 351.

In an embodiment, the projection shapes of the first, second, and third electrical electrodes 321, 322, and 323 on the first semiconductor layer 311 may be the same or different. In addition, the first first electrical electrode 321, the second first electrical electrode 322, the third first electrical electrode 323, and the third electrode 35 can also be formed in the same process.

Fig. 4D is a top view showing a photovoltaic element 700 'according to a sixth embodiment of the present invention. This embodiment is a possible variation of the fifth embodiment, and the manufacturing method, materials used, electrode design, and labeling are the same as those in the fifth embodiment, and are not described herein again.

In this embodiment, the second insulating layer 342 of the photovoltaic device 700 'has a plurality of first openings 3421' for electrically connecting the second electrical electrode 33 and a fourth electrode 36 to be formed subsequently. In this embodiment, the second insulation layer 342 has a plurality of first openings 3421, which can reduce the difference in height between the third electrode 35 and the fourth electrode 36, and reduce the chance of subsequent disconnection from forming a flip-chip structure with the carrier board or circuit element , Which in turn increases product yield.

5A to 5C are schematic diagrams of a light emitting module, and FIG. 5A is a perspective view showing a light emitting module. A light emitting module 800 may include a carrier 502, a photoelectric element (not shown), and a plurality of light emitting modules. Lenses 504, 506, 508, and 510, and two power supply terminals 512 and 514. The light emitting module 800 can be connected to a light emitting unit 540 described later.

5B-5C are cross-sectional views of a light-emitting module 800, and FIG. 8C is an enlarged view of an E area in FIG. 8B. The carrier 502 may include an upper carrier 503 and a download body 501, wherein a surface of the download body 501 may be in contact with the upper carrier 503. The lenses 504 and 508 are formed on the upper carrier 503. The upper carrier 503 may form at least one through hole 515, and the photovoltaic element 300 or other embodiments of the photovoltaic element (not shown) formed in the embodiment of the present invention may be formed in the above-mentioned through hole 515 and contact the download body 501, and be The glue 521 surrounds. A lens 508 is provided on the adhesive material 521, and the material of the adhesive material 521 may be a silicone resin, an epoxy resin, or other materials. In one embodiment, a reflective layer 519 may be formed on both sidewalls of the through hole 515 to increase light extraction efficiency; a metal layer 517 may be formed on the lower surface of the download body 501 to improve heat dissipation efficiency.

6A-6B are schematic diagrams 900 of a light source generating device. A light source generating device 900 may include a light emitting module 800, a light emitting unit 540, and a power supply system (not shown) to supply the light emitting module 800 with a current. And a control element (not shown) for controlling the power supply system (not shown). The light source generating device 900 may be a lighting device, such as a street light, a car light, or an indoor lighting light source, or a traffic light or a backlight light source of a backlight module in a flat panel display.

Figure 7 is a schematic diagram of a light bulb. The light bulb 1000 includes a housing 921, a lens 922, a lighting module 924, a bracket 925, a heat sink 926, a series connection portion 927, and an electrical series connector 928. The lighting module 924 includes a carrier 923, and the carrier 923 includes at least one of the optoelectronic elements 300 in the above embodiments or other optoelectronic elements (not shown).

Specifically, the substrate 30 is a growth and / or carrying foundation. The candidate material may include a conductive substrate or a non-conductive substrate, a light-transmitting substrate, or a light-opaque substrate. One of the conductive substrate materials may be germanium (Ge), gallium arsenide (GaAs), indium phosphorus (InP), silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO2), zinc oxide (ZnO) , Gallium nitride (GaN), aluminum nitride (AlN), metal. One of the light-transmitting substrate materials may be sapphire, lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, and diamond-like carbon (Diamond-Like Carbon; DLC), spinel (MgAl2O4), aluminum oxide (Al2O3), silicon oxide (SiOX), and lithium gallate (LiGaO2).

The epitaxial stack 31 includes a first semiconductor layer 311, an active layer 312, and a second semiconductor layer 313. The first semiconductor layer 311 and the second semiconductor layer 313 are, for example, a cladding layer or a confinement layer, and may have a single-layer or multi-layer structure. The first semiconductor layer 311 and the second semiconductor layer 313 are different in electrical properties, polarity, or dopants. The electrical selection can be a combination of at least any two of p-type, n-type, and i-type, which can be provided separately. The electrons and holes are combined in the active layer 312 to emit light. The materials of the first semiconductor layer 311, the active layer 312, and the second semiconductor layer 313 may include III-V semiconductor materials, such as AlxInyGa (1-xy) N or AlxInyGa (1-xy) P, where 0 ≦ x, y ≦ 1; (x + y) ≦ 1. According to the material of the active layer 312, the epitaxial stack can emit red light with a wavelength between 610 nm and 650 nm, green light with a wavelength between 530 nm and 570 nm, and a wavelength between 450 nm and 490 nm. Blue light, or ultraviolet light with a wavelength less than 400nm.

In another embodiment of the present invention, the photovoltaic element 300, 400, 500, 600, 700, and 700 'may be an epitaxial element or a light-emitting diode, and its light emission spectrum may be changed by changing the epitaxial stacked single layer. Or multiple layers of physical or chemical factors. The single-layer or multi-layer epitaxial laminate may be selected from the group consisting of aluminum (Al), gallium (Ga), indium (In), phosphorus (P), nitrogen (N), zinc (Zn), and oxygen (O). Group. The structure of the active layer 312 is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multilayer quantum well (multi- quantum well (MQW) structure. Moreover, adjusting the logarithm of the quantum wells of the active layer 312 can also change the emission wavelength.

In one embodiment of the present invention, a buffer layer (not shown) may be optionally included between the first semiconductor layer 311 and the substrate 30. This buffer layer is interposed between the two material systems, so that the material system of the substrate 30 "transitions" to the material system of the first semiconductor layer 311. As for the structure of the light emitting diode, on the one hand, the buffer layer is a material layer for matching the lattice between the two materials. On the other hand, the buffer layer can also be a single layer, multiple layers, or structure that is used to combine two types of materials or two separate structures. The materials that can be used include organic materials, inorganic materials, metals, and semiconductors. Selected structures are: reflective layer, thermally conductive layer, conductive layer, ohmic contact layer, anti-deformation layer, stress release layer, stress adjustment layer, bonding layer, wavelength Conversion layer and mechanical fixing structure. In one embodiment, the material of the buffer layer may be selected from aluminum nitride or gallium nitride, and the buffer layer may be formed by sputtering or atomic layer deposition (ALD).

A contact layer (not shown) may be selectively formed between the second semiconductor layer 313 and the second electrical electrode 33. Specifically, the contact layer may be an optical layer, an electrical layer, or a combination thereof. The optical layer system can change the electromagnetic radiation or light emitted from or into the active layer. As used herein, "change" refers to changing at least one optical characteristic of electromagnetic radiation or light. The aforementioned characteristics include, but are not limited to, frequency, wavelength, intensity, general efficiency, efficiency, color temperature, rendering index, and light field. (Light field), and angle of view. The electrical layer can make the voltage, resistance, voltage, and capacitance of at least one of the opposite sides of the contact layer change, the density, the distribution, or the tendency to change. The constituent materials of the contact layer include oxides, conductive oxides, transparent oxides, oxides with 50% or more penetrations, metal, relatively translucent metals, metals with 50% or more transmission, organic matter, At least one of an inorganic substance, a phosphor, a phosphor, a ceramic, a semiconductor, a doped semiconductor, and an undoped semiconductor. In some applications, the material of the contact layer is at least one of indium tin oxide, cadmium tin oxide, antimony tin oxide, indium zinc oxide, zinc aluminum oxide, and zinc tin oxide. Rhenium is a relatively light-transmitting genus, and its thickness is preferably about 0.005 μm to 0.6 μm.

Although the above drawings and descriptions only correspond to specific embodiments, however, the elements, implementations, design guidelines, and technical principles described or disclosed in each embodiment are inconsistent, contradictory, or difficult to implement together. In addition, we shall be free to refer, exchange, match, coordinate, or merge as needed. Although the present invention has been described as above, it is not intended to limit the scope, implementation order, or materials and manufacturing methods of the present invention. Various modifications and changes made without departing from the spirit and scope of the invention.

100, 200, 300, 400, 500, 600, 700, 700’‧‧‧ light-emitting elements

10‧‧‧ transparent substrate

12‧‧‧ semiconductor stack

14.E1, E2‧‧‧ electrodes

30‧‧‧ substrate

31‧‧‧Epitaxial stack

311‧‧‧first semiconductor layer

312‧‧‧active layer

313‧‧‧Second semiconductor layer

S‧‧‧ditch

341‧‧‧First insulation layer

342‧‧‧Second insulation layer

3421‧‧‧First opening

3422‧‧‧Second opening

3423‧‧‧ third opening

3424‧‧‧ Fourth opening

3425‧‧‧ fifth opening

321‧‧‧first first electrical electrode

322‧‧‧Second first electrical electrode

323‧‧‧third first electrical electrode

324‧‧‧Fourth first electrical electrode

33‧‧‧Second electrical electrode

35‧‧‧Third electrode

B1‧‧‧First long side

B3‧‧‧Second long side

B2‧‧‧first short side

B4‧‧‧Second Short Side

351‧‧‧long extension

R‧‧‧ notch

36‧‧‧ Fourth electrode

800‧‧‧light emitting module

501‧‧‧ download

502‧‧‧ carrier

503‧‧‧ on carrier

504, 506, 508, 510‧‧‧ lens

512, 514‧‧‧ Power Supply Terminal

515‧‧‧through hole

519‧‧‧Reflective layer

521‧‧‧Glue

540‧‧‧shell

900‧‧‧ light source generating device

1000‧‧‧ bulb

721‧‧‧shell

722‧‧‧lens

724‧‧‧lighting module

725‧‧‧Scaffold

726‧‧‧ Radiator

727‧‧‧Concatenation Department

728‧‧‧Electric connector

ABC‧‧‧ direction

D1‧‧‧distance

H1, H2‧‧‧ height

FIG. 1 is a structural diagram showing a side-view structural diagram of a conventional array photoelectric element;

FIG. 2 is a schematic diagram showing the structure of a conventional light emitting device;

FIG. 3A is a structural diagram showing a top structural diagram of a photovoltaic element unit according to an embodiment of the present invention; FIG.

FIG. 3B is a structural diagram showing a side structural diagram of a photovoltaic element unit according to an embodiment of the present invention; FIG.

FIG. 3C is a structural diagram showing a top structural diagram of a photovoltaic element unit according to another embodiment of the present invention; FIG.

4A-4D are structural diagrams showing a top structural diagram of a photovoltaic element unit according to another embodiment of the present invention;

5A-5C are schematic diagrams of a light emitting module;

Figures 6A-6B are schematic diagrams of a light source generating device; and

Figure 7 is a schematic diagram of a light bulb.

Claims (10)

A photovoltaic element includes: an epitaxial stack including a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer; a plurality of boundaries are exposed to expose the A first semiconductor layer, and two adjacent borders of the plurality of borders constitute a corner of the first semiconductor layer; a plurality of first first electrical electrodes are formed on the first semiconductor layer exposed by the plurality of borders, The plurality of first first electrical electrodes are separated from each other and are not surrounded by the second semiconductor layer; a third electrode is formed on the plurality of first first electrical electrodes and the second semiconductor layer; And one or more fourth electrodes are formed on the second semiconductor layer. The photovoltaic element according to item 1 of the scope of patent application, wherein the projection of any one of the plurality of first first electrical electrodes onto the first semiconductor layer includes a figure, and the figure includes a polygon , A circle, an oval, or a semicircle. The optoelectronic element according to item 1 of the scope of patent application, further comprising a plurality of second first electrical electrodes formed on the first semiconductor layer and surrounded by the second semiconductor layer, wherein the plurality of second An electrical electrode system is separated from each other. The optoelectronic element according to item 3 of the scope of patent application, wherein the projection of any one of the plurality of second first electrical electrodes onto the first semiconductor layer includes a figure, and the figure includes a polygon , A circle, an ellipse, a semicircle or an arc surface. According to the photovoltaic element described in item 3 of the scope of patent application, wherein the projection areas of the plurality of second first electrical electrodes on the first semiconductor layer are the same as viewed from above. According to the optoelectronic element described in item 3 of the scope of patent application, wherein the projection areas of the plurality of second first electrical electrodes on the first semiconductor layer are different from the top view. The photovoltaic element according to item 1 of the patent application scope, wherein the third electrode includes an extension portion that extends to the fourth electrode or the extension portion is located between the plurality of fourth electrodes. The photovoltaic element according to item 7 of the scope of patent application, wherein one of the plurality of second first electrical electrodes is formed in the extension portion. The photovoltaic element according to item 1 of the scope of patent application, wherein the plurality of first first electrical electrodes include a plurality of first first electrical electrodes formed on any boundary. According to the photovoltaic element described in item 1 of the patent application scope, when viewed from above, the area of one of the fourth electrodes is smaller than the area of one of the third electrodes.