TWI842276B - Optoelectronic device - Google Patents

Abstract

An optoelectronic device including a epitaxial stack including a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer formed on the active layer; multiple boundaries exposing the first semiconductor layer, two adjacent boundaries of the multiple boundaries forming a corner of the first semiconductor layer; first parts of a first conductive type electrodes formed on the first semiconductor layer exposed by the multiple boundaries, wherein the first parts of a first conductive type electrodes are separated from each other, and not surrounded by the second semiconductor layer; a third electrode formed on the first parts of a first conductive type electrodes and the second semiconductor layer; and one or more fourth electrodes formed on the second semiconductor layer.

Description

Optoelectronic components

The present invention relates to a photoelectric element, and more particularly to an electrode design of a photoelectric element.

The light-emitting diode (LED) emits light by utilizing the energy difference between electrons moving between n-type semiconductors and p-type semiconductors, releasing energy in the form of light. This light-emitting principle is different from the heat-emitting principle of incandescent lamps, so LEDs are called cold light sources. In addition, LEDs have advantages such as high durability, long life, light weight, and low power consumption. Therefore, the current lighting market has high hopes for LEDs and regards them as a new generation of lighting tools that have gradually replaced traditional light sources and are applied in various fields, such as traffic signs, backlight modules, street lighting, medical equipment, etc.

FIG. 1 is a schematic diagram of a conventional light-emitting element structure. As shown in FIG. 1 , the conventional light-emitting element 100 includes a transparent substrate 10, a semiconductor stack 12 on the transparent substrate 10, and at least one electrode 14 on the semiconductor stack 12, wherein the semiconductor stack 12 includes at least a first conductive semiconductor layer 120, an active layer 122, and a second conductive semiconductor layer 124 from top to bottom.

In addition, the light-emitting element 100 mentioned above can be further combined and connected with other elements to form a light-emitting apparatus. FIG. 2 is a schematic diagram of a known light-emitting device structure. As shown in FIG. 2, a light-emitting device 200 includes a sub-mount 20 having at least one circuit 202; at least one solder 22 is located on the above-mentioned sub-mount 20, and the above-mentioned light-emitting element 100 is bonded and fixed on the sub-mount 20 by the solder 22 and the substrate 10 of the light-emitting element 100 and the circuit 202 on the sub-mount 20 are electrically connected; and an electrical connection structure 24 is used to electrically connect the electrode 14 of the light-emitting element 100 and the circuit 202 on the sub-mount 20; wherein the above-mentioned sub-mount 20 can be a lead frame or a large-size mounting substrate to facilitate the circuit planning of the light-emitting device 200 and improve its heat dissipation effect.

A photoelectric element comprises: a first semiconductor layer having at least four boundaries, a first surface, and a second surface opposite to the first surface, wherein any two adjacent boundaries can form a corner; a second semiconductor layer formed on the first surface of the first semiconductor layer; a second electrical type electrode formed on the second semiconductor layer; and at least two first electrical type electrodes formed on the first surface of the first semiconductor layer, wherein the at least two first electrical type electrodes are separated from each other and form a design pattern.

The present invention discloses a light emitting element and a manufacturing method thereof. To make the description of the present invention more detailed and complete, please refer to the following description in conjunction with the illustrations of FIGS. 3A to 7 .

FIG. 3A and FIG. 3B show a top view and a side view of the optoelectronic device 300 of the first embodiment of the present invention. FIG. 3B shows a side view of the structure in the direction of A-B-C in FIG. 3A. The optoelectronic device 300 has a substrate 30. The substrate 30 is not limited to a single material, but can also be a composite substrate composed of a plurality of different materials. For example, the substrate 30 can include a first substrate (not shown) and a second substrate (not shown) that are bonded to each other.

An epitaxial stack 31 is formed on the substrate 30 by a conventional epitaxial growth process, including a first semiconductor layer 311 having a first surface 3111 and a second surface 3112 opposite to the first surface, an active layer 312 formed on the first surface 3111 of the first semiconductor layer 311, and a second semiconductor layer 313 formed on the active layer 312. Then, a portion of the epitaxial stack is selectively removed by a photolithography process technology to expose a portion of the first semiconductor layer 311 at the boundary of the optoelectronic device 300, and a trench S is formed in the optoelectronic device 300. In one embodiment, the trench S exposes a portion of the first semiconductor layer 311 and is surrounded by the second semiconductor layer 313. In one embodiment, the trench S is in a strip shape in the top view.

Next, a first insulating layer 341 is deposited on the surface of the epitaxial stack 31 of the optoelectronic element 300 and the sidewall of the trench S by using a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method.

Next, at least one first first conductivity electrode 321 is formed on the first semiconductor layer 311 exposed near the boundary of the optoelectronic element 300. In one embodiment, the first first conductivity electrode 321 is not surrounded by the second semiconductor layer 313, and a second first conductivity electrode 322 is formed in the trench S. In this embodiment, the separated first first conductivity electrode 321 and the second first conductivity electrode 322 form an electrode design type of a first conductivity electrode.

In the embodiment of the present invention, the electrode design type may include the selection of the number of electrodes, electrode shape and electrode position to enhance the current spreading near the boundary area of the optoelectronic element. For example, the electrode design type of the first electrical property electrode may include one or more first first electrical property electrodes 321 and one or more second first electrical property electrodes 322, and the second first electrical property electrode 322 is surrounded by the second semiconductor layer 313 when viewed from above, and is in an extended shape.

In one embodiment, the first semiconductor layer 311 of the optoelectronic device 300 has at least four boundaries, two adjacent boundaries can form a corner, and there is no conductive structure across the boundary. In this embodiment, the first first conductivity electrode 321 is formed at two corners on the same boundary of the optoelectronic device 300, separated from each other and does not cross the boundary of the optoelectronic device 300.

In one embodiment, the projection of the first first electrical type electrode 321 on the first semiconductor layer 311 may have a shape, which may be a polygon, a circle, an ellipse, a semicircle, or a circular arc surface. The second first electrical type electrode 322 may be linear, arc-shaped, a combination of linear and arc-shaped, or may have at least one branch. In one embodiment, the second first electrical type electrode 322 may have a head end and a tail end, and the head end has a width greater than a width of the tail end.

Next, a second conductivity electrode 33 is formed on the second semiconductor layer 313. In one embodiment, the ratio of the projection area of the second conductivity electrode 33 on the first semiconductor layer 311 to the upper surface area of the second semiconductor layer 313 is between 90% and 100%.

Afterwards, a second insulating layer 342 may be formed on the first first electrical electrode 321, the second first electrical electrode 322, the second electrical electrode 33 and a portion of the first insulating layer 341. The second insulating layer 342 may have a first opening 3421 for electrically connecting the second electrical electrode 33 with a fourth electrode 36 to be formed subsequently, and the second insulating layer 342 may also have a second opening 3422 for electrically connecting the first first electrical electrode 321 with a third electrode 35 to be formed subsequently. In one embodiment, the first insulating layer 341 or the second insulating layer 342 may completely cover the exposed first semiconductor layer 311.

In one embodiment, the first insulating layer 341 or the second insulating layer 342 may be a transparent insulating layer. The material of the first insulating layer 341 or the second insulating layer 342 may be an oxide, a nitride, or a polymer. The oxide may include aluminum oxide (Al2O3), silicon oxide (SiO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), or aluminum oxide (AlOx); the nitride may include aluminum nitride (AlN), silicon nitride (SiNx); the polymer may include polyimide or benzocyclobutane (BCB) or a composite combination thereof. In one embodiment, the first insulating layer 341 or the second insulating layer 342 may be a distributed Bragg reflector structure.

Finally, a third electrode 35 is formed on the second insulating layer 342, the first first electrical electrode 321, and the second first electrical electrode 322 and is electrically connected to the first first electrical electrode 321 and the second first electrical electrode 322; and a fourth electrode 36 is formed on the second insulating layer 342 and the second electrical electrode 33 and is electrically connected to the second electrical electrode 33. In one embodiment, when viewed from above, the ratio of the projection area of the third electrode 35 to the fourth electrode 36 on the first semiconductor layer 311 is between 80% and 100%.

In one embodiment, the third electrode 35 may only cover a portion of the first first conductivity type electrode 321 ; in another embodiment, the third electrode 35 may not cover the first first conductivity type electrode 321 at all.

In one embodiment, there is a height H1 from the upper edge of the third electrode 35 to the upper edge of the substrate 30, and there is a height H2 from the upper edge of the fourth electrode 36 to the upper edge of the substrate 30, and H1 is substantially equal to H2. In one embodiment, the difference between H1 and H2 is less than 5-10%. By adjusting the difference between H1 and H2, the probability of disconnection when the optoelectronic element 300 subsequently forms a flip-chip structure with a carrier or a circuit element can be reduced, thereby increasing the product yield. In one embodiment, the boundary of the third electrode 35 and the boundary of the fourth electrode 36 have a minimum distance D1, and D1 is greater than 50μm. In one embodiment, D1 can be 50-200μm or 100-200μm.

In one embodiment, the first first electrical electrode 321, the second first electrical electrode 322, the second electrical electrode 33, the third electrode 35 and the fourth electrode 36 may be a multi-layer structure, and/or include a reflective layer (not shown), and may have a reflectivity of more than 80% for the light emitted by the active layer 312. In one embodiment, the first first electrical electrode 321, the second first electrical electrode 322 and the third electrode 35 may also be formed in the same process. In one embodiment, the light emitted by the optoelectronic element 300 may be reflected by the first first electrical electrode 321, the second first electrical electrode 322, the second electrical electrode 33, the third electrode 35 or the fourth electrode 36 and leave the optoelectronic element 300 from the substrate 30 direction.

In order to achieve a certain conductivity, the material of the first first conductivity electrode 321, the second first conductivity electrode 322, the second conductivity electrode 33, the third electrode 35 and the fourth electrode 36 is preferably a metal, such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), tin (Sn), etc., their alloys or their stacked combinations.

In one embodiment, a carrier or a circuit element (not shown) may be provided, and a first carrier electrode (not shown) and a second carrier electrode (not shown) may be formed on the carrier or the circuit element by wire bonding or soldering. The first carrier electrode and the second carrier electrode may form a flip-chip structure with the third electrode 35 and the fourth electrode 36 of the optoelectronic element 300.

In one embodiment, a first adjustment layer (not shown) may be formed between the first first conductivity electrode 321, and/or the second first conductivity electrode 322 and the third electrode 35, and electrically connected to the first first conductivity electrode 321, and/or the second first conductivity electrode 322 and the third electrode 35. In one embodiment, a second adjustment layer (not shown) may be formed between the second conductivity electrode 33 and the fourth electrode 36, and electrically connected to the second conductivity electrode 33 and the fourth electrode 36. In this embodiment, the first adjustment layer and the second adjustment layer may have a height respectively, and because of the formation positions of the first adjustment layer and the second adjustment layer, the heights of the first adjustment layer and the second adjustment layer will affect the heights of H1 and H2. Therefore, by separately designing the formation height of the first adjustment layer and/or the second adjustment layer, the height difference between H1 and H2 can be reduced, and the probability of disconnection when the optoelectronic element 300 is subsequently formed with a substrate or a circuit element into a flip-chip structure can be reduced, thereby increasing the product yield. In one embodiment, the projection area of the first adjustment layer on the first semiconductor layer 311 is larger than the projection area of the third electrode 35 on the first semiconductor layer 311, or the projection area of the second adjustment layer on the first semiconductor layer 311 is larger than the projection area of the fourth electrode 36 on the first semiconductor layer 311. In one embodiment, the material of the first adjustment layer or the second adjustment layer is preferably a metal, such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), tin (Sn), etc., their alloys or stacked combinations. In one embodiment, the first adjustment layer or the second adjustment layer can be a multi-layer structure and/or include a reflective layer (not shown), and can have a reflectivity of more than 80% for the light emitted by the active layer 312.

FIG. 3C is a top view of the photoelectric element 400 of the second embodiment of the present invention. The manufacturing method, materials used and labels of this embodiment are the same as those of the first embodiment, and will not be repeated here. In the embodiment of the present invention, the electrode design type may include the selection of the number of electrodes, electrode shape and electrode position to enhance the current spreading near the boundary area of the photoelectric element 400.

In one embodiment, the first semiconductor layer 311 of the optoelectronic element 400 has at least four boundaries, two adjacent boundaries may form a corner, and there is no conductive structure crossing the boundary. In this embodiment, the first first electrical property electrode 321 is formed on any corner of the first semiconductor layer 311, and the second insulating layer 342 may have a second opening 3422 for electrically connecting the first first electrical property electrode 321 with the third electrode 35 formed subsequently. The second first electrical property electrode 322 is formed on the first semiconductor layer 311 and is surrounded by the second semiconductor layer 313, and the second insulating layer 342 may also have a third opening 3423 for electrically connecting the second first electrical property electrode 322 with the third electrode 35 formed subsequently.

In this embodiment, the projection of the first first electrical type electrode 321 on the first semiconductor layer 311 may have a shape, wherein the shape may be a polygon, a circle, an ellipse, a semicircle, or a circular arc surface. The second first electrical type electrode 322 is extended, and the shape may be linear, arc, a mixture of linear and arc, or may have at least one branch. In one embodiment, the second first electrical type electrode 322 may have a head end and a tail end, and the head end may have a width greater than a width of the tail end.

In this embodiment, the third first conductivity electrode 323 is formed on the first semiconductor layer 311 exposed at the boundary of the optoelectronic device 400. In one embodiment, the third first conductivity electrode 323 is not surrounded by the second semiconductor layer 313, and the second insulating layer 342 has a fourth opening 3424 for electrically connecting the third first conductivity electrode 323 with the third electrode 35 formed subsequently. The fourth first conductivity electrode 324 is formed on the first semiconductor layer 311 exposed at the boundary of the optoelectronic device 400. In one embodiment, the fourth first conductivity electrode 324 is not surrounded by the second semiconductor layer 313, and the second insulating layer 342 has a fifth opening 3425 for electrically connecting the fourth first conductivity electrode 324 to the third electrode 35 formed subsequently.

In this embodiment, the projection of the third first electrical property electrode 323 on the first semiconductor layer 311 may have a shape, wherein the shape may be a polygon, a circle, an ellipse, a semicircle, or have an arc surface. The shape of the fourth first electrical property electrode 324 may be linear, arc-shaped, a mixture of linear and arc-shaped, or may have at least one branch. In one embodiment, the fourth first electrical property electrode 324 may have a head end and a tail end, and the head end may have a width greater than a width of the tail end. In one embodiment, the third first electrical property electrode 323 and the fourth first electrical property electrode 324 have different shapes.

In one embodiment, according to the requirements of product design, the first first electrical electrode 321 and the third first electrical electrode 323 can be formed at the same boundary of the optoelectronic device 400 and separated from each other. In one embodiment, the first first electrical electrode 321 and the fourth first electrical electrode 324, or the third first electrical electrode 323 and the fourth first electrical electrode 324 are not formed at the same boundary of the optoelectronic device 400.

In one embodiment, the head end of the fourth first conductivity electrode 324 can be covered by the third electrode 35, and the tail end of the fourth first conductivity electrode 324 is not covered by the fourth electrode 36. In this embodiment, the projection area of the third electrode 35 on the first semiconductor layer 311 is larger than the projection area of the fourth electrode 36 on the first semiconductor layer 311, and the ratio of the projection areas of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 is between 110% and 120%. In one embodiment, the extension directions of the tail ends of the second first conductivity electrode 322 and the fourth first conductivity electrode 324 are substantially parallel to each other.

FIG. 4A is a top view of a photoelectric element 500 of the third embodiment of the present invention. The manufacturing method, materials used, and reference numerals of this embodiment are the same as those of the first embodiment, and will not be described in detail here. In the embodiment of the present invention, the electrode design may include the selection of the number of electrodes, the shape of electrodes, and the position of electrodes to enhance the current spreading near the boundary area of the photoelectric element 500.

In this embodiment, the four boundaries of the optoelectronic element 500 form a rectangle, two adjacent boundaries can form a corner, and there is no conductive structure crossing the boundaries, and the above-mentioned boundaries have a first long side B1, a second long side B3, a first short side B2 and a second short side B4. In one embodiment, the length of the above-mentioned first long side B1 or the second long side B3 is greater than the first short side B2 or the second short side B4. In this embodiment, the projections of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 are arranged along the first long side B1 or the second long side B3.

In the present embodiment, two first first electrical electrodes 321 separated from each other are formed on two corners of the first short side B2, and the second insulating layer 342 may also have a second opening 3422 for electrically connecting the first first electrical electrode 321 with the third electrode 35 to be formed subsequently. Two fourth first electrical electrodes 324 are respectively located on the first semiconductor layer 311 exposed at the boundaries of the first long side B1 and the second long side B3. In the present embodiment, the third first electrical electrode 323 is formed on the first short side B2, and the second insulating layer 342 may also have a fourth opening 3424 for electrically connecting the third first electrical electrode 323 with the third electrode 35 to be formed subsequently. The fourth first conductivity electrode 324 is not surrounded by the second semiconductor layer 313, and the second insulating layer 342 may also have a third opening 3423 for electrically connecting the fourth first conductivity electrode 324 with the third electrode 35 to be formed subsequently.

In one embodiment, the third first conductivity electrode 323 is substantially equal to the distance between the two first first conductivity electrodes 321. In addition, the first first conductivity electrode 321, the fourth first conductivity electrode 324, and the third electrode 35 can be formed in the same process.

In this embodiment, the projection of the first first electrical type electrode 321 on the first semiconductor layer 311 may have a shape, wherein the shape is a polygon, a circle, an ellipse, a semicircle, or has an arc surface. The projection of the third first electrical type electrode 323 on the first semiconductor layer 311 may have a shape, wherein the shape is a polygon, a circle, an ellipse, a semicircle, or has an arc surface. The fourth first electrical type electrode 324 is extended, and may be linear, arc-shaped, a mixture of linear and arc-shaped, or may have at least one branch. In one embodiment, the fourth first electrical type electrode 324 has a head end and a tail end, and the head end may have a width greater than a width of the tail end. In one embodiment, the third first conductivity type electrode 323 and the fourth first conductivity type electrode 324 have different shapes.

In one embodiment, the head end of the fourth first electrical type electrode 324 points to the first short side B2 and the tail end points to the second short side B4. In one embodiment, the head end of the fourth first electrical type electrode 324 can be covered by the third electrode 35, and the tail end of the fourth first electrical type electrode 324 is not covered by the fourth electrode 36. In one embodiment, the extension directions of the tail ends of the two fourth first electrical type electrodes 324 are substantially parallel to each other. In this embodiment, the projection area of the third electrode 35 on the first semiconductor layer 311 is larger than the projection area of the fourth electrode 36 on the first semiconductor layer 311; and the ratio of the projection areas of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 is between 110% and 120%.

FIG. 4B is a top view of the photoelectric element 600 of the fourth embodiment of the present invention. The manufacturing method, materials used and labels of this embodiment are the same as those of the first embodiment, and will not be repeated here. In the embodiment of the present invention, the electrode design type may include the selection of the number of electrodes, the shape of electrodes and the position of electrodes to enhance the current spreading near the boundary area of the photoelectric element 600.

In this embodiment, the four boundaries of the optoelectronic element 600 form a rectangle, two adjacent boundaries can form a corner, and there is no conductive structure crossing the boundary. The optoelectronic element 600 has a first long side B1, a second long side B3, a first short side B2 and a second short side B4. In one embodiment, the length of the first long side B1 or the second long side B3 is greater than the length of the first short side B2 or the second short side B4. In this embodiment, the projections of the third electrode 35 and the fourth electrode 36 on the first semiconductor layer 311 are arranged along the first long side B1 or the second long side B3.

In this embodiment, at least one first first electrical property electrode 321 is included. In one embodiment, four first first electrical property electrodes 321 may be formed on the four corners of the first semiconductor layer 311, and the second insulating layer 342 may also have a second opening 3422 for electrically connecting the first first electrical property electrode 321 with the third electrode 35 formed subsequently. Two second first electrical property electrodes 322 are formed on the first semiconductor layer 311 and are surrounded by the second semiconductor layer 313, and the second insulating layer 342 may also have a third opening 3423 for electrically connecting the second first electrical property electrode 322 with the third electrode 35 formed subsequently.

In this embodiment, the projection of the first first electrical type electrode 321 on the first semiconductor layer 311 may have a shape, wherein the shape is a polygon, a circle, an ellipse, a semicircle, or has an arc surface. The projection of the second first electrical type electrode 322 on the first semiconductor layer 311 may have a shape, wherein the shape is a polygon, a circle, an ellipse, a semicircle, or has an arc surface. In one embodiment, the projection shapes of the two second first electrical type electrodes 322 on the first semiconductor layer 311 may be the same or different.

In this embodiment, the third electrode 35 includes two extensions 351 , and the two extensions 351 can substantially form a notch R, and the fourth electrode 36 is located in the notch R. In addition, the first first conductivity electrode 321 , the second first conductivity electrode 322 and the third electrode 35 can be formed in the same process.

FIG. 4C is a top view of the optoelectronic device 700 of the fifth embodiment of the present invention. The manufacturing method, materials used and labels of this embodiment are the same as those of the first embodiment, and will not be repeated here. In the embodiment of the present invention, the electrode design type may include the selection of the number of electrodes, the shape of electrodes and the position of electrodes to enhance the current spreading near the boundary area of the optoelectronic device 700.

In one embodiment, the first semiconductor layer 311 of the optoelectronic element 700 has at least four boundaries, two adjacent boundaries can form a corner, and there is no conductive structure crossing the boundary. In this embodiment, four first first conductivity electrodes 321 are formed on the four corners of the first semiconductor layer 311, respectively, and the second insulating layer 342 can also have a second opening 3422 for electrical connection between the first first conductivity electrode 321 and the third electrode 35 formed subsequently. A plurality of second first electrical electrodes 322 are formed on the first semiconductor layer 311 and are surrounded by the second semiconductor layer 313, and the second insulating layer 342 may also have a fourth opening 3424 for electrically connecting the second first electrical electrodes 322 with the third electrode 35 formed subsequently. A plurality of third first electrical electrodes 323 are formed on the first semiconductor layer 311 exposed at the border of the optoelectronic element 700. In other words, the third first electrical electrodes 323 are not surrounded by the second semiconductor layer 313, and any border of the first semiconductor layer 311 may include one or more third first electrical electrodes 323. The second insulating layer 342 may have a third opening 3423 for electrically connecting the second first conductivity electrode 322 and the third electrode 35 to be formed subsequently.

In this embodiment, the projection of the first first electrical electrode 321 on the first semiconductor layer 311 may have a shape, wherein the shape is a polygon, a circle, an ellipse, a semicircle, or has an arc surface. The projection of the second first electrical electrode 322 on the first semiconductor layer 311 may have a shape, wherein the shape is a polygon, a circle, an ellipse, a semicircle, or has an arc surface. In one embodiment, the shape of the second first electrical electrode 322 may be an extension, and its extension direction may be parallel to the extension direction of the extension portion 351. The second first electrical electrode 322 may be linear, arc-shaped, a mixture of linear and arc-shaped, or may have at least one branch. In one embodiment, the projection areas of the above-mentioned plurality of second first electrical electrodes 322 on the first semiconductor layer 311 may be the same or different. The projection of the third first conductivity electrode 323 on the first semiconductor layer 311 may have a shape, wherein the shape is a polygon, a circle, an ellipse, a semicircle or has an arc surface.

In this embodiment, the third electrode 35 includes three extensions 351 , and the three extensions 351 may substantially form two notches R, and the two fourth electrodes 36 may be formed in the two notches R. In this embodiment, at least one second first conductivity electrode 322 may be formed in the extensions 351 .

In one embodiment, the projection shapes of the first first conductivity electrode 321, the second first conductivity electrode 322, and the third first conductivity electrode 323 on the first semiconductor layer 311 may be the same or different. In addition, the first first conductivity electrode 321, the second first conductivity electrode 322, the third first conductivity electrode 323, and the third electrode 35 may also be formed in the same process.

FIG. 4D is a top view of a photoelectric element 700' of the sixth embodiment of the present invention. This embodiment is a possible variation of the fifth embodiment, and its manufacturing method, materials used, electrode design and numbering are the same as those of the fifth embodiment, and will not be described in detail here.

In this embodiment, the second insulating layer 342 of the optoelectronic element 700' has a plurality of first openings 3421' for electrically connecting the second electrical electrode 33 with the fourth electrode 36 to be formed later. In this embodiment, the second insulating layer 342 has a plurality of first openings 3421, which can reduce the height difference between the third electrode 35 and the fourth electrode 36, reduce the probability of wire breakage when forming a flip-chip structure with a substrate or circuit element later, and thus increase the product yield.

FIG. 5A to FIG. 5C are schematic diagrams of a light emitting module, FIG. 5A is an external perspective view of a light emitting module, and a light emitting module 800 may include a carrier 502, a photoelectric element (not shown), a plurality of lenses 504, 506, 508 and 510, and two power supply terminals 512 and 514. This light emitting module 800 may be connected to the light emitting unit 540 described later.

Figures 5B-5C are cross-sectional views of a light-emitting module 800, wherein Figure 8C is an enlarged view of region E of Figure 8B. The carrier 502 may include an upper carrier 503 and a lower carrier 501, wherein a surface of the lower carrier 501 may be in contact with the upper carrier 503. Lenses 504 and 508 are formed on the upper carrier 503. The upper carrier 503 may form at least one through hole 515, and the optoelectronic element 300 formed according to the embodiment of the present invention or the optoelectronic element of other embodiments (not shown) may be formed in the through hole 515 and in contact with the lower carrier 501, and surrounded by a glue 521. A lens 508 is provided on the glue 521, wherein the material of the glue 521 may be silicone resin, epoxy resin or other materials. In one embodiment, a reflective layer 519 may be formed on both side walls of the through hole 515 to increase light extraction efficiency; and a metal layer 517 may be formed on the lower surface of the carrier 501 to enhance heat dissipation efficiency.

FIG. 6A-6B is a schematic diagram of a light source generating device 900. A light source generating device 900 may include a light module 800, a light unit 540, a power supply system (not shown) for supplying a current to the light module 800, and a control element (not shown) for controlling the power supply system (not shown). The light source generating device 900 may be a lighting device, such as a street lamp, a car lamp, or an indoor lighting source, or a traffic sign or a backlight light source of a backlight module in a flat panel display.

FIG. 7 is a schematic diagram of a light bulb. The light bulb 1000 includes a housing 921, a lens 922, a lighting module 924, a bracket 925, a heat sink 926, a serial connection portion 927 and an electrical serial connector 928. The lighting module 924 includes a carrier 923, and the carrier 923 includes at least one optoelectronic element 300 in the above embodiment or an optoelectronic element in other embodiments (not shown).

Specifically, the substrate 30 is a growth and/or support base. Candidate materials may include a conductive substrate or a non-conductive substrate, a transparent substrate or an opaque substrate. One of the conductive substrate materials may be germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), or metal. One of the transparent substrate materials can be sapphire, lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), glass, diamond, CVD diamond, diamond-like carbon (DLC), spinel (spinel, MgAl2O4), aluminum oxide (Al2O3), silicon oxide (SiOX) and lithium gallate (LiGaO2).

The epitaxial stack 31 includes a first semiconductor layer 311, an active layer 312, and a second semiconductor layer 313. The first semiconductor layer 311 and the second semiconductor layer 313 are, for example, cladding layers or confinement layers, and can be a single layer or a multi-layer structure. The first semiconductor layer 311 and the second semiconductor layer 313 are different in electrical properties, polarities, or dopants, and their electrical properties can be a combination of at least any two of p-type, n-type, and i-type, and can provide electrons and holes respectively, so that the electrons and holes are combined in the active layer 312 to emit light. The materials of the first semiconductor layer 311, the active layer 312, and the second semiconductor layer 313 may include III-V semiconductor materials, such as AlxInyGa(1-x-y)N or AlxInyGa(1-x-y)P, where 0≦x, y≦1; (x+y)≦1. Depending on the material of the active layer 312, the epitaxial stack may emit red light with a wavelength between 610 nm and 650 nm, green light with a wavelength between 530 nm and 570 nm, blue light with a wavelength between 450 nm and 490 nm, or ultraviolet light with a wavelength less than 400 nm.

In another embodiment of the present invention, the photoelectric element 300, 400, 500, 600, 700, 700' can be an epitaxial element or a light-emitting diode, and its luminous spectrum can be adjusted by changing the physical or chemical elements of the epitaxial stacking layer or multiple layers. The epitaxial stacking layer material of the single layer or multiple layers can be selected from the group consisting of aluminum (Al), gallium (Ga), indium (In), phosphorus (P), nitrogen (N), zinc (Zn) and oxygen (O). The structure of the active layer 312 is, for example, a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW) structure. Furthermore, adjusting the number of quantum wells in the active layer 312 can also change the emission wavelength.

In one embodiment of the present invention, a buffer layer (not shown) may be selectively included between the first semiconductor layer 311 and the substrate 30. The buffer layer is between the two material systems, so that the material system of the substrate 30 is "transitioned" to the material system of the first semiconductor layer 311. For the structure of the light-emitting diode, on the one hand, the buffer layer is used to reduce the lattice mismatch between the two materials. On the other hand, the buffer layer can also be a single layer, multiple layers or structure used to combine two materials or two separate structures, and the materials that can be used are such as organic materials, inorganic materials, metals, and semiconductors, etc.; the structures that can be used are such as reflective layers, thermal conductive layers, conductive layers, ohmic contact layers, anti-deformation layers, stress release layers, stress adjustment layers, bonding layers, wavelength conversion layers, and mechanical fixing structures, etc. In one embodiment, the material of the buffer layer can be selected from aluminum nitride or gallium nitride, and the buffer layer can be formed by sputtering or atomic layer deposition (ALD).

A contact layer (not shown) may be selectively formed between the second semiconductor layer 313 and the second electrical electrode 33. Specifically, the contact layer may be an optical layer, an electrical layer, or a combination of the two. The optical layer may change the electromagnetic radiation or light coming from or entering the active layer. The "change" referred to herein refers to changing at least one optical property of the electromagnetic radiation or light, and the aforementioned properties include but are not limited to frequency, wavelength, intensity, flux, efficiency, color temperature, color rendering index, light field, and angle of view. The electrical layer may cause the value, density, or distribution of at least one of the voltage, resistance, current, and capacitance between any set of opposite sides of the contact layer to change or have a tendency to change. The material of the contact layer includes at least one of oxide, conductive oxide, transparent oxide, oxide with a transmittance of 50% or more, metal, relatively transparent metal, metal with a transmittance of 50% or more, organic matter, inorganic matter, fluorescent material, phosphor, ceramic, semiconductor, doped semiconductor, and undoped semiconductor. In some applications, the material of the contact layer is at least one of indium oxide tin, cadmium oxide tin, antimony oxide tin, indium zinc oxide, zinc aluminum oxide, and zinc oxide tin. If it is a relatively transparent metal, its thickness is preferably about 0.005μm~0.6μm.

Although the above drawings and descriptions only correspond to specific embodiments, the components, implementation methods, design principles, and technical principles described or disclosed in each embodiment can be referenced, exchanged, matched, coordinated, or combined as needed, except when they conflict, contradict, or are difficult to implement together. Although the present invention has been described above, it is not intended to limit the scope, implementation sequence, or materials and process methods used in the present invention. Various modifications and changes made to the present invention are within the spirit and scope of the present invention.

100, 200, 300, 400, 500, 600, 700, 700': light emitting element

10: Transparent substrate

12: Semiconductor stacking

14. E1, E2: Electrodes

30: Substrate

31: Epitaxial stacking

311: first semiconductor layer

312: Active layer

313: Second semiconductor layer

S: Ditch

341: First insulation layer

342: Second insulation layer

3421: First opening

3422: Second opening

3423: The third opening

3424: The fourth opening

3425: The fifth opening

321: first first electrical type electrode

322: second first electrical type electrode

323: third first conductivity electrode

324: fourth first conductivity electrode

33: Second electrical electrode

35: Third electrode

B1: First long side

B3: Second longest side

B2: First short side

B4: Second short side

351: elongated extension

R: Notch

36: Fourth electrode

800: Light emitting module

501: Download

502: Carrier

503: Upload body

504, 506, 508, 510: Lens

512, 514: Power supply terminal

515:Through hole

519:Reflective layer

521: Rubber

540: Shell

900: Light source generating device

1000: Bulb

721: Shell

722: Lens

724: Lighting module

725: Bracket

726: Radiator

727: Serial connection

728:Electric connector

ABC: Direction

D1: Distance

H1, H2: Height

FIG. 1 is a structural diagram showing a side view of a conventional array optoelectronic device;

FIG2 is a schematic diagram showing a schematic diagram of a known light emitting device structure;

FIG. 3A is a structural diagram showing a top view of a photoelectric element unit according to an embodiment of the present invention;

FIG. 3B is a structural diagram showing a side view of a photoelectric element unit according to an embodiment of the present invention;

FIG. 3C is a structural diagram showing a top view of a photoelectric element unit according to another embodiment of the present invention;

Figures 4A-4D are structural diagrams showing a top view of a photoelectric element unit according to another embodiment of the present invention;

Figures 5A-5C are schematic diagrams of a light emitting module;

Figures 6A-6B are schematic diagrams showing a light source generating device; and

FIG. 7 is a schematic diagram of a light bulb.

700: Optoelectronic components

311: First semiconductor layer

321: first first electrical electrode

322: Second first electrical electrode

323: The third first electrical electrode

342: Second insulation layer

3422: Second opening

3423: The third opening

3424: The fourth opening

35: Third electrode

351: Extension

36: Fourth electrode

Claims (10)

A photoelectric element comprises: an epitaxial stack, comprising a first semiconductor layer, the first semiconductor layer having a first region and a second region connected to the first region, an active layer formed on the first region, and a second semiconductor layer formed on the active layer, wherein the second semiconductor layer and the active layer are not formed on the second region; a first electrical electrode formed on the second region and electrically connected to the first semiconductor layer; A second electrical type electrode is formed on the second semiconductor layer; a first adjustment layer is electrically connected to the first electrical type electrode; a second adjustment layer is formed on the second electrical type electrode; and a third electrode is electrically connected to the first semiconductor layer via the first electrical type electrode, wherein a projection area of the first adjustment layer on the first semiconductor layer is larger than a projection area of the third electrode on the first semiconductor layer. A photoelectric element comprises: an epitaxial stack, comprising a first semiconductor layer, the first semiconductor layer having a first region and a second region connected to the first region, an active layer formed on the first region, and a second semiconductor layer formed on the active layer, wherein the second semiconductor layer and the active layer are not formed on the second region; a plurality of first electrical type electrodes, including a first portion of the plurality of first electrical type electrodes formed on the second region and surrounded by the second semiconductor layer and a plurality of first electrical type electrodes of a second portion are formed on the second region, wherein a first distance between one of the plurality of first electrical type electrodes of the first portion and one of the plurality of first electrical type electrodes of the second portion is greater than a second distance between another of the plurality of first electrical type electrodes of the first portion and the one of the plurality of first electrical type electrodes of the second portion; and a third electrode, electrically connected to the first semiconductor layer through the plurality of first electrical type electrodes. The optoelectronic element as described in item 1 or 2 of the patent application further comprises a fourth electrode electrically connected to the second semiconductor layer. The optoelectronic element as described in item 3 of the patent application further comprises a contact layer located between the second semiconductor layer and the fourth electrode, wherein the contact layer comprises an oxide, a conductive oxide, or a transparent oxide. The optoelectronic element as described in item 3 of the patent application further comprises an insulating layer including a first opening for electrically connecting the fourth electrode to the second semiconductor layer and a second opening for electrically connecting the first electrical electrode to the first semiconductor layer, wherein the insulating layer comprises a distributed Bragg reflector structure. As described in item 3 of the patent application scope, the photoelectric element, wherein when viewed from above, a top-view area of the fourth electrode is smaller than a top-view area of the third electrode. The optoelectronic element as described in item 3 of the patent application scope, wherein a minimum distance between one boundary of the third electrode and one boundary of the fourth electrode is greater than 50μm. The optoelectronic element as described in item 1 of the patent application scope, wherein the first semiconductor layer includes two long sides and two short sides, any one of the long sides and one of the short sides constitutes a corner, and the first electrical electrode is formed on the corner of the first semiconductor layer, wherein the projection of the first electrical electrode on the first semiconductor layer has a shape, and the shape includes a polygon, a circle, an ellipse or a semicircle. The optoelectronic element as described in item 8 of the patent application further comprises another first electrical electrode close to one of the two long sides of the first semiconductor layer, wherein the other first electrical electrode comprises a head end and a tail end, and the head end comprises a width greater than a width of the tail end, wherein the first electrical electrode and the other first electrical electrode are separated from each other and do not touch each other. The optoelectronic element as described in item 9 of the patent application further comprises a fourth electrode electrically connected to the second semiconductor layer, wherein the head end of the other first electrical type electrode is covered by the third electrode, and the tail end is not covered by the third electrode and the fourth electrode.

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