CN105551971A - 基于Flip-chip连接的集成电路封装结构及封装工艺 - Google Patents
基于Flip-chip连接的集成电路封装结构及封装工艺 Download PDFInfo
- Publication number
- CN105551971A CN105551971A CN201510895922.8A CN201510895922A CN105551971A CN 105551971 A CN105551971 A CN 105551971A CN 201510895922 A CN201510895922 A CN 201510895922A CN 105551971 A CN105551971 A CN 105551971A
- Authority
- CN
- China
- Prior art keywords
- chip
- integrated circuit
- chamfering
- silver coating
- salient point
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 40
- 238000012536 packaging technology Methods 0.000 title abstract description 7
- 239000002184 metal Substances 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 26
- 238000005260 corrosion Methods 0.000 claims abstract description 11
- 230000007797 corrosion Effects 0.000 claims abstract description 11
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 33
- 238000007747 plating Methods 0.000 claims description 33
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 29
- 229910052709 silver Inorganic materials 0.000 claims description 29
- 239000004332 silver Substances 0.000 claims description 29
- 239000011248 coating agent Substances 0.000 claims description 26
- 238000000576 coating method Methods 0.000 claims description 26
- 229910052759 nickel Inorganic materials 0.000 claims description 16
- 238000000034 method Methods 0.000 claims description 14
- 230000011664 signaling Effects 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 abstract 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 abstract 3
- 239000010931 gold Substances 0.000 abstract 3
- 229910052737 gold Inorganic materials 0.000 abstract 3
- 229910052763 palladium Inorganic materials 0.000 abstract 3
- 239000003566 sealing material Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 description 13
- 239000000047 product Substances 0.000 description 13
- 239000005022 packaging material Substances 0.000 description 10
- 238000013461 design Methods 0.000 description 9
- 238000005538 encapsulation Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 239000003292 glue Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000004891 communication Methods 0.000 description 2
- 230000002860 competitive effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
本发明提供了一种基于Flip-chip连接的集成电路封装结构及封装工艺,包括有芯片、设于芯片上的金属凸点、镀镍钯金层和倒角镀银层、塑封体;所述倒角镀银层为相互独立的镀银层段,所述芯片上设有金属凸点,金属凸点、芯片、镀镍钯金层和倒角镀银层塑封于塑封体中,金属凸点、芯片、倒角镀银层和镀镍钯金层构成了电路的电源和信号通道。本发明同时提供了上述结构的封装工艺;极大地降低了框架在腐蚀变薄后,在模具内滑动的风险;同时,降低了塑封料压力,适用于集成电路封装中应用。
Description
技术领域
本发明属于集成电路封装技术领域,具体涉及一种基于Flip-chip连接的集成电路封装结构及封装工艺。
背景技术
集成电路扁平无引脚封装(QFN/DFN),在近几年随着通讯设备(如基站、交换机)、智能手机、便携式设备(如平板电脑)、可穿戴设备(如智能手表、智能眼镜、智能手环等)的普及而迅速发展,特别适用于有高频、高带宽、低噪声、高导热、小体积、高速度等电性需求的大规模集成电路的封装。集成电路扁平无引脚封装(QFN/DFN)有效地利用了引线脚的封装空间,从而大幅度地提高了封装效率。该封装由于引线短小、塑封体尺寸小、封装体薄,可以使CPU体积缩小30%-50%,同时具有良好的散热性能。传统的集成电路扁平无引脚封装封装(QFN/DFN)主要存在以下不足:一是设计及制作周期长,成本比较高;二是凸点的排布以及I/O的密集程度受到框架设计及框架制造工艺的限制;三是框架在腐蚀变薄后,在模具内有滑动的风险,封装可靠性得不到保障;四是传统的QFN/DFN产品厚度仍然比较大,无法满足当前的便携式设备对小体积、高密度封装的需求。传统的基于Flip-chip的QFN/DFN工艺流程为:框架镀银→晶圆减薄→划片→做金属凸点→倒装上芯→塑封→腐蚀框架→电镀→切割→包装。
发明内容
本发明提供了一种基于Flip-chip连接的免贴膜、免电镀的封装件及其制作工艺,同时降低了塑封料压力,增加了塑封料与金属框架的接合面积,封装可靠性大幅提升的基于Flip-chip连接的集成电路封装结构及封装工艺。
一种基于Flip-chip连接的集成电路封装结构,其特征是:包括有芯片、设于芯片上的金属凸点、镀镍钯金层和倒角镀银层、塑封体;所述倒角镀银层为相互独立的镀银层段,所述芯片上设有金属凸点,金属凸点、芯片、镀镍钯金层和倒角镀银层塑封于塑封体中,金属凸点、芯片、倒角镀银层和镀镍钯金层构成了电路的电源和信号通道。
一种基于Flip-chip连接的集成电路封装工艺,其特征是:包括有如下步骤:
a.在引线框的框架上镀镍钯金;
b.生长倒角镀银层;
c.对芯片进行晶圆减薄;
d.划片;
e.在引线框架上制作金属凸点;
f.采用倒装方式安装芯片于引线框上;
g.对上述结构进行塑封;
h腐蚀引线框的框架。
在上述工序完毕后,再对对塑封完毕的产品进行切割并进行包装。
更进一步的,b步骤中倒角镀银层是通过化学腐蚀法,使镀镍钯金层之上的镀银层形成倒角凹槽。
本发明可以实现的有益效果:生产产品前不再需要根据芯片尺寸及电路连通方式设计框架图形及加工框架,在引线框架制作过程中即可设计图形,使用普通的金属板即可制作产品,无需对金属板进行过多加工,制作周期短,极大降低成本。在很大程度上使目前集成电路扁平无引脚系列封装件不再被框架设计及制作工艺所局限,使得产品在凸点的排布以及I/O的密集程度上得到极大的提升。同时,在镀镍钯金层上镀一层银,并腐蚀成倒角形状,塑封之后形成有效的防拖拉结构,极大地降低了框架在腐蚀变薄后,在模具内滑动的风险,本发明采用普通框架即可进行产品制作流程,无需过多加工框架载体,缩短设计周期,降低成本。倒角镀银层和镀镍钯金层厚度仅1um,大大降低了QFN/DFN封装产品的厚度(QFN产品厚度可控制在0.35mm以内),而传统的QFN/DFN产品厚度在0.7mm以上。本发明提供的技术可使封装体厚度减小100%。在凸点排布及I/O数不受框架设计及制作限制的前提下,实现了凸点排布可任意定义,更好地实现芯片与载体的互连。在镀镍钯金层上镀一层银,并腐蚀成倒角形状,塑封之后形成有效的防拖拉结构,极大地降低了框架在腐蚀变薄后,在模具内滑动的风险;同时,降低了塑封料压力,增加了塑封料与金属框架的接合面积,封装可靠性大幅提升。本发明提供的封装件将镀镍钯金层作为与外部电路的信号连接通道,相当于普通封装的“管脚”,可以省去电镀环节。传统的QFN/DFN框架,为了防止塑封时发生“溢胶”,要在框架背面贴有一层膜;而本发明由于框架上面镀了一层镍钯金,可以起到隔离塑封料的作用,塑封后腐蚀掉框架,同样可以起到防止“溢胶”的作用,这样就可以省去框架厂商“贴膜”的过程。由于本发明提供的封装件可以免电镀、免贴膜,生产成本可以大幅降低,产品更有竞争力。
附图说明
图1为引线框架剖面图;
图2为引线框架镀镍钯金后剖面图;
图3为引线框架的镀镍钯金层上镀银并腐蚀出倒角后的剖面图;
图4为芯片减薄划片后的剖面图;
图5为芯片植金属凸点后的剖面图;
图6为倒装上芯后的剖面图;
图7为产品塑封后的剖面图;
图8为产品腐蚀框架后的剖面图;
图9为产品成品剖面图。
具体实施方式
如图9所示,一种基于Flip-chip连接的免贴膜、免电镀的封装件,所述封装件主要由金属凸点2、芯片3、塑封体4、倒角镀银层5、镀NiPdAu层6组成;所述倒角镀银层为相互独立的镀银层段,所述芯片上植有金属凸点,所述塑封体包围了金属凸点、芯片、镀NiPdAu层和倒角镀银层,金属凸点、芯片、倒角镀银层和镀NiPdAu层构成了电路的电源和信号通道。
一种基于Flip-chip连接的免贴膜、免电镀的封装件的主要工艺流程:框架镀NiPdAu→生长倒角镀银层(通过腐蚀,使镀NiPdAu层之上的镀银层形成如附图3所示的倒角凹槽)→晶圆减薄→划片→芯片做金属凸点→倒装上芯→塑封→腐蚀框架→切割→包装。
如图1至图9所示,一种基于框架镀银技术采用Flip-chip连接方式的封装件的制作工艺,按照以下步骤进行:
1)框架镀NiPdAu:在引线框架1的图形部分镀一层1um的NiPdAu层6;
2)生长倒角镀银层:在NiPdAu层6上生长一层20~30um的银层5,并腐蚀成倒角形状;
3)晶圆减薄:减薄厚度50um~200um,粗糙度Ra0.10mm~0.05mm;
4)划片:150um以上晶圆同普通集成电路扁平封装件划片工艺,但厚度在150um以下晶圆,使用双刀划片机及其工艺;
5)芯片上做金属凸点、上芯:在芯片3上用植球的方式作出金属凸点2,倒装上芯后经过倒角镀银层及镀NiPdAu与引线框架1连通;
6)塑封:同常规方法,塑封料填充满倒角镀银层的凹槽,形成有效的防拖拉结构,极大地提高了封装可靠性;
7)框架腐蚀:用化学溶液腐蚀掉全部引线框架1,露出镀NiPdAu层6;
8)切割、包装同常规方法。
在凸点排布及I/O数不受框架设计及制作限制的前提下,本发明通过电镀银之后倒装上芯的方法,实现了框架图形设计可在框架制作时期就完成,缩短了制作周期,更好地实现芯片与载体的互联,使I/O更加密集,成本更低。同时,增加了一层1um的NiPdAu层,使生产时免电镀;增加了一层20~30um的倒角镀银层,塑封之后,塑封料填充满倒角镀银层的凹槽,形成有效的防拖拉结构,同时降低了塑封料压力,增加了塑封料与金属框架的接合面积,提高了封装的可靠性。
本发明提供的封装件将镀NiPdAu层作为与外部电路的信号连接通道,相当于普通封装的“管脚”,可以省去电镀环节。传统的QFN/DFN框架,为了防止塑封时发生“溢胶”,在框架背面贴有一层膜;而本发明由于框架上面镀了一层NiPdAu,可以起到隔离塑封料的作用,塑封后腐蚀掉框架,同样可以起到防止“溢胶”的作用,这样就可以省去框架厂商“贴膜”的过程。由于本发明提供的封装件免电镀、免贴膜,生产成本可以大幅降低,产品更有竞争力。
Claims (3)
1.一种基于Flip-chip连接的集成电路封装结构,其特征是:包括有芯片、设于芯片上的金属凸点、镀镍钯金层和倒角镀银层、塑封体;所述倒角镀银层为相互独立的镀银层段,所述芯片上设有金属凸点,金属凸点、芯片、镀镍钯金层和倒角镀银层塑封于塑封体中,金属凸点、芯片、倒角镀银层和镀镍钯金层构成了电路的电源和信号通道。
2.一种基于Flip-chip连接的集成电路封装工艺,其特征是:包括有如下步骤:
a.在引线框的框架上镀镍钯金;
b.生长倒角镀银层;
c.对芯片进行晶圆减薄;
d.划片;
e.在引线框架上制作金属凸点;
f.采用倒装方式安装芯片于引线框上;
g.对上述结构进行塑封;
h.腐蚀引线框的框架。
3.根据权利要求2所述的一种基于Flip-chip连接的集成电路封装工艺,其特征是:b步骤中倒角镀银层是通过化学腐蚀法,使镀镍钯金层之上的镀银层形成倒角凹槽。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510895922.8A CN105551971A (zh) | 2015-12-08 | 2015-12-08 | 基于Flip-chip连接的集成电路封装结构及封装工艺 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201510895922.8A CN105551971A (zh) | 2015-12-08 | 2015-12-08 | 基于Flip-chip连接的集成电路封装结构及封装工艺 |
Publications (1)
Publication Number | Publication Date |
---|---|
CN105551971A true CN105551971A (zh) | 2016-05-04 |
Family
ID=55831082
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201510895922.8A Pending CN105551971A (zh) | 2015-12-08 | 2015-12-08 | 基于Flip-chip连接的集成电路封装结构及封装工艺 |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN105551971A (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112018058A (zh) * | 2020-09-08 | 2020-12-01 | 济南南知信息科技有限公司 | 一种电力逆变器模块及其制造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100129964A1 (en) * | 2008-11-26 | 2010-05-27 | Infineon Technologies Ag | Method of manufacturing a semiconductor package with a bump using a carrier |
CN103346140A (zh) * | 2013-06-10 | 2013-10-09 | 孙青秀 | 一种基于框架采用镀银技术的封装件及其制作工艺 |
CN204348715U (zh) * | 2015-01-05 | 2015-05-20 | 广东气派科技有限公司 | 一种超薄封装件 |
-
2015
- 2015-12-08 CN CN201510895922.8A patent/CN105551971A/zh active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20100129964A1 (en) * | 2008-11-26 | 2010-05-27 | Infineon Technologies Ag | Method of manufacturing a semiconductor package with a bump using a carrier |
CN103346140A (zh) * | 2013-06-10 | 2013-10-09 | 孙青秀 | 一种基于框架采用镀银技术的封装件及其制作工艺 |
CN204348715U (zh) * | 2015-01-05 | 2015-05-20 | 广东气派科技有限公司 | 一种超薄封装件 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112018058A (zh) * | 2020-09-08 | 2020-12-01 | 济南南知信息科技有限公司 | 一种电力逆变器模块及其制造方法 |
CN112018058B (zh) * | 2020-09-08 | 2021-09-24 | 南京宏景智能电网科技有限公司 | 一种电力逆变器模块及其制造方法 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN105514079A (zh) | 集成电路封装结构及其生产工艺 | |
CN103346135A (zh) | 一种基于框架采用键合线连接技术的封装件及其制作工艺 | |
CN102231372B (zh) | 多圈排列无载体ic芯片封装件及其生产方法 | |
CN204348715U (zh) | 一种超薄封装件 | |
CN105551971A (zh) | 基于Flip-chip连接的集成电路封装结构及封装工艺 | |
CN105470232A (zh) | 一种预包封引线框架的制造方法 | |
CN105895615A (zh) | 一种超薄封装元件及其制作工艺 | |
CN103021996A (zh) | 一种带有方形凹槽的冲压框架的扁平多芯片封装件及其制作方法 | |
CN101090077A (zh) | 半导体封装件及其制法 | |
CN105870100A (zh) | 一种超薄封装件及其制作工艺 | |
CN203260570U (zh) | 一种基于框架腐蚀凸点的无载体式新型封装件 | |
CN112349673A (zh) | 一种基于键合线连接的超薄封装件及其制作工艺 | |
CN102013419A (zh) | 一种微型射频模块封装用载带 | |
CN114300437A (zh) | 一种无框架的半导体封装结构及其制备工艺 | |
CN203690287U (zh) | 一种基于框架采用镀银技术的封装件 | |
CN103346140A (zh) | 一种基于框架采用镀银技术的封装件及其制作工艺 | |
CN203481213U (zh) | 一种基于框架采用键合线连接技术的封装件 | |
CN203589000U (zh) | 一种基于无框架csp封装背面植球塑封封装件 | |
CN203339152U (zh) | 一种基于冲压框架的单芯片扁平封装件 | |
CN204348707U (zh) | 一种超薄的封装元件 | |
CN112349674A (zh) | 一种基于Flip-chip连接的超薄封装件及其制作工艺 | |
CN204407321U (zh) | 一种多圈超薄封装件 | |
CN203103287U (zh) | 一种带有方形凹槽的冲压框架的扁平多芯片封装件 | |
CN216671626U (zh) | 一种无框架的半导体封装结构 | |
CN203481222U (zh) | 一种基于不同尺寸芯片采用植球优化技术的框架csp封装件 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160504 |